JPS6113899A - Time slot conversion system of digital trunk - Google Patents

Abstract

PURPOSE:To attain miniaturization at a low cost by providing a one-surface constitution time switch having memory of the number of time slots of an input PCM signal and one multiframe and reading and writing ascending and descending signal areas during an idle timing caused by the speed conversion. CONSTITUTION:A channel memory 20 is constituted of an ascending call area 50, an ascending signal area 51, a descending call area 52 and a descending signal area 53 and its total capacity goes to 224wX8 bits. A control memory 22 is constituted of an ascending area 60 and descending area 61, and its total capacity goes to 160wX8 bits. An address generation part 26 generates address information for executing read and write of the signal area corresponding to the channel memory based on the frame number. A PCM signal from a PCM transmitter writes signaling information in the ascending signal area with aid of the address information of the address generation part, while a PCM signal from a digital exchange reads out signaling information stored in the descending signal area with aid of the address information of the address generation part. As a result, the time slot conversion and the extraction, insertion and passing of the signal time slot are executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a time slot conversion method for digital trunks, and particularly for digital trunks that interface between a digital exchange and a PCM transmission device.
This relates to a time slot conversion method using call memory.

[Background of the Invention] Conventionally, digital exchange networks have adopted high-speed transmission, for example, 8.192 Mb/s, in order to increase the multiplicity of signals and to reduce the size and cost of equipment.

In addition, the transmission speed of the PCM transmission device in the CIEPT system is 2.048 Mb/S for the first order group and 8.448 Mb/S for the second order group when 64 Kb/s is taken as the 0th order group.
b/s.

For this reason, an interface unit (hereinafter referred to as a digital trunk) is used to connect a digital exchange (hereinafter referred to as a switch) and a PCM transmission device using PCM signals as they are.
HDB3 (High Density
Bipolar) -N RZ (Non Return)
Processing such as signal conversion, extraction/insertion of signal time slots, and speed conversion of audio time slots is performed.

Figure 2 is a PCM signal frame configuration diagram of the CEPT-1st order group between the PCM transmission device and the digital trunk, where 0 to 31 are time slot numbers (TSNO), and signal 1 is a synchronization signal or game alarm inserted. , Signal 2 is inserted with a signaling signal if the inter-office signaling system is a line individual signaling system, or a call or signaling signal is inserted if it is a common line signaling system. Figure 3 shows that the transmission speed between the exchange network and the digital trunk is 8.
．． This is a 192M b/s PCM signal frame configuration diagram, and the time slots TSN00-3.64-67 are used for the control channel between the exchange and the digital trunk, so the remaining 1 is used for speech signals and signaling signals.
It is transmitted by arbitrarily allocating it to 20 time slots.

FIG. 4 is a block diagram of a conventional digital trunk.

In FIG. 4, 1 is a PCM transmission device, 2A.

2B is a code converter, 3 is a signal time slot extractor,
4A, 4B are signal memories, 5A, 5B.

8A, 8B, IOA, IOB are address selectors, 6A
, 6B is a transmission speed converter, 7A and 7B are communication path memories,
9A and 9B are control memories, 11 is an exchange network, ] 2 is a signal time spot 1-insertion section, 13 is a return test section, 14 is a counter, and 15 is a microprocessor (M
PU), 16 is the exchange control device, J7 is the highway,
18 is a link line, and 19 is a digital trunk. Note that the network 11 of the exchange and each digital trunk are connected using a highway 17 with a transmission speed of 8.192 Mb/s.

The (upstream) PCM signal shown in FIG. 2 sent from the PCM transmission device 1 to the digital trunk 19 is sent to the code converter 2
The P'CM signal of the HDB 3 is converted into an NRZ signal at A, and then the signal time slots of T S No, O and TSNα16 are extracted by the signal time slot extractor 3, and the frame is sent from the counter 14 through the address selector 5A. It is written into the signal memory 4A at the address of the NO signal. Note that the contents of T S Nu O and 16 stored in the signal memory 4A are
is read out and sent to the control device 16 as control information via the link line 18. The call time slots of TSNα1 to 15 and 17 to 31 are
3 to the transmission rate converter 6A, and 2.048
Mb/s to 4x 8.192Mb/s
s from the counter 14 to the address selector 8A.
The timeslot number (T S No
) signals are sequentially written into the communication path memory 7A (sequential writing).

The MPU 15 writes the empty time slot number among the 120 time slots of the highway 17 allocated by the control device 16 to the location corresponding to the address in the control memory 9A through the address selector and OA. The empty time slot number stored in the control memory 9A is the address selector IO
T S specified by the counter 14 input through A
The address of the No signal is read out as the channel memory 7A address of the corresponding time slot position. Further, the signal is sent to the communication path memory 7A through the address selector 8A, and is then sent as a PCM signal of the corresponding address to the exchange network 11 via the highway 7 (random read).

On the contrary, the (down) PCM signal shown in FIG. 3 sent from the network 11 of the exchange to the digital trunk 19 passes through the highway 17, and the (up) call time slots are sequentially written into the channel memory 7A. Similarly, after being sequentially written in the channel memory 7B, random reading is performed, and the transmission rate converter 6B converts the data to 8.192M
',)/s to 2.048Mb/s. TSNα0 and 1 which are signal tie scores 1-
The control information to M P 6 is transmitted to M P
U ], 5 is the address corresponding to Frey lX number,
It is written at the same time as it is sent to the signal memory 4B through the address selector 5B, and the counter 14 outputs it to the address selector 5.
The address of the frame number signal sent through B is read out and sent to the signal time slot insertion section 12.

The signal time slot insertion section 12 sends the output of the transmission rate conversion section 6B to the code conversion section 2B during the call time slots (TSNα1 to 15 and 17 to 31), In between, the output of the signal memory 4B (the aforementioned control information) is sent to the code converter 2B.

The code converter 2B converts the received NRZ signal into HDB3P.
It is converted into a CM signal and sent to the PCM transmission device 1.

The operation described above is for the line individual signaling system, but in the case of the common line signaling system, the TSN of the signal time slot
Since α16 is used for data information for the common line or for communication, the communication channel memories 7A, 7B and control memories 9A, 9B are configured to be able to process TSN016 as well, and the signal time slot insertion unit 12
Configure TSN016 so that it can pass through. In other words, the call memories 7A and 7B have a capacity for 128 time slots.

The return test section 13 has a function for checking the normality of the connection between the exchange network 11 and the digital trunk 19, and temporarily stores any one time slot of the received (down) PCM signal. By inserting it into any one time slot of the (upstream) PCM signal and looping it back, the received PCM signal and the transmitted (downstream) PCM signal are checked against each other on the network 11 side of the exchange, and the signal is transmitted between the devices. connection status is confirmed.

Here, when calculating the capacity of each memory in FIG. 4, signal memory 4. A and 4B are 32w x 8bi each, since one frame has T S Na O and 16 2-tile slots, and 16 frames make up 1 multiframe.
The capacity of 1 channel memory 7A, 7B of t is 8.192M.
b/s 1 frame (128 time slots 1), each with a capacity of 128 wX 8 bits,
Since the control memories 9A and 9B require 128 addresses, each requires a capacity of 128w×7bjF', and a total of 4.352 bits. Furthermore, since it is composed of six memories, six sets of control circuits such as address selectors are also required.

Furthermore, in order to perform a test in which multiple time slots are folded simultaneously, multiple sets of memory ICs and control circuits are required, resulting in drawbacks such as a large number of parts, high cost, and inability to downsize.

[Purpose of the invention]

The purpose of the present invention is to eliminate such conventional drawbacks, reduce the number of parts without using special circuit parts, and create an interface between a PCM transmission device and a network of exchanges that can be made smaller at low cost. An object of the present invention is to provide a time slot conversion method for digital trunks.

[Summary of the invention]

In order to achieve the above object, the digital trunk time slot conversion method of the present invention has a communication channel memory and a control memory, and in a digital trunk that connects a digital exchange and a PCM transmission device, the upstream and downstream communication areas are and an address creation unit that creates address information for reading/writing a signal area to the communication path memory having a signal (signaling) area for one multiframe or more based on a frame number, Signaling information is written in the uplink signal area using the PCM signal from the address generator using the address information from the address generator, while signaling information stored in the downstream signal area using the PCM signal from the digital exchange is read using the address information from the address generator. The characteristic is that time slot conversion and signal time slot extraction, insertion and passing are performed by outputting the signal time slot.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a digital trunk showing an embodiment of the present invention, and FIG. 5(a) shows a block diagram of a digital trunk.

(b) is an area allocation diagram of the communication path memory and control memory, respectively, and FIG. 6 is a diagram of the read/write timing allocation diagram of the communication path memory.

In FIG. 1, 2o is a channel memory, 21, 23 is an address selector, 22 is a control memory, 24 is a multiplexer, 25 is a demultiplexer, 26 is an address generator, and 27 is a digital trunk.

As shown in FIG. 5(a), the communication path memory 20 includes an uplink communication area 50-) (32wX 5bit), an uplink signal area 51→(32wX 8bit), a downlink communication area 52→(128wX 8bit), and a downlink signal area. 53 (32w x 8bit). In the above explanation, the number in parentheses indicates the capacity, and the total is 224w
8 bits (1,792 bits). In addition, the control memory 22 stores the upstream area 6 as shown in FIG. 5(b).
0 (128wX8bit) and downstream area 61 (32w
It is configured with X8bi). The total capacity is 160
w x 8 bits (1280 bits).

As shown in FIG. 6, the writing and reading timing in the call memory 20 is one time slot of the CPET primary group (i.e., 125 μs ÷ 32 = 3.906 n
s ) into 16 parts (0-1 as timing numbers)
5) (244 ns), the processing is carried out to distinguish whether the processing time slot is for a call or for a signal.

Also, the transmission speed is 8.192M b / s and 2.0
48M b/S has a speed difference of 4 times, so 2
．． 8 for one time slot of 048 Mb/s
．． In order to allocate four time slots of 192M b/S, timing numbers 0 to 3 are set to 4N, timing numbers 4 to 7 are set to 4N+1.
Assign 8 to 11 to 4N+2.12 to 15 to 4N+3, and 8. ], 992 Mb/s time slot.

As a result, when processing call time slots (TSNnl~15 and 17~31), 2
．． 048Mb/s to 8.192Mb/s
Since the speed is converted to 2.048 Mb/s (3,906 ns'), writing to the uplink communication area 50 (input from the PCM transmission device 1) is performed once, and reading is performed once. (How to exit to Highway 17) is done 4 times.

Here, writing is performed at timing number 0, and reading is performed at timing numbers 1, 5, 9, and 13, respectively.

For one downlink, 2.048Mb from speed conversion
During one time slot of /s (3,906ns), writing to the downlink communication area 52 is performed four times and reading is performed once.
．． 14, and readout is also performed at timing number 3.

In addition, reading of the uplink signal area 51 and downlink signal area 53
The write timing is only when requested by the MPU 15.
These are performed at timing numbers 8 and 15, respectively (Figure 6 shows tree 1).
), which are executed twice in each frame.

When processing signal time slots (TSNo. 0 and 16), in the line individual signaling system, time slots O and 1
In addition, in the common line signaling method, in order to extract and insert time slot O and pass through time slot 16 (for example, handing over to network 11), both of the above two methods use uplink ( TSNoO and 16
), the uplink communication area 50 is used for passing.
is written with timing number O, and further, as extraction, is written into the upstream signal area 51 with timing number 4.

On the other hand, for the downlink of T S Nn Q and 16 of the line individual signaling system and TSNoO of the common line signaling system, the downlink signal area 53 is read out at timing number 3 in order to perform insertion. However, for the downlink of TS No. 16 of the common line signaling system, the downlink communication area 52 is read out at the same timing number 3 as described above in order to pass it (indicated by *2 in FIG. 6).

Note that writing and reading of timing numbers other than timing numbers 3 and 4 during the above processing are the same as those during the above-mentioned call time spot 1 to processing.

Next, the operation of the digital trunk shown in FIG. 4 will be explained with reference to FIGS. 5(a), (b), and FIG. 6.

2,048M b / transmitted by PCM transmission device 1
The PC'M signal of S is converted to NRZ by the code converter 2A.
After being converted into a signal, the T SN from the counter 14 at timing number O for each of TSN&1 to 3I during call time slot processing.

The signals are sequentially written into the upstream communication area 50 of the communication path memory 20 shown in FIG. 5(a) (sequential writing). Also, MPU
Reference numeral 15 indicates, in response to an instruction from the control device 16, a communication area read address, that is, an address in the communication path memory 20 corresponding to an empty time slot in Highway 7, in the upstream area 60 of the control memory 22 shown in FIG. 5(b). Write.

The above address is 8,192M output by the counter 14.
The T S No signal of b/s is output from the address selector 23 and is controlled at timing numbers 1, 5, and 9.13 by the operation of the timing control circuit (not shown in FIG. 4). It is read out by sending it to the memory 22 and is read out through the address selector 21 and sent to the communication path memory 20.
sent to. The call information is sent from the call path memory 20 in the lj, 192 Mb/s time slot corresponding to the above address, and sent to the exchange network 11 via the demultiplexer 25 and the highway 17 (random read).

On the other hand, in the case of signal time slot processing, in the same way as the above processing, at timing number 0, the uplink communication area 5
0 with the corresponding addresses of TS Nos. 0 and 16, and use them for passing.Furthermore, at timing number 4, the address generation unit 26 writes frame N from the counter 14 for extraction.

By converting the signal into address information corresponding to the uplink signal area 51 of the communication path memory 20 and sending it to the communication path memory 20 through the address selector 21, the uplink signal area 5
1 with T S Na O and the appropriate address of 16. PCM written in the above uplink signal area 51
The signal data is ADDRESS and DATA2 from the MPU 15 at timing number 15 (with tree 1).
and is sent to the control device 16 via the link line 18.

Conversely, from switch network 11 to highway 17
and 8, 19 sent through multiplexer 24
2M b/s PCM signal is 2,6°10.1
At timing number 4, the data is sequentially written into the downlink communication area 52. On the other hand, in the down signal area 53, the control device 1
The MPU 15 that received the instruction of 6 is written at timing number 8 using the ADDRESS and DADA1 lines. The above-mentioned downlink call area 52 and downlink signal area 53 are read out as follows.

When processing a call time slot and a signal time slot (TS No. 16) in the common line signaling system, at timing number 3, the downlink call area read address stored in the control memory 22 is read out by the counter 14 T S N
By sending the o signal to the communication path memory 2o,
The downlink communication area 52 is read out and sent to the code converter 2B via the demultiplexer 25. On the other hand, when processing a signal time slot (TSN no. 16) (however, only T S Na O in the common line signaling system), at timing number 3, the address generation unit 26 sets the counter 1.
By converting the frame NO signal of No. 4 into address information corresponding to the downlink signal area 53 of the communication path memory 2o and sending it to the communication path memory 2° through the address selector 21,
The downlink signal area 53 is read out and sent to the code converter 2B via the demultiplexer 25.

The code converter 2B converts the NRZ signal into an HDB3 signal from the channel memory 2o and sends it to the PCM transmission device 1.

Next, a multiple time slot simultaneous repeat test performed on the digital trunk 27 will be described.

The MPU 15 receiving the instruction from the control device 16 writes a downlink call area read address to be sent to the call path memory 20 in the uplink area 6o of the control memory 22. - Read out the read address written in the uplink call area read timing at timing number 1,5.9°13, and read any plurality of time slots of the PCM signal sent from the highway 17 from the call path memory 20 to the highway. The test can be performed by inserting the PCM signal into an arbitrary time slot of the PCM signal sent to No. 17 and looping it back.

Also, the communication path memory 2 is stored in the downstream area 61 of the control memory 22.
By writing the "Niri call area read address of 0",
The uplink communication area 50 is read at the downlink communication area read timing (timing number 3), and the arbitrary time slots 1 to 1 of the PCM signal sent from the PCM transmission device 1 are PCMed again.
It can also be looped back to the transmission device 1.

In this way, 6 memories (total capacity 4.352 bits)
2) time slot conversion, speed conversion, signal time slot extraction, and insertion of communication time slots in digital trunks, which were realized in the above configuration.

In addition, simultaneous repeat testing of multiple time slots can be realized with the configuration of two memories (total capacity: 3.272 bits) in this embodiment. Additionally, control circuits for each memory can be integrated, reducing the number of components and improving reliability.

〔Effect of the invention〕

As explained above, according to the present invention, a digital trunk is provided with a time switch having a -plane configuration, which has the number of time slots of an input PCM signal and a memory for one multiframe. By performing reading/writing during the idle timing generated by speed conversion, it is possible to realize a lower cost and smaller size of the trunk device.

[Brief explanation of drawings]

Figure 1 is a configuration block diagram of a digital trunk showing an embodiment of the present invention, Figure 2 is a diagram of the PCM signal frame configuration of the CEPT-1st order group, and Figure 3 is a transmission rate of 8.192M.
b/s PCM signal frame configuration diagram, Figure 4 is a configuration block diagram of a conventional digital trunk, Figures 5 (a), (
b) are respective communication path memories. FIG. 6 is an area layout diagram of the control memory, and FIG. 6 is a diagram showing the read/write timing layout of the communication path memory. 1...I) CM transmission device, 2A, 2B... code conversion unit, 3... signal tie 11 slot extraction unit, 4A,
4B...signal memory, 5A, 5B,
8 A, 8 B, 10 A. 10B, 21.23...address selector, 6A. 6B...Transmission speed converter, 7A, 7B, 20...Call path memory, 9A, 9B...Control memory, 11...Network of exchange, 12...Signal time slot insertion unit, 13...・Return test section, 14... counter,
I5...MPU, 16...Control device, 17...Highway, 18...Link line, 19.27...Digital trunk, 24...Multiplexer, 25...
Demulti■ 1 Zuyu 2I211

Claims (1)

[Scope of Claims] 1. In a digital trunk that has a communication channel memory and a control memory and connects a digital converter and a PCM transmission device, the uplink and downlink communication areas and signals of one multiframe or more (signaling ) area, the address generation unit generates address information for reading/writing a signal area based on a frame number, and the address generation unit generates signaling information using a PCM signal from a PCM transmission device. , the address information of the address generation section is written in the uplink signal area, and the signaling information stored in the downlink signal area is read out using the address information of the address generation section using the PCM signal from the digital exchange. A digital trunk time slot conversion method characterized by slot conversion and extraction, insertion, and passing of signal time slots. 2. In the description in paragraph 1, the above-mentioned communication path memory includes an uplink P
Write uplink communication area for CM signal, write uplink signal area, read uplink communication area, read uplink signal area, write downlink communication area for downlink PCM signal, write downlink signal area 7 of reading the downlink signal area or downlink call area
2. The digital trunk time slot conversion method according to claim 1, wherein the digital trunk time slot conversion method is operated periodically at two timings. 3. In the description of item 1, the communication path memory is configured to read/write the communication area at timing n (an integer of 2 or more) in order to convert the uplink and downlink transmission speeds of the PCM signal. 2. The digital trunk time slot conversion system according to claim 1, wherein one timing corresponds to a write (or read) operation. 4. In the above-mentioned item 1, in order to perform a simultaneous repetition test of multiple time slots, the downlink (or uplink) communication area is read out at the read timing of the uplink (or downlink) communication area. A digital trunk time slot conversion system according to claim 1, characterized in that: 5. In the description of paragraph 1, the communication path memory is a digital converter (when the transmission speed is n (an integer of 2 or more) times that of the PCM transmission device, writing of the upstream signal area, reading of the upstream signal area, and downlink signal 2. The digital trunk time slot conversion method according to claim 1, wherein the operation speed is halved by writing the area during an empty timing resulting from speed conversion.