JPH07326866A - Dielectric board module - Google Patents

Dielectric board module

Info

Publication number
JPH07326866A
JPH07326866A JP6117863A JP11786394A JPH07326866A JP H07326866 A JPH07326866 A JP H07326866A JP 6117863 A JP6117863 A JP 6117863A JP 11786394 A JP11786394 A JP 11786394A JP H07326866 A JPH07326866 A JP H07326866A
Authority
JP
Japan
Prior art keywords
dielectric substrate
layer
dielectric board
heat dissipation
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6117863A
Other languages
Japanese (ja)
Inventor
Hiroshi Toki
博史 土基
Hideshi Suzaki
秀史 須崎
Toshiaki Yamanaka
利晃 山中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP6117863A priority Critical patent/JPH07326866A/en
Publication of JPH07326866A publication Critical patent/JPH07326866A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To provide a dielectric board module which is high enough in heat dissipating properties and strength. CONSTITUTION:A dielectric board module 100 is formed through such a manner that dielectric board layers 1, 3, 5, and 7 and GND layers 2, 4, and 6 are laminated, wiring patterns 1i, 3i, and 5i are buried in the dielectric board layers 1, 3, and 5, a wiring pattern 1s is formed on the surface of the dielectric board layer 1, an active device chip 8 is mounted thereon, and two heat transfer members 9 extending from the active device chip 8 to the GND layer 2 are buried in the dielectric board layer 1. Heat released from the active device chip 8 is transmitted to the GND layer 2 through the intermediary of the heat transfer members 9, then transferred to the dielectric board 1 from the GND layer 2, and then dissipated into the air from the dielectric board 1. By this setup, a dielectric board module of this constitution is enhanced enough in heat dissipation capacity, so that an active device can be prevented from deteriorating in characteristics. No holes are bored in a dielectric board, so that the board is kept high in mechanical strength.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、誘電体基板モジュー
ルに関し、さらに詳しくは、誘電体基板の表面に実装し
た能動素子チップの熱を十分に放散できるように改良し
た誘電体基板モジュールに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric substrate module, and more particularly to a dielectric substrate module improved so that heat of an active element chip mounted on the surface of a dielectric substrate can be sufficiently dissipated.

【0002】[0002]

【従来の技術】図4は、従来の誘電体基板モジュールの
一例を示した断面図である。この誘電体基板モジュール
400は、誘電体基板1,3,5,7と、GND層2,
4,6とを積層し、前記誘電体基板層1,3,5中に配
線パターン1i,3i,5iを埋設すると共に、前記誘
電体基板層1の表面に配線パターン1sを形成し且つ能
動素子チップ8を実装した構造である。前記誘電体基板
1,3,5,7は、セラミックである。前記GND層
2,4,6および配線パターン1i,3i,5i,1s
は、銅箔である。前記能動素子チップ8は、FET(電
界効果トランジスタ)やMMIC(モノリシックマイク
ロ波集積回路)のベアチップ(bear chip)である。
2. Description of the Related Art FIG. 4 is a sectional view showing an example of a conventional dielectric substrate module. This dielectric substrate module 400 includes a dielectric substrate 1, 3, 5, 7 and a GND layer 2,
4 and 6 are laminated, the wiring patterns 1i, 3i and 5i are embedded in the dielectric substrate layers 1, 3 and 5, and the wiring pattern 1s is formed on the surface of the dielectric substrate layer 1 and the active element is formed. This is a structure in which the chip 8 is mounted. The dielectric substrates 1, 3, 5, 7 are ceramics. The GND layers 2, 4, 6 and the wiring patterns 1i, 3i, 5i, 1s
Is a copper foil. The active element chip 8 is a bare chip of FET (field effect transistor) or MMIC (monolithic microwave integrated circuit).

【0003】図5は、従来の誘電体基板モジュールの他
の一例を示した断面図である。この誘電体基板モジュー
ル500は、誘電体基板1,3,5,7と、GND層
2,4,6とを積層し、前記誘電体基板層1,3,5中
に配線パターン1i,3i,5iを埋設すると共に、前
記誘電体基板層1の表面に配線パターン1sを形成し、
放熱ブロック取付孔50を穿設し、その放熱ブロック取
付孔50に放熱ブロック60を嵌入して誘電体基板7に
取り付け、放熱ブロック60上に能動素子チップ8を実
装した構造である。前記放熱ブロック60は、アルミニ
ウムである。
FIG. 5 is a sectional view showing another example of a conventional dielectric substrate module. This dielectric substrate module 500 is a stack of dielectric substrates 1, 3, 5, 7 and GND layers 2, 4, 6, and wiring patterns 1i, 3i, in the dielectric substrate layers 1, 3, 5 are laminated. 5i is buried and a wiring pattern 1s is formed on the surface of the dielectric substrate layer 1,
The heat dissipation block mounting hole 50 is provided, the heat dissipation block 60 is fitted into the heat dissipation block mounting hole 50, and the heat dissipation block 60 is mounted on the dielectric substrate 7, and the active element chip 8 is mounted on the heat dissipation block 60. The heat dissipation block 60 is aluminum.

【0004】[0004]

【発明が解決しようとする課題】上記従来の誘電体基板
モジュール400では、能動素子チップ8で発生した熱
は、直接的に空気中に放散されると共に、誘電体基板層
1に伝わってから間接的に空気中に放散される。しか
し、誘電体基板1は熱伝導性が低いため、能動素子チッ
プ8の熱を十分に放散できない問題点がある。一方、上
記従来の誘電体基板モジュール500では、能動素子チ
ップ8で発生した熱は、直接的に空気中に放散されると
共に、放熱ブロック60に伝わってから間接的に空気中
に放散される。この放熱ブロック60は熱伝導性が高い
ため、能動素子チップ8の熱を十分に放散することが出
来る。しかし、放熱ブロック取付孔50を穿設するた
め、基板強度が低下する問題点がある。そこで、この発
明の目的は、十分に放熱でき且つ基板強度を低下させな
いように改良した誘電体基板モジュールを提供すること
にある。
In the above-mentioned conventional dielectric substrate module 400, the heat generated in the active element chip 8 is directly dissipated in the air, and at the same time it is transmitted to the dielectric substrate layer 1 and then indirectly. Is dissipated into the air. However, since the dielectric substrate 1 has low thermal conductivity, there is a problem that the heat of the active element chip 8 cannot be sufficiently dissipated. On the other hand, in the above-mentioned conventional dielectric substrate module 500, the heat generated in the active element chip 8 is directly dissipated in the air, and is also indirectly dissipated in the air after being transmitted to the heat dissipation block 60. Since the heat dissipation block 60 has high thermal conductivity, the heat of the active element chip 8 can be sufficiently dissipated. However, since the heat dissipation block mounting hole 50 is formed, there is a problem in that the strength of the substrate is reduced. Therefore, an object of the present invention is to provide a dielectric substrate module improved so that heat can be sufficiently dissipated and the strength of the substrate is not lowered.

【0005】[0005]

【課題を解決するための手段】この発明の誘電体基板モ
ジュールは、誘電体基板の表面に能動素子チップを実装
した誘電体基板モジュールにおいて、誘電体基板中に金
属材料の放熱層を埋設すると共に、前記能動素子チップ
の熱を前記放熱層に導く金属材料の複数の伝熱部材を誘
電体基板中に埋設したことを構成上の特徴とするもので
ある。上記構成の誘電体基板モジュールにおいて、誘電
体基板を多層に積層し、2以上の誘電体基板に前記放熱
層を設け、それら放熱層に前記伝熱部材を貫通させるこ
とが好ましい。
A dielectric substrate module according to the present invention is a dielectric substrate module in which an active element chip is mounted on the surface of a dielectric substrate, and a heat dissipation layer made of a metal material is embedded in the dielectric substrate. A structural feature is that a plurality of heat transfer members made of a metal material for guiding the heat of the active element chip to the heat dissipation layer are embedded in a dielectric substrate. In the dielectric substrate module having the above structure, it is preferable that the dielectric substrates are laminated in multiple layers, the heat dissipation layer is provided on two or more dielectric substrates, and the heat transfer member is penetrated through these heat dissipation layers.

【0006】[0006]

【作用】この発明の誘電体基板モジュールでは、能動素
子チップで発生した熱は、直接的に空気中に放散される
と共に、複数の伝熱部材を介して放熱層に伝わり、その
放熱層から誘電体基板に伝わり、その誘電体基板から間
接的に空気中に放散される。能動素子チップから誘電体
基板への有効伝熱面積は、図4の従来例では能動素子チ
ップ8の底面積に限られたが、この発明の誘電体基板モ
ジュールでは放熱層の面積によって任意に拡大される。
従って、十分に放熱できるようになる。また、放熱層を
誘電体基板中に埋設するため、基板強度が低下する問題
も生じない。伝熱部材を複数にするのは、伝熱のための
接触を確実にするため及び伝熱断面積を大きくするため
である。なお、2以上の誘電体基板に放熱層を設けれ
ば、放熱層の面積を容易に拡大できるようになる。
In the dielectric substrate module of the present invention, the heat generated in the active element chip is directly dissipated in the air and is also transmitted to the heat dissipation layer through the plurality of heat transfer members, and the heat dissipation layer causes the heat to be generated. It is transmitted to the body substrate and indirectly diffused into the air from the dielectric substrate. Although the effective heat transfer area from the active element chip to the dielectric substrate is limited to the bottom area of the active element chip 8 in the conventional example of FIG. 4, in the dielectric substrate module of the present invention, it is arbitrarily expanded depending on the area of the heat dissipation layer. To be done.
Therefore, heat can be sufficiently dissipated. Further, since the heat dissipation layer is embedded in the dielectric substrate, the problem of lowering the substrate strength does not occur. The plurality of heat transfer members is provided to ensure contact for heat transfer and to increase the heat transfer cross-sectional area. If the heat dissipation layer is provided on two or more dielectric substrates, the area of the heat dissipation layer can be easily expanded.

【0007】[0007]

【実施例】以下、図に示す実施例によりこの発明をさら
に詳細に説明する。なお、これによりこの発明が限定さ
れるものではない。
The present invention will be described in more detail with reference to the embodiments shown in the drawings. The present invention is not limited to this.

【0008】−第1実施例− 図1は、この発明の第1実施例の誘電体基板モジュール
の断面図である。この誘電体基板モジュール100は、
誘電体基板1,3,5,7と、GND層2,4,6とを
積層し、前記誘電体基板層1,3,5中に配線パターン
1i’,3i,5iを埋設すると共に、前記誘電体基板
層1の表面に配線パターン1sを形成し且つ能動素子チ
ップ8を実装し、さらに、前記誘電体基板層1中に能動
素子チップ8からGND層2に至る2本の伝熱部材9を
埋設した構造である。
[First Embodiment] FIG. 1 is a sectional view of a dielectric substrate module according to a first embodiment of the present invention. This dielectric substrate module 100 is
The dielectric substrates 1, 3, 5, 7 and the GND layers 2, 4, 6 are laminated, and the wiring patterns 1i ′, 3i, 5i are embedded in the dielectric substrate layers 1, 3, 5 and at the same time, The wiring pattern 1s is formed on the surface of the dielectric substrate layer 1 and the active element chip 8 is mounted, and further two heat transfer members 9 from the active element chip 8 to the GND layer 2 are provided in the dielectric substrate layer 1. It is a structure with embedded.

【0009】前記誘電体基板1,3,5,7は、セラミ
ックである。前記GND層2,4,6および配線パター
ン1i’,3i,5i,1sは、銅箔である。前記GN
D層2は、後述するように、放熱層として機能する。前
記配線パターン1i’は、伝熱部材9との干渉を避ける
ため、能動素子チップ8の下部には設けられていない。
前記能動素子チップ8は、FET(電界効果トランジス
タ)やMMIC(モノリシックマイクロ波集積回路)の
ベアチップ(bear chip)である。前記伝熱部材9は、
直径0.2mmの中実銅柱である。能動素子チップ8か
らGND層2への伝熱を確実にするため及び全体として
の断面積を大きくするため、前記伝熱部材9は2本にし
てある。伝熱部材の全体としての断面積を、0.06平
方mm以上にするのが好ましい。なお、誘電体基板モジ
ュール100の完成状態で前記伝熱部材9が能動素子チ
ップ8からGND層2に至る中実銅柱になればよく、初
めから能動素子チップ8からGND層2に至る長さの中
実銅柱を用いる必要はない。
The dielectric substrates 1, 3, 5, 7 are ceramics. The GND layers 2, 4, 6 and the wiring patterns 1i ', 3i, 5i, 1s are copper foils. The GN
The D layer 2 functions as a heat dissipation layer as described later. The wiring pattern 1i ′ is not provided below the active element chip 8 in order to avoid interference with the heat transfer member 9.
The active element chip 8 is a bare chip of FET (field effect transistor) or MMIC (monolithic microwave integrated circuit). The heat transfer member 9 is
It is a solid copper pillar with a diameter of 0.2 mm. In order to ensure heat transfer from the active element chip 8 to the GND layer 2 and to increase the overall cross-sectional area, the number of the heat transfer members 9 is two. It is preferable that the heat transfer member has a sectional area of 0.06 mm 2 or more as a whole. The heat transfer member 9 may be a solid copper pillar extending from the active element chip 8 to the GND layer 2 in the completed state of the dielectric substrate module 100. It is not necessary to use solid copper pillars.

【0010】図2は、上記誘電体基板モジュール100
の一部破断斜視図である。前記誘電体基板1を貫通し
て、2本の伝熱部材9が、能動素子チップ8からGND
層2に至っている。
FIG. 2 shows the dielectric substrate module 100.
It is a partially broken perspective view of FIG. The two heat transfer members 9 penetrate the dielectric substrate 1 and are connected to the active element chip 8 to the GND.
It has reached layer 2.

【0011】以上の誘電体基板モジュール100によれ
ば、能動素子チップ8で発生した熱は、直接的に空気中
に放散されると共に、2本の伝熱部材9を介してGND
層2に伝わり、そのGND層2から誘電体基板1に伝わ
り、その誘電体基板1から間接的に空気中に放散され
る。能動素子チップ8から誘電体基板1への有効伝熱面
積は、GND層2の面積によって拡大され、十分に放熱
できるようになる。また、誘電体基板1,3,5,7に
孔を穿設しないため、基板強度の低下はない。
According to the above dielectric substrate module 100, the heat generated in the active element chip 8 is directly dissipated in the air, and the heat is transmitted through the two heat transfer members 9 to GND.
It is transmitted to the layer 2, is transmitted from the GND layer 2 to the dielectric substrate 1, and is indirectly diffused into the air from the dielectric substrate 1. The effective heat transfer area from the active element chip 8 to the dielectric substrate 1 is expanded by the area of the GND layer 2 so that heat can be sufficiently dissipated. Further, since no holes are formed in the dielectric substrates 1, 3, 5 and 7, the strength of the substrate does not decrease.

【0012】−第2実施例− 図3は、この発明の第2実施例の誘電体基板モジュール
の断面図である。この誘電体基板モジュール200は、
誘電体基板1,3,5,7と、GND層2,4,6とを
積層し、前記誘電体基板層1,3,5中に配線パターン
1i’,3i’,5i’および放熱層10を埋設すると
共に、前記誘電体基板層1の表面に配線パターン1sを
形成し且つ能動素子チップ8を実装し、さらに、前記誘
電体基板層1中に能動素子チップ8からGND層6に至
る2本の伝熱部材9を埋設した構造である。
-Second Embodiment- FIG. 3 is a sectional view of a dielectric substrate module according to a second embodiment of the present invention. This dielectric substrate module 200 is
The dielectric substrates 1, 3, 5, 7 and the GND layers 2, 4, 6 are laminated, and the wiring patterns 1i ′, 3i ′, 5i ′ and the heat dissipation layer 10 are provided in the dielectric substrate layers 1, 3, 5. Embedded therein, the wiring pattern 1s is formed on the surface of the dielectric substrate layer 1 and the active element chip 8 is mounted, and further, the active element chip 8 to the GND layer 6 are provided in the dielectric substrate layer 2 This is a structure in which a book heat transfer member 9 is embedded.

【0013】前記誘電体基板1,3,5,7は、セラミ
ックである。前記GND層2,4,6および配線パター
ン1i’,3i’,5i’,1sおよび放熱層10は、
銅箔である。前記GND層2,4,6は、後述するよう
に、放熱層としても機能する。前記配線パターン1
i’,3i’,5i’は、放熱層10を設けるため、能
動素子チップ8の下部には設けられていない。前記能動
素子チップ8は、FET(電界効果トランジスタ)やM
MIC(モノリシックマイクロ波集積回路)のベアチッ
プ(bear chip)である。前記伝熱部材9は、直径0.
2mmの中実銅柱である。能動素子チップ8からGND
層2,4,6および放熱層10への伝熱を確実にするた
め及び全体としての断面積を大きくするため、前記伝熱
部材9は2本にしてある。前記放熱層10は、伝熱部材
の全体としての断面積を、0.06平方mm以上にする
のが好ましい。なお、前記伝熱部材9は、誘電体基板モ
ジュール100の完成状態で能動素子チップ8からGN
D層2に至る中実銅柱になるが、実際には、能動素子チ
ップ8から誘電体基板1の放熱層10までの中実銅柱
と,誘電体基板1の放熱層10からGND層2までの中
実銅柱と,GND層2から誘電体基板3の放熱層10ま
での中実銅柱と、誘電体基板3の放熱層10からGND
層4までの中実銅柱と,GND層4から誘電体基板5の
放熱層10までの中実銅柱と,誘電体基板5の放熱層1
0からGND層6までの中実銅柱とから成っている。つ
まり、GND層2,4,6および放熱層10は、個々の
中実銅柱を接続するランドとしても機能している。
The dielectric substrates 1, 3, 5, 7 are ceramics. The GND layers 2, 4, 6 and the wiring patterns 1i ′, 3i ′, 5i ′, 1s and the heat dissipation layer 10 are
It is copper foil. The GND layers 2, 4, 6 also function as heat dissipation layers, as described later. The wiring pattern 1
Since i ', 3i' and 5i 'are provided with the heat dissipation layer 10, they are not provided under the active element chip 8. The active element chip 8 includes an FET (field effect transistor) and an M
It is a bear chip of MIC (monolithic microwave integrated circuit). The heat transfer member 9 has a diameter of 0.
It is a solid copper pillar of 2 mm. Active element chip 8 to GND
In order to ensure heat transfer to the layers 2, 4, 6 and the heat dissipation layer 10 and to increase the cross-sectional area as a whole, the number of the heat transfer members 9 is two. It is preferable that the heat dissipation layer 10 has a sectional area of 0.06 square mm or more as a whole of the heat transfer member. It should be noted that the heat transfer member 9 is disposed from the active element chip 8 to the GN when the dielectric substrate module 100 is completed.
The solid copper pillar extending to the D layer 2 is actually the solid copper pillar from the active element chip 8 to the heat dissipation layer 10 of the dielectric substrate 1, and the heat dissipation layer 10 of the dielectric substrate 1 to the GND layer 2 Solid copper pillars up to and including the solid copper pillars from the GND layer 2 to the heat dissipation layer 10 of the dielectric substrate 3 and down to the heat dissipation layer 10 of the dielectric substrate 3 to GND
Solid copper pillars up to layer 4, solid copper pillars from GND layer 4 to heat dissipation layer 10 of dielectric substrate 5, and heat dissipation layer 1 of dielectric substrate 5
It consists of solid copper columns from 0 to GND layer 6. That is, the GND layers 2, 4, 6 and the heat dissipation layer 10 also function as lands that connect the individual solid copper pillars.

【0014】以上の誘電体基板モジュール200によれ
ば、能動素子チップ8で発生した熱は、直接的に空気中
に放散されると共に、2本の伝熱部材9を介してGND
層2,4,6および放熱層10に伝わり、そのGND層
2,4,6および放熱層10から誘電体基板1,3,
5,7に伝わり、その誘電体基板1,3,5,7から間
接的に空気中に放散される。能動素子チップ8から誘電
体基板1,3,5,7への有効伝熱面積は、GND層
2,4,6および放熱層10の面積によって拡大され、
十分に放熱できるようになる。また、誘電体基板1,
3,5,7に孔を穿設しないため、基板強度の低下はな
い。
According to the above-mentioned dielectric substrate module 200, the heat generated in the active element chip 8 is directly dissipated in the air and the GND is transmitted via the two heat transfer members 9.
It is transmitted to the layers 2, 4, 6 and the heat dissipation layer 10, and the dielectric layers 1, 3, 6 are transmitted from the GND layers 2, 4, 6 and the heat dissipation layer 10.
5 and 7, and is indirectly diffused into the air from the dielectric substrates 1, 3, 5, and 7. The effective heat transfer area from the active element chip 8 to the dielectric substrates 1, 3, 5, 7 is expanded by the areas of the GND layers 2, 4, 6 and the heat dissipation layer 10,
You will be able to radiate heat sufficiently. In addition, the dielectric substrate 1,
Since no holes are formed in 3, 5, and 7, the strength of the substrate does not decrease.

【0015】[0015]

【発明の効果】この発明の誘電体基板モジュールによれ
ば、能動素子チップで発生した熱を複数の伝熱部材で放
熱層に伝え、その放熱層から誘電体基板に伝えて放散す
るので、十分に放熱できるようになる。この結果、熱に
よる能動素子の特性劣化を防止することが出来る。ま
た、誘電体基板に孔を穿設しないから、基板強度が低下
することはない。
According to the dielectric substrate module of the present invention, the heat generated in the active element chip is transmitted to the heat dissipation layer by the plurality of heat transfer members, and is transmitted to the dielectric substrate from the heat dissipation layer to be dissipated sufficiently. Will be able to radiate heat. As a result, the characteristic deterioration of the active element due to heat can be prevented. Moreover, since no holes are formed in the dielectric substrate, the substrate strength does not decrease.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の第1実施例による誘電体基板モジュ
ールの断面図である。
FIG. 1 is a sectional view of a dielectric substrate module according to a first embodiment of the present invention.

【図2】図1の誘電体基板モジュールの一部破断斜視図
である。
FIG. 2 is a partially cutaway perspective view of the dielectric substrate module of FIG.

【図3】この発明の第2実施例による誘電体基板モジュ
ールの断面図である。
FIG. 3 is a sectional view of a dielectric substrate module according to a second embodiment of the present invention.

【図4】従来の誘電体基板モジュールの一例を示した断
面図である。
FIG. 4 is a sectional view showing an example of a conventional dielectric substrate module.

【図5】従来の誘電体基板モジュールの他の一例を示し
た断面図である。
FIG. 5 is a sectional view showing another example of a conventional dielectric substrate module.

【符号の説明】[Explanation of symbols]

100,200,400,500 誘電体基板モ
ジュール 1,3,5,7 誘電体基板 2,4,6 GND層 8 能動素子チッ
プ 9 伝熱部材 1s,1i,3i,5i 配線パターン 1i’,3i’,5i’ 配線パターン 50 放熱ブロック
取付孔 60 放熱ブロック
100,200,400,500 Dielectric substrate module 1,3,5,7 Dielectric substrate 2,4,6 GND layer 8 Active element chip 9 Heat transfer member 1s, 1i, 3i, 5i Wiring pattern 1i ', 3i' , 5i 'Wiring pattern 50 Heat dissipation block mounting hole 60 Heat dissipation block

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 誘電体基板の表面に能動素子チップを実
装した誘電体基板モジュールにおいて、 誘電体基板中に金属材料の放熱層を埋設すると共に、前
記能動素子チップの熱を前記放熱層に導く金属材料の複
数の伝熱部材を誘電体基板中に埋設したことを構成上の
特徴とする誘電体基板モジュール。
1. A dielectric substrate module in which an active element chip is mounted on a surface of a dielectric substrate, wherein a heat dissipation layer of a metal material is embedded in the dielectric substrate, and heat of the active element chip is guided to the heat dissipation layer. A dielectric substrate module having a structural feature in which a plurality of heat transfer members made of a metal material are embedded in a dielectric substrate.
【請求項2】 請求項1に記載の誘電体基板モジュール
において、誘電体基板を多層に積層し、2以上の誘電体
基板に前記放熱層を設け、それら放熱層に前記伝熱部材
を貫通させたことを特徴とする誘電体基板モジュール。
2. The dielectric substrate module according to claim 1, wherein the dielectric substrates are laminated in multiple layers, the heat dissipation layers are provided on two or more dielectric substrates, and the heat transfer members are penetrated through these heat dissipation layers. A dielectric substrate module characterized by the above.
JP6117863A 1994-05-31 1994-05-31 Dielectric board module Pending JPH07326866A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6117863A JPH07326866A (en) 1994-05-31 1994-05-31 Dielectric board module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6117863A JPH07326866A (en) 1994-05-31 1994-05-31 Dielectric board module

Publications (1)

Publication Number Publication Date
JPH07326866A true JPH07326866A (en) 1995-12-12

Family

ID=14722165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6117863A Pending JPH07326866A (en) 1994-05-31 1994-05-31 Dielectric board module

Country Status (1)

Country Link
JP (1) JPH07326866A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262512B1 (en) * 1999-11-08 2001-07-17 Jds Uniphase Inc. Thermally actuated microelectromechanical systems including thermal isolation structures
WO2004068923A1 (en) * 2003-01-28 2004-08-12 Cmk Corporation Metal core multilayer printed wiring board
JP2010245120A (en) * 2009-04-01 2010-10-28 Hitachi Kokusai Electric Inc Wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262512B1 (en) * 1999-11-08 2001-07-17 Jds Uniphase Inc. Thermally actuated microelectromechanical systems including thermal isolation structures
WO2004068923A1 (en) * 2003-01-28 2004-08-12 Cmk Corporation Metal core multilayer printed wiring board
US7087845B2 (en) 2003-01-28 2006-08-08 Cmk Corporation Metal core multilayer printed wiring board
JP2010245120A (en) * 2009-04-01 2010-10-28 Hitachi Kokusai Electric Inc Wiring board

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