JPH07326702A - Manufacturing method of leadframe for semiconductor device - Google Patents

Manufacturing method of leadframe for semiconductor device

Info

Publication number
JPH07326702A
JPH07326702A JP12111694A JP12111694A JPH07326702A JP H07326702 A JPH07326702 A JP H07326702A JP 12111694 A JP12111694 A JP 12111694A JP 12111694 A JP12111694 A JP 12111694A JP H07326702 A JPH07326702 A JP H07326702A
Authority
JP
Japan
Prior art keywords
palladium
plating
plating film
film
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12111694A
Other languages
Japanese (ja)
Inventor
Satoshi Chinda
聡 珍田
Ryoichi Koizumi
良一 小泉
Osamu Yoshioka
修 吉岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP12111694A priority Critical patent/JPH07326702A/en
Publication of JPH07326702A publication Critical patent/JPH07326702A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable a palladium plated iron alloy material to sustain an excellent corrosion resistance by minimizing the pinholes made in an underneath layer of the palladium plating. CONSTITUTION:In order to manufacture the title lead frame For semiconductor device, the plating step is mandatory. Firstly, an Ni plating film is formed as an underneath plating palladium. Later, a palladium plating film or palladium alloy film is to be plated at least in an inner lead part and an outer lead part. Next, when an Ni plating film is formed, a pulse current is impressed so as to form an Ni plated film by pulse plating step. At this time, if the duty cycle 5-25% of the pulse waves is specified, the iron elusion amount is diminished below that of the specimen made by smooth DC so as to weaken the corrosion resistance i.e., the pin holes. Furthermore, if the period is specified to be 1-100ms, the iron elusion amount is relatively small down to the level posing no practical problems at all.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置用リードフレ
ームの製造方法に係り、特にニッケルめっき法を改善し
たものに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device lead frame, and more particularly to an improved nickel plating method.

【0002】[0002]

【従来の技術】一般に、リードフレームを用いて半導体
装置を組み立てるには次のようにする。半導体装置用リ
ードフレームのインナリード部の先端に、予め半導体チ
ップとのボンディング性を良好にするために銀めっき層
を設ける。半導体チップ搭載部上に半導体チップをボン
ディングした後、半導体チップの電極とインナリード部
の先端の銀めっき層を、金などの極細線でボンディング
する。この後、モールド樹脂でモールドする。さらに、
半導体パッケージをプリント基板上に取り付ける際の装
着性を良くするために、リードフレームの外枠部を切断
したのち、アウタリード部を含む部分にはんだめっき層
を設けて完成品とする。
2. Description of the Related Art Generally, a semiconductor device is assembled using a lead frame as follows. A silver plating layer is provided in advance on the tip of the inner lead portion of the semiconductor device lead frame in order to improve the bondability with the semiconductor chip. After bonding the semiconductor chip on the semiconductor chip mounting portion, the electrodes of the semiconductor chip and the silver plating layer at the tip of the inner lead portion are bonded with an ultrafine wire such as gold. After that, molding is performed with a molding resin. further,
In order to improve the mountability when mounting the semiconductor package on the printed circuit board, after cutting the outer frame portion of the lead frame, a solder plating layer is provided on the portion including the outer lead portion to complete the product.

【0003】しかし、アウタリード部にはんだめっきを
設けるには、アウタリード部をディップする溶融めっき
時の200℃を越える加熱のために、熱衝撃を受けてレ
ジンモールドにクラックが発生したり、溶融めっき時に
使用するフラックスにより、半導体パッケージやアウタ
リード部などが汚染され、耐湿性が低下したりして、半
導体装置の信頼性を低下させる原因になっている。ま
た、はんだめっきの他に、銀めっきを設ける必要がある
ため、生産性も悪くコスト高となっていた。
However, in order to provide the solder plating on the outer lead portion, the resin mold is cracked due to thermal shock due to the heating exceeding 200 ° C. during the hot dipping for dipping the outer lead portion, or during the hot dipping. The flux used contaminates the semiconductor package, the outer lead portion, and the like, and reduces the moisture resistance, which causes the reliability of the semiconductor device to be reduced. In addition to the solder plating, it is necessary to provide silver plating, resulting in poor productivity and high cost.

【0004】このような問題を解決するために、近年、
リードフレーム製造の段階で、予めワイヤボンディング
性およびはんだ付け性の良いパラジウムを表面処理膜と
して設ける技術が検討されている。予めリードフレーム
最表面にパラジウムめっき層を設けたリードフレーム
は、パラジウムめっき層だけでワイヤボンディング性お
よびはんだ付け性が良いため、めっき工程も簡略化でき
る。そのため最近では、銀めっき及びはんだめっきを予
め設けたリードフレームに代って、注目される技術とな
っている。
In order to solve such a problem, in recent years,
At the stage of manufacturing a lead frame, a technique of previously providing palladium having a good wire bonding property and solderability as a surface treatment film is being studied. A lead frame having a palladium plating layer on the outermost surface of the lead frame in advance has good wire bonding and solderability only with the palladium plating layer, and therefore the plating process can be simplified. For this reason, in recent years, a technique that has attracted attention is replacing the lead frame in which silver plating and solder plating are provided in advance.

【0005】[0005]

【発明が解決しようとする課題】ところで、リードフレ
ーム用金属基体は、銅合金材と鉄合金材に大別される。
銅合金材にNiめっきを施し、次いでパラジウムめっき
膜を施したリードフレームを用いて製造した半導体部品
の耐食性は良好であり、すでにパラジウムめっき銅合金
材リードフレームは実用化されている。
By the way, the metal substrate for lead frame is roughly classified into a copper alloy material and an iron alloy material.
A semiconductor component manufactured by using a lead frame obtained by plating a copper alloy material with Ni and then with a palladium plating film has good corrosion resistance, and a palladium plating copper alloy lead frame has already been put into practical use.

【0006】しかし鉄合金材にパラジウムめっき膜を設
けると、パラジウムの下地にニッケルめっきを施して
も、パラジウムと鉄合金材との電位差が大きいため、ニ
ッケルめっき膜のピンホールを介して、鉄合金材が激し
く腐食してしまい、パラジウムめっき鉄合金材リードフ
レームの実用化が困難となっている。
However, when the palladium plating film is provided on the iron alloy material, the potential difference between the palladium and the iron alloy material is large even if nickel is plated on the underlayer of the palladium. Therefore, the iron alloy is passed through the pin hole of the nickel plating film. The material corrodes violently, making it difficult to put the palladium-plated iron alloy material lead frame to practical use.

【0007】下地めっき膜のピンホールを少なくする方
法として、ニッケルめっきの光沢化も考えられるが、光
沢剤成分の硫黄がめっき膜に包含され、かえって耐食性
が悪くなるため採用できない。
As a method for reducing pinholes in the undercoat plating film, brightening nickel plating can be considered, but it cannot be used because sulfur as a brightener component is included in the plating film and the corrosion resistance deteriorates.

【0008】本発明の目的は、上述した従来技術の欠点
を解消して、パラジウムめっき膜の下地に設けるニッケ
ルめっき膜のピンホールを極力少なくして、パラジウム
めっき膜を鉄合金材に施しても、良好な耐食性を維持で
きる半導体装置用リードフレームを提供することにあ
る。
The object of the present invention is to solve the above-mentioned drawbacks of the prior art, to minimize the pinholes of the nickel plating film provided on the base of the palladium plating film, and to apply the palladium plating film to the iron alloy material. The purpose of the present invention is to provide a lead frame for a semiconductor device that can maintain good corrosion resistance.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に、本発明は、半導体装置用リードフレームにNiめっ
き膜を施した後、パラジウムめっき膜またはパラジウム
合金めっき膜を施す工程を備え、上記ニッケルめっき膜
を施す際、パルスめっきによって施すようにしたもので
ある。
In order to achieve the above object, the present invention comprises a step of applying a Ni plating film to a lead frame for a semiconductor device and then applying a palladium plating film or a palladium alloy plating film, When the nickel plating film is applied, it is applied by pulse plating.

【0010】[0010]

【作用】パルスめっきは、電流印加と休止が繰り返し出
現するもので、電流印加時に激しい析出反応で被めっき
面の金属イオン濃度が少なくなっても、電流休止時に金
属イオンが泳動により補給され、これを繰り返すことに
よって、一般には結晶粒の小さな緻密で平滑なめっき膜
を得る方法である。パルス波で電析させためっき膜には
ピンホールが少ないため、耐食性は平滑直流波で電析さ
せた場合よりも良好となる。
[Function] In pulse plating, current application and resting appear repeatedly. Even if the metal ion concentration on the surface to be plated decreases due to a violent deposition reaction when current is applied, the metal ions are replenished by migration during resting of the current. It is a method of obtaining a dense and smooth plating film with small crystal grains by repeating the above. Since there are few pinholes in the plating film electrodeposited by pulse wave, the corrosion resistance is better than that when electrodeposited by smooth DC wave.

【0011】このため、パラジウムめっき膜の下地のニ
ッケルめっき膜析出時に、パルス波を用いると、これに
より鉄合金材にパラジウムめっき膜を設けても、下地ニ
ッケルめっき膜のピンホールが少ないため、ニッケルめ
っき膜を介しての鉄合金材の腐食がおきにくく、良好な
耐食性を保つことができる。
Therefore, if a pulse wave is used during the deposition of the nickel plating film as the base of the palladium plating film, even if the palladium plating film is provided on the iron alloy material, the number of pinholes in the nickel plating film of the base is small, so Corrosion of the iron alloy material is less likely to occur through the plated film, and good corrosion resistance can be maintained.

【0012】本発明によれば、ニッケルめっき膜析出時
のパルス波は、パルス周期1〜100ms、1周期に占め
る電流印加時間の割合であるデューティサイクルは5〜
25%が良い。周期が1msより短いと、電流の印加と休
止の切り換えが早すぎるため、被めっき面の金属イオン
濃度の回復は望めない。また100msより長いと、電流
変化の割合が少ないため、充分なパルス波の効果を上げ
ることができない。また、デューティサイクルが5%よ
り小さいと、ピーク電流が高くなりすぎて、析出めっき
膜は焼けめっきとなり、かえってピンホールだらけとな
る。例えば平均電流密度4A/dm2 のとき、デューティ
サイクルを4%とすると、ピーク電流密度は100A/
dm2 にもなる。一方、デューティサイクルが25%より
大きいと、電流印加時間が長くなるため、微細結晶が析
出しにくい。
According to the present invention, the pulse wave at the time of depositing the nickel plating film has a pulse cycle of 1 to 100 ms and a duty cycle of 5 to 5 which is a ratio of the current application time to one cycle.
25% is good. If the period is shorter than 1 ms, the switching between the application of current and the pause is too early, and the recovery of the metal ion concentration on the plated surface cannot be expected. On the other hand, if it is longer than 100 ms, the rate of change in current is small and the effect of the pulse wave cannot be sufficiently enhanced. Further, if the duty cycle is less than 5%, the peak current becomes too high, and the deposited plating film becomes burnt plating, and is rather full of pinholes. For example, when the average current density is 4 A / dm 2 , and the duty cycle is 4%, the peak current density is 100 A / dm 2.
It can be dm 2 . On the other hand, when the duty cycle is larger than 25%, the current application time becomes long, so that fine crystals are hard to deposit.

【0013】[0013]

【実施例】以下、本発明の実施例を説明する。半導体装
置用のリードフレームの基体にめっきを施すには、まず
パラジウムの下地めっきとしてNiめっき膜を全面に施
す。半導体装置用リードフレームは、一般には半導体チ
ップ搭載部、インナリード部、アウタリード部、外枠部
などからなるが、ニッケルめっき後、少なくともインナ
リード部およびアウタリード部にパラジウムめっき膜ま
たはパラジウム合金膜を施す。
EXAMPLES Examples of the present invention will be described below. In order to plate a substrate of a lead frame for a semiconductor device, first, a Ni plating film is plated on the entire surface as a base plating of palladium. A lead frame for a semiconductor device generally includes a semiconductor chip mounting portion, an inner lead portion, an outer lead portion, an outer frame portion, etc., but after nickel plating, at least the inner lead portion and the outer lead portion are coated with a palladium plating film or a palladium alloy film. .

【0014】このように2回にわたってめっきを施す
が、本実施例では、最初のNiめっき膜を施す際、通常
直流印加であるところを、パルスめっきを用い、パルス
電流でニッケルめっき膜を析出させるようにしている。
パルスめっきの採用により、耐食性が大きく関与するピ
ンホールが激減する。
Although the plating is performed twice as described above, in the present embodiment, when the first Ni plating film is applied, the place where the direct current is normally applied is pulse plating and the nickel plating film is deposited by the pulse current. I am trying.
By adopting pulse plating, the number of pinholes, which greatly contribute to corrosion resistance, will be drastically reduced.

【0015】したがって、パラジウムの下地にニッケル
めっきを施しても、ニッケルめっき膜のピンホールを介
して鉄合金材が腐食することがほとんどなくなり、パラ
ジウムめっき鉄合金材リードフレームの実用化が可能と
なる。
Therefore, even if nickel plating is applied to the base of palladium, the iron alloy material is hardly corroded through the pin holes of the nickel plating film, and the palladium plated iron alloy material lead frame can be put to practical use. .

【0016】また、パルスめっきによりニッケルめっき
膜のピンホールを少なくするので、ニッケルめっきの光
沢化を施す必要がなく、光沢剤成分の硫黄がめっき膜に
包含されて耐食性が悪くなることもない。
Further, since the pinholes of the nickel plating film are reduced by the pulse plating, it is not necessary to brighten the nickel plating, and sulfur as a brightener component is not contained in the plating film to deteriorate the corrosion resistance.

【0017】本実施例では、パルスめっきによるニッケ
ルめっきに関して、次のような実験を行った。42合金
板(30×40mm)の全面に、表1に示す無光沢ニッケ
ルめっき液を用いて、ニッケルめっき膜を約1μm 形成
した。
In this example, the following experiment was conducted for nickel plating by pulse plating. A nickel plating film of about 1 μm was formed on the entire surface of the 42 alloy plate (30 × 40 mm) using the matte nickel plating solution shown in Table 1.

【0018】[0018]

【表1】 [Table 1]

【0019】その際、表2に示す条件のパルス電流条件
により、ニッケルめっき膜を析出させた。ここで、iav
は平均電流密度、ip はピーク電流密度、tonはパルス
長さ、toff は休止時間である。また、表の上半分はサ
イクルタイム=10ms一定としてデューティーサイクル
を変え、表の下半分はデューティーサイクル=9%一定
としてサイクルタイムを変えている。
At this time, a nickel plating film was deposited under the pulse current conditions shown in Table 2. Where i av
The average current density, i p is the peak current density, t on the pulse length, t off is the rest time. The upper half of the table changes the duty cycle with the cycle time fixed at 10 ms, and the lower half of the table changes the cycle time with constant duty cycle = 9%.

【0020】[0020]

【表2】 [Table 2]

【0021】さらにニッケルめっき膜の上に、表3に示
す条件で、パラジウムめっき膜を約0.1μm 形成し
た。
Further, a palladium plating film having a thickness of about 0.1 μm was formed on the nickel plating film under the conditions shown in Table 3.

【0022】なお、パルス電流を用いた本実施例との比
較のために、ニッケルめっき膜析出の際、平滑直流を用
いた試料も作成した。
For the purpose of comparison with the present embodiment using pulse current, a sample using smooth direct current was also prepared during the nickel plating film deposition.

【0023】[0023]

【表3】 [Table 3]

【0024】このようにして作成したパラジウムめっき
42合金板を、0.05 mol/lの食塩水を満たした小
型圧力容器(容積70ml)に入れて密閉し、121℃の
恒温槽中で24時間保持した。次に試料板を取出し、食
塩水中に溶出した42合金板からの鉄成分量を原子吸光
法で定量した。この場合、鉄溶出量が少ないほど、耐食
性が良好といえる。
The palladium-plated 42 alloy plate thus prepared was placed in a small pressure vessel (volume: 70 ml) filled with 0.05 mol / l of saline solution and hermetically sealed, and kept in a constant temperature bath at 121 ° C. for 24 hours. Held Next, the sample plate was taken out, and the amount of iron component from the 42 alloy plate eluted in saline was quantified by the atomic absorption method. In this case, the smaller the elution amount of iron, the better the corrosion resistance.

【0025】パラジウムめっき膜の下地ニッケルめっき
析出時に、パルス電流を印加した場合の、デューティサ
イクルθの変化と42合金素材からの鉄成分溶出量の関
係を図1に示す。デューティーサイクルが9%のとき
に、鉄溶出量がもっとも少なくなり、耐食性が良好であ
ることが分った。また5〜25%の範囲で、平滑直流
(100%)で作成した試料より耐食性が向上すること
がわかった。
FIG. 1 shows the relationship between the change in duty cycle θ and the elution amount of the iron component from the 42 alloy material when a pulse current is applied during the deposition of nickel undercoat on the palladium plating film. It was found that when the duty cycle was 9%, the iron elution amount was the smallest and the corrosion resistance was good. It was also found that in the range of 5 to 25%, the corrosion resistance was improved as compared with the sample prepared with smooth DC (100%).

【0026】次にデューティサイクルを9%一定とし、
パルス電流の周期を0.1〜1000msの範囲で変化さ
せた場合の、パラジウムめっき42合金材からの鉄成分
溶出量分析結果を図2に示す。この結果から、周期10
ms時に、鉄溶出量がもっとも少なくなり、耐食性が良好
であることが分った。また周期1〜100msの範囲で、
比較的鉄溶出量は少なく、実用上問題のないレベルであ
ることを確認した。
Next, the duty cycle is kept constant at 9%,
FIG. 2 shows the analysis results of the amount of iron component elution from the palladium-plated 42 alloy material when the period of the pulse current was changed in the range of 0.1 to 1000 ms. From this result, cycle 10
At ms, it was found that the iron elution amount was the smallest and the corrosion resistance was good. Moreover, in the range of the cycle 1-100ms,
It was confirmed that the amount of iron elution was relatively small and there was no practical problem.

【0027】この実験から明らかになったように、ニッ
ケルめっきをパルスめっきで行うようにすると、ピンホ
ールの少ない信頼性の高いパラジウムめっき鉄合金材リ
ードフレームの実用化が可能となる。
As is clear from this experiment, if nickel plating is performed by pulse plating, a highly reliable palladium-plated iron alloy lead frame with few pinholes can be put to practical use.

【0028】42合金材に代表される鉄合金材は剛性が
高いため、多ピン狹ピッチフレーム用材料として需要が
多い。一方、パラジウムめっき膜を設けたリードフレー
ムは、後工程の外装はんだめっきを省略できるため、組
み立て時間の短縮化が可能で半導体製造コストの低減を
図ることができる。また、はんだブリッジの心配がな
く、狹ピッチフレームには最適である。しかも最近指摘
されている鉛公害の問題もない。さらにワイヤボンド用
の銀めっきもないため、銀によるマイグレーション現象
の心配もない。このようにパラジウムめっき鉄合金材リ
ードフレームを実用化したことによる効果は非常に大き
い。
The iron alloy material represented by the 42 alloy material has high rigidity, and thus is in great demand as a material for a multi-pin fox pitch frame. On the other hand, since the lead frame provided with the palladium plating film can omit the external solder plating in the subsequent step, the assembly time can be shortened and the semiconductor manufacturing cost can be reduced. In addition, there is no concern about solder bridges, which makes it ideal for fox pitch frames. Moreover, there is no lead pollution problem that has been pointed out recently. Furthermore, since there is no silver plating for wire bonding, there is no fear of migration phenomenon due to silver. As described above, the practical use of the palladium-plated iron alloy material lead frame has a great effect.

【0029】なお、本発明は、パラジウムめっき膜の下
地に設けるニッケルめっき膜をパルス電流で析出させ、
ピンホールの少ないめっき膜を実現させたものである。
したがって、ニッケルめっき膜のさらに下層にめっき膜
を設けてあっても何ら差し支えない。また、リードの素
材としては鉄合金材ばかりでなく銅合金材を用いてもよ
い。その場合、耐食性はさらに向上する。
In the present invention, the nickel plating film provided on the base of the palladium plating film is deposited by pulse current,
This is a plating film with few pinholes.
Therefore, there is no problem even if a plating film is provided below the nickel plating film. Further, not only an iron alloy material but also a copper alloy material may be used as the material of the lead. In that case, the corrosion resistance is further improved.

【0030】[0030]

【発明の効果】本発明によれば、パラジウムめっき膜ま
たはパラジウム合金めっき膜の下地に設けるニッケルめ
っき膜をパルスめっきにより形成するようにしたので、
ニッケルめっき膜のピンホールが極力少なくなり、パラ
ジウムめっき膜またはパラジウム合金めっき膜を鉄系ま
たは鉄合金系のリードフレームに施しても、良好な耐食
性を維持できる。
According to the present invention, since the nickel plating film provided on the base of the palladium plating film or the palladium alloy plating film is formed by pulse plating,
The pinholes of the nickel plating film are reduced as much as possible, and good corrosion resistance can be maintained even if the palladium plating film or the palladium alloy plating film is applied to the iron-based or iron alloy-based lead frame.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置用リードフレームの製造方
法の実施例を説明するための下地ニッケルめっき析出時
のパルス電流のデューティサイクル(θ)の変化と、パ
ラジウムめっき42合金材の腐食試験後の鉄溶出量の関
係を示す特性図。
FIG. 1 is a diagram illustrating a method of manufacturing a lead frame for a semiconductor device according to an embodiment of the present invention, which shows a change in duty cycle (θ) of a pulse current during deposition of nickel-plated undercoat, and a corrosion test of a palladium-plated 42 alloy material. FIG. 6 is a characteristic diagram showing the relationship between the amount of iron eluted from the steel.

【図2】本実施例例を説明するための下地ニッケルめっ
き析出時のパルス電流の周期の変化とパラジウムめっき
42合金材の腐食試験後の鉄溶出量の関係を示す特性
図。
FIG. 2 is a characteristic diagram showing the relationship between changes in the cycle of the pulse current at the time of depositing nickel undercoat and the amount of iron elution after a corrosion test of a palladium plated 42 alloy material for explaining the present example.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体装置用リードフレームにNiめっき
膜を施した後、パラジウムめっき膜またはパラジウム合
金めっき膜を施す工程を備え、上記ニッケルめっき膜を
施す際、パルスめっきによって施すようにしたことを特
徴とする半導体装置用リードフレームの製造方法。
1. A step of applying a nickel plating film to a semiconductor device lead frame and then applying a palladium plating film or a palladium alloy plating film, wherein the nickel plating film is applied by pulse plating. A method for manufacturing a semiconductor device lead frame.
【請求項2】上記パルスめっきに使用するパルス波は、
周期1〜100ms、デューティサイクル5〜25%であ
ることを特徴とする請求項1に記載の半導体装置用リー
ドフレームの製造方法。
2. The pulse wave used for the pulse plating is
The method for manufacturing a lead frame for a semiconductor device according to claim 1, wherein the cycle is 1 to 100 ms and the duty cycle is 5 to 25%.
JP12111694A 1994-06-02 1994-06-02 Manufacturing method of leadframe for semiconductor device Pending JPH07326702A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12111694A JPH07326702A (en) 1994-06-02 1994-06-02 Manufacturing method of leadframe for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12111694A JPH07326702A (en) 1994-06-02 1994-06-02 Manufacturing method of leadframe for semiconductor device

Publications (1)

Publication Number Publication Date
JPH07326702A true JPH07326702A (en) 1995-12-12

Family

ID=14803287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12111694A Pending JPH07326702A (en) 1994-06-02 1994-06-02 Manufacturing method of leadframe for semiconductor device

Country Status (1)

Country Link
JP (1) JPH07326702A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6150713A (en) * 1998-04-18 2000-11-21 Samsung Aerospace Industries, Ltd. Lead frame for semiconductor package and lead frame plating method
JP2006518553A (en) * 2003-02-19 2006-08-10 ハネウエル・インターナシヨナル・インコーポレーテツド Method of generating thermal interconnect system and use thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6150713A (en) * 1998-04-18 2000-11-21 Samsung Aerospace Industries, Ltd. Lead frame for semiconductor package and lead frame plating method
KR100275381B1 (en) * 1998-04-18 2000-12-15 이중구 Lead frame for semiconductor package and method for plating lead frame
JP2006518553A (en) * 2003-02-19 2006-08-10 ハネウエル・インターナシヨナル・インコーポレーテツド Method of generating thermal interconnect system and use thereof
US7897437B2 (en) 2003-02-19 2011-03-01 Honeywell International Inc. Thermal interconnect systems methods of production and uses thereof

Similar Documents

Publication Publication Date Title
TWI335943B (en) Whiskerless plated structure and plating method
JP3417395B2 (en) Lead frame for semiconductor device, method of manufacturing the same, and semiconductor device using the same
US7488408B2 (en) Tin-plated film and method for producing the same
CN103295916B (en) Semiconductor devices and its manufacture method
CA2118758C (en) Lead frame for integrated circuits
US6037653A (en) Semiconductor lead frame having multi-layered plating layer including copper-nickel plating layer
CA1250963A (en) Nickel/indium plated cover for hermetically sealed container for electronic device
JP2012502462A (en) Lead frame and manufacturing method thereof
WO2005074026A2 (en) Tin-based coating of electronic component
KR101038491B1 (en) lead frame and the method for manufacturing the same
JPH07326702A (en) Manufacturing method of leadframe for semiconductor device
US7432584B2 (en) Leadframe for use in a semiconductor package
JPH07326701A (en) Conductive material for electric-electronic part, lead frame and semiconductor integrated circuit using the same
JPS583962A (en) Stress free nickel layer formation
JP2000174191A (en) Semiconductor device and its manufacture
KR100378489B1 (en) Ag or Ag-alloy plated Lead frame for semiconductor package and the method of manufacturing the same
JPH07230904A (en) Forming method for electrode terminal of chip-fixed resistor
US5530283A (en) Lead frame and lead frame material
JPH0529517A (en) Lead frame for semiconductor device
JPH10284666A (en) Electronic component device
KR100503038B1 (en) Lead frame for semiconductor package
KR100209264B1 (en) Semiconductor lead frame
JPH07300696A (en) Electrodeposition tin plating method
JPH08209359A (en) Ic package
JPS5926985A (en) Soldering bondage of glass or ceramics and copper