JPH07326626A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a manufacture of a semiconductor device which enables simultaneous realization of miniaturization and stabilization of a process. CONSTITUTION:The side wall of a poly-Si film pattern 35a formed in isolation above a semiconductor substrate 31 is oxidized and an oxide film 38 thus obtained is removed, so that a minute poly-Si film pattern 35b under a resist pattern 37 be formed. Based on the self-alignment with this minute poly-Si film pattern 35b, an emitter electrode in a bipolar transistor or a gate electrode in an MOS transistor is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a self-aligning method for a semiconductor device which is suitable for manufacturing a transistor such as a bipolar transistor and which can be miniaturized and speeded up.

[0002]

2. Description of the Related Art In order to improve the performance of a semiconductor device, especially a bipolar transistor, it is important to improve the cutoff frequency fT, the capacitance between bases and collectors, the reduction of parasitic elements and the reduction of base resistance.

Among these improvements, in order to reduce the number of parasitic elements, it is important to miniaturize the transistor as much as possible and remove a portion unnecessary for the operation of the transistor as much as possible. Therefore, a lithography technique capable of forming a fine pattern and performing highly accurate alignment is required.

Therefore, also in the manufacturing process of the transistor, a self-alignment technique corresponding to miniaturization and high speed becomes important. Further, such a self-alignment technique is important not only for the bipolar transistor described above but also for the MOS transistor.

FIG. 7 is a schematic sectional view of a high speed bipolar transistor (NPN) manufactured by a conventional manufacturing method.

In FIG. 7, 1 is an N-collector layer, 2 is a P-base layer, 3 is an N ⁺ -emitter layer, 4 is a P-channel stop layer, 5 is a SiO ₂ film, and 7 is P-poly Si.
A film, 8 is a SiO ₂ film, 10 is a SiO ₂ side wall (sidewall), and 11 is a poly-Si film.

As described above, in the bipolar transistor shown in FIG. 7, the emitter electrode of the N ⁺ -emitter layer 3 is po
A double polysilicon structure in which the base electrode of the ly-Si film 11 and the P-base layer 2 is taken out by two layers of the P-poly Si film 7 is adopted, and the electrodes are insulated and separated by the SiO ₂ side wall 10. As a result, the base-collector capacitance is significantly reduced.

The technique for forming the SiO ₂ side wall 10 shown in FIG. 7 is known as the most commonly used self-alignment technique in the related art because of its controllability and ease of processing.

A conventional method of manufacturing a bipolar transistor will be described below with reference to FIG. 8 showing a conventional manufacturing process of the bipolar transistor.

First, as shown in FIG. 8A, a p-type conductive film having a thickness of 150 nm is formed on a silicon (Si) substrate 21.
The poly-Si film 22 and S having a thickness of 600 nm as an insulating film
After sequentially forming the iO ₂ films 23 by the CVD method, a resist is applied on the SiO ₂ film 23 and a resist pattern 24 having emitter holes is formed in the resist by a photolithography technique.

Next, as shown in FIG. 8B, the SiO ₂ film 23 and the poly-Si film 2 are formed by RIE (reactive ion etching) using the resist pattern 24 as a mask.
2 are sequentially etched to form an emitter opening 25, and then the resist pattern 24 is removed.

Next, as shown in FIG. 8C, a SiO ₂ film having a thickness of 15 nm is formed by thin film oxidation, followed by CV.
A SiO ₂ film having a thickness of 600 nm was formed by using the D method, and a SiO ₂ film 27 was also formed. Then nitrogen (N ₂ )
Si is annealed in the atmosphere at a temperature of 900 ° C. for 30 minutes
Densify the O ₂ film 27 (defect removal).

Next, as shown in FIG. 8D, the SiO ₂ film 27 is etched by RIE to form SiO ₂ sidewalls 28 as sidewalls on the sidewalls of the SiO ₂ film 23.

[0014]

The problem to be solved by the invention is shown in FIG.
After the emitter opening by the process shown in FIG.
When forming the SiO ₂ side wall 28, the following problems occurred.

1) SiO ₂ film 2 for forming sidewalls
The shape of the SiO ₂ side wall (sidewall) 28 also varies due to the variation in the coverage of No. 7 (coverage of the step portion or the groove portion).

FIGS. 9A to 9D are process sectional views for explaining the problem of variations in the shape of the sidewalls.
As shown in (a), in the SiO ₂ film 27a formed by the oxidation and CVD method, the central recess wall is inclined as compared with the coverage shape of the SiO ₂ film 27 shown in FIG. 8C.

Therefore, the side wall SiO ₂ side wall 28a formed by the subsequent RIE is narrower than the SiO ₂ side wall 28 shown in FIG. 8D.

2) During RIE for forming sidewalls in the steps of FIGS. 8C to 8D, the base (Si) is changed due to the variation of the etching selection ratio between the insulating film (SiO ₂ ) and the base (Si). The etching amount of) also varies.

In FIG. 10, when the SiO ₂ side wall 28b is formed, the Si substrate 21 is simultaneously etched to form the Si groove 30.

As shown in FIGS. 9 and 10, variations in the sidewall shape, variations in the selection ratio, etc. cause variations in the finally formed device shapes and greatly affect the device characteristics.

An object of the present invention is to provide a method of manufacturing a semiconductor device which can realize miniaturization and process stabilization at the same time in consideration of the above problems.

[0022]

A method of manufacturing a semiconductor device according to claim 1 of the present invention for solving the above-mentioned problems comprises a first insulating film on a semiconductor substrate and a second insulating film on the first insulating film. A film, a first conductive film on the second insulating film, a third insulating film sequentially stacked on the first conductive film, and a resist pattern on the third insulating film having a stacked structure, A step of removing the third insulating film and the first conductive film by using the resist pattern as a mask to form the third insulating film pattern and the first conductive film pattern under the resist pattern; and a step of removing the first conductive film pattern exposed in the removing step. After the step of oxidizing the side wall and removing the oxidized portion of the first conductive film pattern, the second insulating film is removed using the unoxidized first conductive film pattern as a mask to form a second layer under the unoxidized first conductive film pattern. Insulating film pattern formation process and unoxidized first conductor The step of removing the film pattern, and after forming the fourth insulating film on the second insulating film pattern, etching is performed to form a sidewall made of the fourth insulating film on the side wall of the second insulating film and to form the first insulating film. A step of removing, a step of embedding the second conductive film in a portion excluding the second insulating film pattern and the fourth insulating film sidewall, a step of oxidizing the surface of the second conductive film, a second insulating film and the second insulating film. Removing the first insulating film under the insulating film, the second insulating film and the second insulating film
The method is characterized by including a step of embedding a third conductive film in a portion where the first insulating film is removed under the insulating film.

A method of manufacturing a semiconductor device according to a second aspect of the present invention is characterized in that, in the first aspect, the second conductive film is a base extraction electrode and the third conductive film is an emitter extraction electrode.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a first insulating film on a semiconductor substrate; a second insulating film on the first insulating film; and a first conductive film on the second insulating film. Membrane, the first
A step of sequentially stacking and forming a third insulating film on the conductive film; a step of forming a resist pattern on the third insulating film having a stacked structure; and a step of forming the third insulating film and the first mask using the resist pattern as a mask.
A step of removing the conductive film to form a third insulating film pattern and a first conductive film pattern under the resist pattern; a step of oxidizing a sidewall of the first conductive film pattern exposed in the removing step; a first conductive film pattern And removing the second insulating film using the unoxidized first conductive film pattern as a mask to form a second insulating film pattern under the unoxidized first conductive film pattern. 1 a step of removing the conductive film pattern, a step of forming a ring base layer using the second insulating film pattern as a mask, and a step of forming a fourth insulating film on the second insulating film pattern and then etching the sidewall of the second insulating film. Forming a sidewall made of a fourth insulating film on the base, removing the first insulating film, and filling the second conductive film in a portion excluding the second insulating film pattern and the fourth insulating film sidewall to form a base. Forming a protruding electrode; oxidizing the surface of the second conductive film; removing the second insulating film and the first insulating film below the second insulating film; A step of burying a third conductive film in the removed portion of the first insulating film under the second insulating film and forming an emitter extraction electrode;
The method is characterized by including a step of forming a base layer and an emitter layer by diffusion using the third conductive film or removal of the first insulating film and ion implantation before embedding the third conductive film.

Further, a method of manufacturing a semiconductor device according to a fourth aspect of the present invention is the method according to the first or third aspect, wherein the first insulating film is a SiO ₂ film, the second and third insulating films are SiN films, and A feature is that a poly-Si film or an amorphous Si film is used as the second and third conductive films.

A method for manufacturing a semiconductor device according to a fifth aspect of the present invention is directed to a first insulating film on a semiconductor substrate, a second insulating film on the first insulating film, and a first conductive film on the second insulating film. A step of sequentially forming a third insulating film on the first conductive film, and a step of forming a resist pattern on the third insulating film having a laminated structure,
Removing the third insulating film and the first conductive film using the resist pattern as a mask to form the third insulating film pattern and the first conductive film pattern under the resist pattern; and the third insulating film pattern and the first conductive film pattern. Source as mask
The step of forming the drain region, the step of oxidizing the sidewall of the first conductive film pattern exposed in the removing step, and the removal of the second insulating film and the first insulating film using the unoxidized portion of the first conductive film pattern as a mask. However, the method includes the step of forming a shallow impurity introduction region in the semiconductor substrate.

A method of manufacturing a semiconductor device according to a sixth aspect of the present invention is the method according to the fifth aspect, wherein S is used as the first insulating film.
iO ₂ film, SiN film as second and third insulating films, first,
A feature is that a poly-Si film or an amorphous Si film is used as the second and third conductive films.

[0028]

According to the present invention, as shown in FIG. 1, the SiO ₂ film 32, the SiN film 33, and the poly-S are formed on the Si substrate 31.
After the i film 35 and the SiN film 36 are sequentially laminated to have a predetermined thickness, the upper SiN film 36 and the poly-Si film are stacked.
The film 35 is patterned to have a line width of about 0.8 μm, and the exposed sidewalls of the obtained poly-Si film pattern 35a are oxidized with good controllability. As a result, it is possible to stably form the unoxidized poly-Si pattern 35b having a fine line width W1 of about 0.2 μm.

In this way, the unoxidized poly-Si film pattern 35b having the miniaturized structure is formed on the Si substrate 31 in a self-aligned manner, and the miniaturized unoxidized poly-Si film 35b is formed.
Based on the film pattern 35b, a miniaturized emitter electrode of a bipolar transistor, a miniaturized gate electrode of a MOS transistor (the unoxidized poly-Si film pattern 35b itself is used as a gate electrode), and the like can be manufactured.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a process sectional view for forming a first substrate structure according to the present invention. As shown in FIG. 1A, first, a SiO ₂ film 32 is formed as a thin film oxide film having a thickness of 15 nm on a Si substrate 31 by thermal oxidation, then a SiN film 33 having a thickness of 15 nm and a pol having a thickness of 150 nm are formed by a CVD method.
The y-Si film 35 and the SiN film 36 having a thickness of 100 nm are successively formed. After that, a resist is applied on the entire surface, and then the line width is about 0.8 μm by photolithography technology.
A resist pattern 37 of is formed.

Next, using the resist pattern 37 as a mask, the SiN film 36, po is formed by RIE as shown in FIG.
The ly-Si film 35 is etched to form the SiN film pattern 3
6a, a poly-Si film pattern 35a is formed. The RIE etching process is a two-step etching process. The first step is the SiN film 36, and the second step is poly-S.
The i film 35 was etched. Note that SiO ₂ vs. SiN
The selection ratio was 10 or more.

Next, as shown in FIG. 1C, the exposed side wall of the remaining poly-Si film pattern 35a is thermally oxidized. At this time, the poly-Si film pattern 35a
Since the upper and lower layers are each made of SiN, poly
Oxidation other than the sidewalls of -Si can be suppressed as much as possible. p
The unoxidized poly-S which is the unoxidized poly-Si film 35.
The i-film pattern 35b is oxidized in the side direction until the line width becomes about 0.2 μm to form the SiO ₂ film 38.

Next, the SiO ₂ film 38 is removed by wet etching using dilute hydrofluoric acid, and then the entire surface is subjected to RIE.
The SiN film pattern 36a, the SiN film 33 and the Si
The O ₂ film 32 is removed (FIG. 1D). At this time, RIE
The condition is that the width W1 of the poly-Si is about 0.2 μm by giving a selection ratio to the poly-Si (> 5).
Therefore, it is possible to form the isolated pattern 35b which is made fine with m.

As described above, the 0.2 μm pattern line width of the poly-Si formed by the steps of FIGS. 1A to 1D is determined only by the photolithography pattern of about 0.8 μm and the oxidation. -Si 0.
The 2 μm fine pattern is stably formed in the process.
The 0.8 μm lithography described above can be performed by G-line lithography.

Next, an embodiment in which the present invention is applied to the manufacture of bipolar transistors will be described with reference to FIGS.

First, as shown in FIG. 2A, a SiO ₂ film 42 as a thin oxide film having a thickness of 15 nm is formed on a Si substrate 41 by thermal oxidation, and then a SiN film 43 having a thickness of 150 nm is formed by a CVD method. 150 nm thick poly-Si film 4
5. The SiN film 46 having a thickness of 100 nm is successively formed. After applying a resist on the entire surface of the above-mentioned laminated film, a resist pattern 47 (line width of about 0.8 μm) for forming an emitter electrode is formed by a lithography technique.

Next, using the resist pattern 47 as a mask, as shown in FIG. 2B, the SiN film 46, p is formed by RIE.
The poly-Si film 45 is sequentially etched to form a SiN film pattern 46a and a poly-Si film pattern 45a. The etching of this RIE is a two-step etching. The first step is the SiN film 46, and the second step is the pol.
The y-Si film 45 was etched (selectivity ratio to SiN> 1).
0).

Next, as shown in FIG. 2C, the remaining p
The oli-Si film 45 is thermally oxidized to form a SiO ₂ film 48. At this time, the poly-Si exposed by the above-mentioned RIE is used.
Only the side wall of the film pattern 45a is oxidized and unoxidized po
The ly-Si film pattern 45b remains. Also, pol
Since the upper layer and the lower layer of the y-Si film 45 are each made of SiN, oxidation other than the sidewalls of the poly-Si film can be suppressed as much as possible. By this oxidation, the unoxidized portion of the poly-Si film 45 (unoxidized poly-Si film pattern 45b) is oxidized in the side direction until the line width becomes about 0.2 μm.

Next, as shown in FIG.
The SiO ₂ film 48 formed in (c) is removed with dilute hydrofluoric acid, and then RIE is performed on the entire surface to form the SiN film pattern 46a,
The SiN film 43 is removed (selectivity ratio to SiO ₂ > 10).
At this time, the miniaturized unoxidized poly-Si film pattern 45b serves as a mask to form the SiN film pattern 43a in which the line width (W2) of the SiN film 43 is finely processed in a self-aligned manner. it can. Then, using a KOH solution, the unoxidized poly-Si used as the mask.
The film pattern 45b is removed (FIG. 3B).

Next, after forming a SiO ₂ film with a thickness of 300 nm on the entire surface by the CVD method, annealing is performed in a nitrogen atmosphere at 900 ° C. for 30 minutes, and the entire surface is etched.
A side wall SiO ₂ side wall 49 is formed on the finely processed SiN film pattern 43a formed in FIG.
(C)).

Next, a thickness of 300 n is formed on the entire surface by the CVD method.
m poly-Si is deposited and smoothed by SOG etch-back, resist etch-back, CMP, etc. so as to fill the recess, and poly-Si is deposited around the SiO ₂ film side wall 49.
The Si film 50 is formed (FIG. 4A).

Next, as shown in FIG.
Oly-Si film 50 is oxidized to form SiO ₂ film 51 on the surface. The thickness of the unoxidized poly-Si film 50a that was not oxidized by the oxidation at this time was 150 nm. Then, by wet etching with a dilute hydrofluoric acid solution, an oxide film with a thickness of about 10 nm (this oxide film is p
The one formed simultaneously with the oxidation of the ol-Si film 50) is removed, and the SiN film pattern 43a is removed by wet etching with a hot phosphoric acid solution. At this time SiO ₂
An opening 52 is formed in the side wall 49.

Next, as shown in FIG. 4C, after removing the SiO ₂ film 42 having a thickness of 15 nm disposed under the portion (opening 52) where the SiN film pattern 43a has been removed, the CV is removed.
Poly-Si is deposited by the D method to fill the opening 52, and patterning is performed so that the bonding portion with the Si substrate 41 is 0.2.
A fine poly-Si emitter electrode 53a having a thickness of μm is formed.

As described above, according to the steps shown in FIGS. 2 to 4, the present invention can be applied to manufacture a fine emitter electrode of a bipolar transistor.

FIG. 5 is a process sectional view for explaining a method of forming an activation layer in the manufacturing process of the bipolar transistor shown in FIGS.

First, as shown in FIG. 5A, when the SiN film pattern 43a shown in FIG. 3B is formed, the link base ion implantation (II) is performed using the SiN film pattern 43a as a mask. Do. The ion species is BF ₂ ⁺
And the implantation energy is set to 40 KeV, and the implantation amount is 2 × 10.
^{It was set to 13} to 4 × 10 ¹³ / cm ² . After that, the SiO ₂ sidewall 4
After formation of the SiO ₂ film to form a 9, P layer 56 as the link base layer on the Si substrate 41 by performing annealing
To form.

Next, as shown in FIG. 5B, SiO ₂ sidewalls 49 are formed around the SiN film pattern 43a. Then, in the step of FIG. 4A, the poly-Si film 50 is formed by using boron-doped poly-Si or by depositing poly-Si by a CVD method, and then forming P on the entire surface.
F ₂ ⁺ implantation energy 30 KeV, implantation dose 3 × 10 ¹⁵ /
It is formed by implanting in cm ² . After that, as shown in FIG. 5C, a P ⁺ layer 57 as a base layer is formed on the Si substrate 41 and formed on the oxide film of the poly-Si film 50 in the above-described step of FIG. 4B.

Next, when the buried emitter electrode (embedded) poly-Si film 53a shown in FIG. 5D is formed, base ion implantation (BF ₂ ⁺ , 50 KeV, 1 ×) is performed on the poly-Si film 53a. 10 ^{14 to} 3 × 10 ¹⁴ / c
m ² ), followed by base diffusion (800 ° C. for 30 minutes and 900 ° C. for 30 minutes), followed by emitter ion implantation (As ⁺ , 40 KeV, 1 × 10 ¹⁶ to 2 × 1).
0 ¹⁶ / cm ² ) and perform emitter diffusion (30 at 800 ° C.
Minutes and 1000 ° C to 1100 ° C for 10 seconds),
From the poly-Si film 53a side to the emitter layer (N ⁺ layer) 6
1. A base layer (P layer) 62 is formed.

As described above, the emitter layer and the base layer of the bipolar transistor can be stably formed with a fine line width of about 0.2 μm by the process of FIG.

Next, an example in which the present invention is applied to manufacture of a MOS transistor will be described with reference to FIG.

First, in the step of FIG.
In this embodiment, as shown in FIG. 6A, the SiO ₂ film 42 as a thin oxide film has a thickness of 10 nm, the SiN film 43 has a thickness of 10 nm, and the poly-Si film 45 has a thickness of 150 n.
m, and a SiN film 46 having a thickness of 100 nm is laminated respectively, and then a thin SiN film 43 and a SiO ₂ film 42 are formed.
Ion implantation such as boron through the source (S) /
The respective regions 70a and 70b of the drain (D) are formed.

Next, in the steps of FIGS. 3A and 3B described above, a state where the poly-Si film pattern 45a is left is formed on the SiN film pattern 43a to form a shallow junction for LDD. Ion implantation is performed (FIG. 6B).

In this way, the miniaturization process of the present invention is carried out by MO.
It can be applied to the manufacture of S-transistors.

Further, the above-mentioned bipolar transistor and M
It is also possible to fabricate BiCMOS transistors on the same Si substrate by combining the two examples of OS transistors.

[0056]

As described above, according to the present invention,
By using self-alignment technology instead of sidewalls, it becomes possible to stabilize the emitter electrode in a bipolar transistor and the gate electrode in a MOS transistor in a process manner and easily miniaturize them, thereby improving the performance of a transistor such as a bipolar transistor or a MOS transistor. Can be realized.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view for forming a basic structure according to the present invention.

FIG. 2 is a process sectional view (I) showing a first embodiment in which the present embodiment is applied to manufacture of a bipolar transistor.

FIG. 3 is a process sectional view (II) showing a first embodiment in which the present embodiment is applied to manufacture of a bipolar transistor.

FIG. 4 is a process sectional view (III) showing a first example in which the present example is applied to manufacture of a bipolar transistor.

FIG. 5 is a process sectional view showing the method of forming the activation layer in the first embodiment.

FIG. 6 is a process sectional view showing a second embodiment in which the present invention is applied to manufacture of a MOS transistor.

FIG. 7 is a schematic cross-sectional view of a bipolar transistor manufactured by a conventional method.

FIG. 8 is a process cross-sectional view showing a conventional manufacturing process of a bipolar transistor.

9A to 9C are process cross-sectional views showing an example of forming sidewalls caused by RIE.

FIG. 10 is a process cross-sectional view showing another example of formation of sidewalls caused by RIE.

[Explanation of symbols]

1 N-collector layer 2 P-base layer 3 N ⁺ -emitter layer 4 P-channel stop layer 5,8 SiO ₂ film 7 P-poly Si film 10, 28, 28 a, 28 b SiO ₂ side wall (sidewall) 11 poly -Si film 21, 31, 41 Si substrate 22 poly-Si film 23,27,27a SiO ₂ film 24 resist pattern 25 emitter apertures 30 Si grooves 32, 42 SiO ₂ film (thin oxide film) 33,36,43, 46 SiN film 35, 45 poly-Si film 35a, 45a poly-Si film pattern 35b, 45b unoxidized poly-Si film pattern 36a, 43a, 46a SiN film pattern 37, 47 resist pattern 38, 48 SiO ₂ film 49 SiO ₂ sidewalls (sidewall) 50a unoxidized poly-Si film 51 SiO ₂ film 5 Buried emitter electrode for poly-Si film 53a poly-Si emitter electrode 56 P layer (link base layer) 57 P ⁺ layer (extraction base layer) 61 emitter layer (N ⁺ layer) 62 base layer (P layer) 70a source region 70b Drain region 71 LDD region

Claims (6)

[Claims] 1. A first insulating film on a semiconductor substrate, a second insulating film on the first insulating film, a first conductive film on the second insulating film, and a third insulating film on the first conductive film. A step of sequentially laminating, a step of forming a resist pattern on the third insulating film having the above-mentioned laminated structure, and a step of removing the third insulating film and the first conductive film by using the resist pattern as a mask to form a resist pattern under the resist pattern. 3 step of forming the insulating film pattern and the first conductive film pattern, oxidizing the side wall of the first conductive film pattern exposed in the removing step, and removing the oxidized portion of the first conductive film pattern. Removing the second insulating film using the oxidized first conductive film pattern as a mask to form a second insulating film pattern under the unoxidized first conductive film pattern; and removing the unoxidized first conductive film pattern. Process and on the second insulating film pattern After forming the fourth insulating film on
Forming a sidewall made of a fourth insulating film on the side wall of the second insulating film by etching and removing the first insulating film; and a step of removing the second insulating film pattern and the fourth insulating film sidewall. Embedding a second conductive film, oxidizing the surface of the second conductive film, removing the second insulating film and the first insulating film under the second insulating film, and the second insulating film And a step of burying a third conductive film in a portion where the first insulating film is removed under the second insulating film. 2. A base lead electrode for the second conductive film,
The method of manufacturing a semiconductor device according to claim 1, wherein the third conductive film is used as an emitter extraction electrode. 3. A first insulating film on a semiconductor substrate, a second insulating film on the first insulating film, a first conductive film on the second insulating film, and a third insulating film on the first conductive film. A step of sequentially laminating, a step of forming a resist pattern on the third insulating film having the above-mentioned laminated structure, and a step of removing the third insulating film and the first conductive film by using the resist pattern as a mask to form a resist pattern under the resist pattern. 3 step of forming the insulating film pattern and the first conductive film pattern, oxidizing the side wall of the first conductive film pattern exposed in the removing step, and removing the oxidized portion of the first conductive film pattern. Removing the second insulating film using the oxidized first conductive film pattern as a mask to form a second insulating film pattern under the unoxidized first conductive film pattern; and removing the unoxidized first conductive film pattern. Process and the second insulating film pattern A step of forming a ring base layer as a mask, and a step of forming a fourth insulating film on the second insulating film pattern,
Forming a sidewall made of a fourth insulating film on the side wall of the second insulating film by etching and removing the first insulating film; and a step of removing the second insulating film pattern and the fourth insulating film sidewall. A step of embedding a second conductive film to form a base extraction electrode; a step of oxidizing the surface of the second conductive film; and a step of removing the second insulating film and the first insulating film under the second insulating film. And a step of burying a third conductive film in the removed portion of the second insulating film and the first insulating film below the second insulating film to form an emitter extraction electrode, and diffusion using the third conductive film or the above process. A method of manufacturing a semiconductor device, comprising the step of removing a first insulating film and forming a base layer and an emitter layer by using ion implantation before embedding a third conductive film. 4. A SiO ₂ film as the first insulating film, a SiN film as the second and third insulating films, and a poly-Si film or amorphous S as the first, second and third conductive films.
The method for manufacturing a semiconductor device according to claim 1, wherein an i film is used. 5. A first insulating film on a semiconductor substrate, a second insulating film on the first insulating film, a first conductive film on the second insulating film, and a third insulating film on the first conductive film. A step of sequentially laminating, a step of forming a resist pattern on the third insulating film having the above-mentioned laminated structure, and a step of removing the third insulating film and the first conductive film by using the resist pattern as a mask to form a resist pattern under the resist pattern. A step of forming a third insulating film pattern and a first conductive film pattern, a step of forming a source / drain region using the third insulating film pattern and the first conductive film pattern as a mask, and a first conductive film exposed in the removing step. A step of oxidizing the side wall of the film pattern; a step of removing the second insulating film and the first insulating film using the unoxidized portion of the first conductive film pattern as a mask to form a shallow impurity introduction region in the semiconductor substrate. Specially including The method of manufacturing a semiconductor device according to. 6. A SiO ₂ film as the first insulating film, a SiN film as the second and third insulating films, and a poly-Si film or amorphous S as the first, second and third conductive films.
The method for manufacturing a semiconductor device according to claim 5, wherein an i film is used.