JPH0732376B2 - Time slot allocation method - Google Patents
Time slot allocation methodInfo
- Publication number
- JPH0732376B2 JPH0732376B2 JP62138066A JP13806687A JPH0732376B2 JP H0732376 B2 JPH0732376 B2 JP H0732376B2 JP 62138066 A JP62138066 A JP 62138066A JP 13806687 A JP13806687 A JP 13806687A JP H0732376 B2 JPH0732376 B2 JP H0732376B2
- Authority
- JP
- Japan
- Prior art keywords
- speed
- bit
- bits
- time slot
- allocation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は複数の低速回線を収容するビット多重装置にお
いて，高速回線側速度により割り付け総ビット数を計算
し，低速回線側の速度により割り付けビット数を決定
し，割り付け総ビット数に割り付けるタイムスロット方
式に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention is a bit multiplexer that accommodates a plurality of low-speed lines, calculates the total number of bits allocated by the speed of the high-speed line, and allocates the bits by the speed of the low-speed line. It relates to a time slot method in which the number is determined and assigned to the total number of assigned bits.
従来，この種のタイムスロット割り付け方式は，第２図
に示すよに，高速側１フレームをＸとし，高速側速度を
Ｙとすると高速側総ビット数Ｚは， Ｚ＝X/1/Y ………（１） で表わされる。Conventionally, this type of time slot allocation system has a total number of bits on the high-speed side, Z = X / 1 / Y, where X is one frame on the high-speed side and Y is the speed on the high-speed side, as shown in FIG. ... (1)
例にとると,1フレーム・5mS,高速側速度・48KB/Sとする
と，高速側総ビット数Ｚ＝5mS/1/48KB/S＝240ビットな
る。For example, if one frame is 5 mS and the speed is 48 KB / S on the high speed side, the total number of bits on the high speed side is Z = 5 mS / 1/48 KB / S = 240 bits.
ここで高速側タイムスロットに割り付ける場合，割り付
け順序が有る。When assigning to the high-speed time slot, there is an assignment order.
まず，フレームビット（Ｆ）201を１ビット割り付け，
次に対局制御CHビット（Ｃ）202を12ビットを全体１フ
レームの等間隔になるように割り付ける。次に，低速回
線の速度によりCH Dataビット（Ｄ）203を速度に応じた
ビット数を割り付ける。例として，速度回線の速度を1
9.2KB/Sとすると割り付けCH Dataビットは96ビットにな
り割り付け間隔は（２ビット,3ビット…）の繰り返しで
割り付ける。First, 1 bit is allocated to the frame bit (F) 201,
Next, 12 bits of the game control CH bit (C) 202 are allocated so as to be equally spaced over one frame. Next, the CH Data bit (D) 203 is assigned the number of bits according to the speed according to the speed of the low speed line. As an example, the speed of the speed line is 1
With 9.2 KB / S, the allocation CH Data bit becomes 96 bits and the allocation interval is allocated by repeating (2 bits, 3 bits ...).
しかしながら，上述の従来の割り付け方式は，低速回線
側速度の総合計高速側速度に対して，十分に空きがある
が｛（48KB/S−19.2KB/S×２）＝9.6KB/S:余り速度｝，
最初に19.2KB/Sを割り付けた時点で,Fビット,Cビット・
D1ビットがあるので，次の19.2KB/SのD2ビットを割り付
け不可能となる。このように従来のタイムスロット割り
付け方式では伝送効率が低下するという欠点がある。However, the above-mentioned conventional allocation method has a sufficient vacancy for the total high-speed speed of the low-speed line-side speed, but {(48KB / S-19.2KB / S x 2) = 9.6KB / S: remainder speed},
When 19.2 KB / S is first allocated, F bit, C bit
Since there is a D 1 bit, the next 19.2KB / S D 2 bit cannot be allocated. As described above, the conventional time slot allocation method has a drawback that the transmission efficiency is lowered.
そこで，本発明の技術的課題は上記欠点に鑑み，総和が
高速回線より小さい低速回線速度を，高速側速度に対し
て効率良く割り付けることができるタイムスロット割り
付け方式を提供することである。In view of the above-mentioned drawbacks, the technical problem of the present invention is to provide a time slot allocation method capable of efficiently allocating a low speed line speed whose sum is smaller than that of a high speed line to a high speed side speed.
本発明によれば，複数の低速回線を収容するビット多重
装置と対向するビット多重装置を，中継回線で接続した
通信システムのタイムスロット割り付け方式において，
高速回線の速度により，割り付け総ビット数を計算する
手段と低速回転の速度により，割り付け総ビット中に等
間隔に割付ける手段と対局するビット多重装置を制御す
る為に制御CH用ビットを割り付ける手段と割り付け順番
を制御する手段を有する，タイムスロット割り付け方式
が得られる。According to the present invention, in a time slot allocation method of a communication system in which a bit multiplexer that accommodates a plurality of low-speed lines and a bit multiplexer that faces the bit multiplexer are connected by a relay line,
A means for calculating the total number of allocated bits according to the speed of the high-speed line, and a means for allocating at equal intervals in the total allocated bits for the speed of low-speed rotation, and a means for allocating control CH bits for controlling the bit multiplexer to play And a time slot allocation method having means for controlling the allocation order.
次に本発明について第１図を参照し説明する。 Next, the present invention will be described with reference to FIG.
高速側速度を48KB/Sとし，対局制御CH信号（Ｃ）＝2.4K
B/S,低速側速度１＝19.2KB/S,低速側速度２＝19.2KB/S
とする。第１図の開始先頭ビットにフレームビット
（Ｆ）１を１ビット割り付ける。次に，低速回線側速度
１＝19.2KB/Sを割り付ける。割り付けビット＝96ビッ
ト，割り付け間隔（２ビット,3ビット…）でD1,2を割り
付ける。Ｆビットを中心にＦビットより前１ビット目を
最終ビット,Fビット後２ビット目を第１番目として行な
う。次に低速回線側速度２＝19.2KB/Sを割り付ける。低
速回線側速度１と速度は同じなので，割り付け間隔（２
ビット,3ビット…）でD2,3を割り付ける。次に，対局制
御CH（Ｃ）2.4KB/Sを割り付けビット＝12ビット，割り
付け間隔＝20ビットごとに割り付ける。High speed side is set to 48KB / S, game control CH signal (C) = 2.4K
B / S, low speed side 1 = 19.2KB / S, low speed side 2 = 19.2KB / S
And One frame bit (F) 1 is allocated to the start head bit in FIG. Next, the low speed side speed 1 = 19.2KB / S is allocated. Allocation bits = 96 bits, D1, 2 are allocated at allocation intervals (2 bits, 3 bits ...). Centering on the F bit, the first bit before the F bit is the last bit and the second bit after the F bit is the first bit. Next, allocate the low speed line speed 2 = 19.2KB / S. Since the speed is the same as speed 1 on the low-speed line side, the allocation interval (2
Bits, 3 bits ...) are used to assign D2,3. Next, assign 2.4KB / S to the control channel CH (C) for each allocation bit = 12 bits and allocation interval = 20 bits.
以上説明したように，本発明は，タイムスロット割り付
ける際，対局制御用CHを一番最後に割り付けることによ
り，従来，低速回線速度の総和が高速回線より小さく，
多重できるのであるが，割り付け不可の為，多重できな
いという欠点を解消することができるから効率を上げる
効果がある。As described above, according to the present invention, when allocating a time slot, the CH for controlling the game is allocated at the end so that the sum of the low-speed line speeds is smaller than that of the high-speed line.
Although it is possible to multiplex, it is possible to eliminate the disadvantage that multiplexing is not possible because allocation is not possible, which has the effect of increasing efficiency.
第１図は本発明の割り付け図，第２図は従来の割り付け
図である。 1:フレームビット（Ｆ）,2:低速回線速度１（D1）,3:低
速回線速度２（D2）,4:対局制御CH（Ｃ）,201:フレーム
ビット（Ｆ）,202:対局制御CH（Ｃ）,203:低速回線速度
１（D1）,204:低速回線速度２（D2）。FIG. 1 is an allocation diagram of the present invention, and FIG. 2 is a conventional allocation diagram. 1: Frame bit (F), 2: Low speed line speed 1 (D 1 ), 3: Low speed line speed 2 (D 2 ), 4: Opposition control CH (C), 201: Frame bit (F), 202: Opposition Control CH (C), 203: Low speed line speed 1 (D 1 ), 204: Low speed line speed 2 (D 2 ).
Claims (1)
と対向するビット多重装置を中継回線で接続した通信シ
ステムのタイムスロット割り付け方式において，高速回
線の速度により割り付け総ビット数を計算する手段と，
低速回転の速度により割り付け総ビット中に等間隔に割
り付ける手段と，対局するビット多重装置を制御する為
に制御CH用ビットを一番最後に割り付ける手段と，割り
付け順番を制御する手段とを有し，タイムスロット上の
割り付けビットを効果的に割り付け，伝送効率を上げる
ことを特徴とするタイムスロット割り付け方式。1. A means for calculating the total number of bits to be allocated by the speed of a high speed line in a time slot allocation system of a communication system in which a bit multiplexer which accommodates a plurality of low speed lines and a bit multiplexer which faces the bit multiplexer are connected by a trunk line. ，
It has means for allocating at equal intervals among all allocated bits by the speed of low-speed rotation, means for allocating the control CH bit at the very end to control the bit multiplexer to be played, and means for controlling the allocation order. , Time slot allocation method characterized by effectively allocating allocation bits on time slots to improve transmission efficiency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62138066A JPH0732376B2 (en) | 1987-06-03 | 1987-06-03 | Time slot allocation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62138066A JPH0732376B2 (en) | 1987-06-03 | 1987-06-03 | Time slot allocation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63302634A JPS63302634A (en) | 1988-12-09 |
| JPH0732376B2 true JPH0732376B2 (en) | 1995-04-10 |
Family
ID=15213179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62138066A Expired - Lifetime JPH0732376B2 (en) | 1987-06-03 | 1987-06-03 | Time slot allocation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0732376B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5935220B2 (en) * | 1980-04-28 | 1984-08-27 | 富士通株式会社 | Terminal control method |
-
1987
- 1987-06-03 JP JP62138066A patent/JPH0732376B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63302634A (en) | 1988-12-09 |
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