JPS5779793A - Multi-dimension traffic time division exchanger - Google Patents

Multi-dimension traffic time division exchanger

Info

Publication number
JPS5779793A
JPS5779793A JP15458580A JP15458580A JPS5779793A JP S5779793 A JPS5779793 A JP S5779793A JP 15458580 A JP15458580 A JP 15458580A JP 15458580 A JP15458580 A JP 15458580A JP S5779793 A JPS5779793 A JP S5779793A
Authority
JP
Japan
Prior art keywords
time slot
vacant
channel
transmission
baud
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15458580A
Other languages
Japanese (ja)
Other versions
JPS6316080B2 (en
Inventor
Masamitsu Shiragami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15458580A priority Critical patent/JPS5779793A/en
Publication of JPS5779793A publication Critical patent/JPS5779793A/en
Publication of JPS6316080B2 publication Critical patent/JPS6316080B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
    • H04L12/52—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques

Abstract

PURPOSE:To enable to use time slot effectively, by taking the number of one row of memories in matrix arrangement for vacant time slot selection as the time slot number required for the assignment of data at the highest speed. CONSTITUTION:In assigning 20 channels for signal transmission of 2,400 Baud at the highest speed in 960 channels multiplexity, the matrix for vacant time slot selection is constituted in 48 rows and 20 columns as shown in Figure. 20 time slots for the highest speed signal transmission are assigned to 20 bits to each row. In assigning the channels for the transmission of 2,400 Baud, each column of the matrix is sequantially read out, and when all the bits are vacant, the channel desigrated for the row is assigned. In assigning the channel for the transmission of 240 Baud, the channel designated with the bits where consecutive 2-bit of the read out column are vacant is assigned. The assignment of the channel for the transmission of other speeds can be made similarly.
JP15458580A 1980-11-05 1980-11-05 Multi-dimension traffic time division exchanger Granted JPS5779793A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15458580A JPS5779793A (en) 1980-11-05 1980-11-05 Multi-dimension traffic time division exchanger

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15458580A JPS5779793A (en) 1980-11-05 1980-11-05 Multi-dimension traffic time division exchanger

Publications (2)

Publication Number Publication Date
JPS5779793A true JPS5779793A (en) 1982-05-19
JPS6316080B2 JPS6316080B2 (en) 1988-04-07

Family

ID=15587410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15458580A Granted JPS5779793A (en) 1980-11-05 1980-11-05 Multi-dimension traffic time division exchanger

Country Status (1)

Country Link
JP (1) JPS5779793A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6038999A (en) * 1983-08-12 1985-02-28 Toshiba Corp Exchange control system
JPS615655A (en) * 1984-06-14 1986-01-11 Fujitsu Ltd Multiplex method and multiple exchange system
JPS61164397A (en) * 1985-01-17 1986-07-25 Oki Electric Ind Co Ltd Multi-dimension processing system
JPS6481497A (en) * 1987-09-22 1989-03-27 Nec Corp Multiple access control system for time division multiplex switch

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2208737B (en) * 1987-08-17 1991-08-14 Ainsworth Nominees Pty Ltd Improvements in poker machines
JPH01303180A (en) * 1988-06-01 1989-12-07 Ikyo Kk Game machine
JPH0318389A (en) * 1989-06-16 1991-01-25 Shinjiyou Kenkyu Kaihatsu Kk Illegality preventing device in electronic control type pinball machine

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6038999A (en) * 1983-08-12 1985-02-28 Toshiba Corp Exchange control system
JPS615655A (en) * 1984-06-14 1986-01-11 Fujitsu Ltd Multiplex method and multiple exchange system
JPS61164397A (en) * 1985-01-17 1986-07-25 Oki Electric Ind Co Ltd Multi-dimension processing system
JPS6481497A (en) * 1987-09-22 1989-03-27 Nec Corp Multiple access control system for time division multiplex switch

Also Published As

Publication number Publication date
JPS6316080B2 (en) 1988-04-07

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