ES8702679A1 - Multiple memory loading system. - Google Patents

Multiple memory loading system.

Info

Publication number
ES8702679A1
ES8702679A1 ES543645A ES543645A ES8702679A1 ES 8702679 A1 ES8702679 A1 ES 8702679A1 ES 543645 A ES543645 A ES 543645A ES 543645 A ES543645 A ES 543645A ES 8702679 A1 ES8702679 A1 ES 8702679A1
Authority
ES
Spain
Prior art keywords
memories
gls1
modules
loading system
multiple memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES543645A
Other languages
Spanish (es)
Other versions
ES543645A0 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Espana SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Espana SA filed Critical Alcatel Espana SA
Publication of ES543645A0 publication Critical patent/ES543645A0/en
Publication of ES8702679A1 publication Critical patent/ES8702679A1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17393—Indirect interconnection networks non hierarchical topologies having multistage networks, e.g. broadcasting scattering, gathering, hot spot contention, combining/decombining
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Circuits Of Receivers In General (AREA)
  • Communication Control (AREA)
  • Multi Processors (AREA)
  • Nitrogen Condensed Heterocyclic Rings (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Computer And Data Communications (AREA)
  • Saccharide Compounds (AREA)
  • Debugging And Monitoring (AREA)
  • Information Transfer Between Computers (AREA)

Abstract

Multiple memory loading system with a plurality of intercoupled modules (TCEA/B TCEL/n) including memories and processing means and at least one (TCEA/B) of which is able to transmit each (GLS1) of a plurality of data packets (GLS1/m) to the memories of a number of modules wherein said data packet may then be stored. The transmission of each (GLS1) of said data packets (GLS1/m) from said one module (TCEA/B) only occurs directly to the memories of a number of predetermined modules (TCE1, 14, 27, 40) of an initial set (TCE1/50) and indirectly from said memories to memories of other modules.
ES543645A 1984-06-01 1985-05-30 Multiple memory loading system. Expired ES8702679A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP84200783A EP0162970B1 (en) 1984-06-01 1984-06-01 Multiple memory loading system

Publications (2)

Publication Number Publication Date
ES543645A0 ES543645A0 (en) 1986-11-16
ES8702679A1 true ES8702679A1 (en) 1986-11-16

Family

ID=8192446

Family Applications (1)

Application Number Title Priority Date Filing Date
ES543645A Expired ES8702679A1 (en) 1984-06-01 1985-05-30 Multiple memory loading system.

Country Status (11)

Country Link
US (1) US4866668A (en)
EP (1) EP0162970B1 (en)
JP (1) JPS619056A (en)
AT (1) ATE40501T1 (en)
AU (1) AU578287B2 (en)
DE (1) DE3476503D1 (en)
ES (1) ES8702679A1 (en)
FI (1) FI80183C (en)
IN (1) IN164797B (en)
MX (1) MX157241A (en)
NO (1) NO852033L (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2201066B (en) * 1986-11-14 1991-08-21 Fuji Xerox Co Ltd Storage star network
LU87095A1 (en) * 1987-06-11 1988-04-05 Siemens Ag CIRCUIT ARRANGEMENT FOR A CENTRALLY CONTROLLED TELECOMMUNICATION SYSTEM, ESPECIALLY PCM TELEPHONE SYSTEM, WITH A CENTRAL PART AND WITH THIS CONNECTED GROUPS
AR246648A1 (en) * 1987-10-06 1994-08-31 Siemens Ag Method for switching a line card to an associated line card in telecommunication exchanges, especially pcm time division multiplex telephone exchanges
GB8911395D0 (en) * 1989-05-18 1989-07-05 British Telecomm Data communications network
JPH04291538A (en) * 1991-03-19 1992-10-15 Fujitsu Ltd Down-load system using standby line
US5224100A (en) * 1991-05-09 1993-06-29 David Sarnoff Research Center, Inc. Routing technique for a hierarchical interprocessor-communication network between massively-parallel processors
US5262906A (en) * 1992-06-19 1993-11-16 Alcatel Network Systems, Inc. Message routing for SONET telecommunications maintenance network
US5581778A (en) * 1992-08-05 1996-12-03 David Sarnoff Researach Center Advanced massively parallel computer using a field of the instruction to selectively enable the profiling counter to increase its value in response to the system clock
US5579527A (en) * 1992-08-05 1996-11-26 David Sarnoff Research Center Apparatus for alternately activating a multiplier and a match unit
US5586289A (en) * 1994-04-15 1996-12-17 David Sarnoff Research Center, Inc. Method and apparatus for accessing local storage within a parallel processing computer
GB9412553D0 (en) 1994-06-22 1994-08-10 At & T Global Solutions Intern Method and apparatus for distributing software
DE4438698A1 (en) * 1994-10-29 1996-05-02 Sel Alcatel Ag Method of loading multi-computer systems
DE4438697A1 (en) * 1994-10-29 1996-05-02 Sel Alcatel Ag Method for loading multi-computer systems
DE19520030C1 (en) * 1995-05-31 1996-05-15 Siemens Ag Modular communication network programme structure realising method
JP3698761B2 (en) * 1995-07-19 2005-09-21 富士通株式会社 Information transfer method and information transfer apparatus
US5910179A (en) * 1996-10-25 1999-06-08 Pitney Bowes Inc. Method and system for transmitting data within a tree structure and receiving a confirmation or status therefor
US6810408B1 (en) * 2000-05-31 2004-10-26 International Business Machines Corporation Method and apparatus for controlling cascading e-mail distribution

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1108325B (en) * 1978-04-10 1985-12-09 Cselt Centro Studi Lab Telecom ROAD PROCEDURE AND DEVICE FOR A PACKAGE SWITCHING COMMUNICATION NETWORK
JPS6023535B2 (en) * 1978-11-22 1985-06-07 株式会社リコー Facsimile broadcast communication method
BE876025A (en) * 1979-05-04 1979-11-05 Bell Telephone Mfg SIGNALING SYSTEM
US4347498A (en) * 1979-11-21 1982-08-31 International Business Machines Corporation Method and means for demand accessing and broadcast transmission among ports in a distributed star network
JPS57134741A (en) * 1981-02-12 1982-08-20 Nec Corp Program on-line load system
JPS5875351A (en) * 1981-10-30 1983-05-07 Fuji Xerox Co Ltd Relaying system of digital signal
SE428859B (en) * 1981-12-15 1983-07-25 Ellemtel Utvecklings Ab DEVICE FOR CHARGING THE MEMORY IN A TELECOMMUNICATION SWITCH
US4525830A (en) * 1983-10-25 1985-06-25 Databit, Inc. Advanced network processor
US4550397A (en) * 1983-12-16 1985-10-29 At&T Bell Laboratories Alternate paths in a self-routing packet switching network

Also Published As

Publication number Publication date
IN164797B (en) 1989-06-03
ES543645A0 (en) 1986-11-16
EP0162970B1 (en) 1989-01-25
US4866668A (en) 1989-09-12
MX157241A (en) 1988-11-07
AU578287B2 (en) 1988-10-20
AU4270485A (en) 1985-12-05
JPS619056A (en) 1986-01-16
EP0162970A1 (en) 1985-12-04
ATE40501T1 (en) 1989-02-15
FI80183B (en) 1989-12-29
NO852033L (en) 1985-12-02
DE3476503D1 (en) 1989-03-02
FI80183C (en) 1990-04-10
FI852161L (en) 1985-12-02
FI852161A0 (en) 1985-05-30

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19990918