JPS5668092A - Time series exchange system - Google Patents

Time series exchange system

Info

Publication number
JPS5668092A
JPS5668092A JP14469679A JP14469679A JPS5668092A JP S5668092 A JPS5668092 A JP S5668092A JP 14469679 A JP14469679 A JP 14469679A JP 14469679 A JP14469679 A JP 14469679A JP S5668092 A JPS5668092 A JP S5668092A
Authority
JP
Japan
Prior art keywords
sequence
speed
sequences
speeds
multiplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14469679A
Other languages
Japanese (ja)
Inventor
Masaaki Murai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14469679A priority Critical patent/JPS5668092A/en
Publication of JPS5668092A publication Critical patent/JPS5668092A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1623—Plesiochronous digital hierarchy [PDH]
    • H04J3/1629—Format building algorithm

Abstract

PURPOSE:To multiply all speeds, by setting integral multiples of 60 into the multiplied number, in case that the third speed-sequence line is multiplied in time division to sequences where channel basic speeds are 600bits/s and 800bits/s respectively. CONSTITUTION:Between sequence 1 of speed (bis/s) 600, 2,400, 4,800, 9,600 and 48,000 and sequence 2 of speed 800, 3,200, 12,800 and 64,000, 9,600 of sequence 1 is three times as high as 3,200 of sequence 2. Consequently, when the third speed sequence with 9,600 added, namely, 800, 3,200, 6,400, 9,600, 12,800 and 64,000 is constituted newly, this sequence can keep the relation of the integral ratio for sequences 1 and 2, and sequences 1 and 2 are mixed and stored. That is, the multiplexing number becomes the integral multiple of 2X2X3X5=60 by selecting 3,200 bits/s as the channel basic speed, and all speeds multiplied to constitute a time division exchange system.
JP14469679A 1979-11-08 1979-11-08 Time series exchange system Pending JPS5668092A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14469679A JPS5668092A (en) 1979-11-08 1979-11-08 Time series exchange system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14469679A JPS5668092A (en) 1979-11-08 1979-11-08 Time series exchange system

Publications (1)

Publication Number Publication Date
JPS5668092A true JPS5668092A (en) 1981-06-08

Family

ID=15368136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14469679A Pending JPS5668092A (en) 1979-11-08 1979-11-08 Time series exchange system

Country Status (1)

Country Link
JP (1) JPS5668092A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943655A (en) * 1982-09-03 1984-03-10 Nec Corp Line editing system
JPH0278338A (en) * 1988-09-14 1990-03-19 Fujitsu Ltd Time division multiplex timing signal generating system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943655A (en) * 1982-09-03 1984-03-10 Nec Corp Line editing system
JPH0278338A (en) * 1988-09-14 1990-03-19 Fujitsu Ltd Time division multiplex timing signal generating system

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