JPH07321640A - Programmable logic circuit - Google Patents

Abstract

PURPOSE:To reduce a device packaging area by processing plural clock signals whose frequencies differ from each other by using a single device. CONSTITUTION:A desired logic is programmed at first to a logic block 4 to realize a desired function in the inside of a chip, and a desired signal direction is confirmed by a program because input and output terminals 2 are two-way terminals as they are. The prescribed connection information is programmed even to a wiring region 3 and clock selection circuits 9, 10 select either of clock signals of two different systems from the clock signal input terminals 7 and 8 by using a program depending on a speed of input and output signals relating to the logic circuit realized by each logic block 4. The selected clock signal is distributed to a clock terminal 6 of a register 5 provided to the output of each logic block 4 and a region 3 connecting to input output ports 12, 13 of a memory sub-system 14 is programmed to decide the operating made of the system 14.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an FPGA (Field Program)
Used for mable Gate Array). The present invention is suitable for use as an interface circuit between two systems which require different speeds. The present invention is a FIFO (First In First Ou)
t) A technique for realizing a circuit configuration using a memory or a memory map I / O in a single FPGA.

[0002]

2. Description of the Related Art An FPGA, that is, a programmable logic circuit, is a gate array that can be prototyped by a user himself / herself in a few minutes by using a dedicated writing machine and design software. In a conventional programmable logic circuit, a clock signal supplied to a register that holds data is common to all registers, and is of a type that enables synchronous operation with a single clock of the entire device, or an ordinary type. There are some that can be operated asynchronously by treating them in the same way as signal lines.

The former can reduce the clock skew and enable high-speed operation of the device, but the entire chip can handle only a single clock, and different clocks are used on the input side and the output side, such as communication protocol processing. It was difficult to apply to a system operating at speed. On the other hand, in the latter, it is possible to operate the inside of the device with multiple clocks, but when sending and receiving signals between parts that operate with different clocks inside the chip, the operation is asynchronous and continuous. It is necessary to pass through the memory for the accurate transfer of the data.

[0004]

The memory required here needs to have a so-called FIFO memory structure, but a programmable memory incorporating a conventional memory having a structure for performing writing and reading at a single speed is used. With a logic circuit, it is difficult to construct a FIFO memory that requires different clocks on the input side and the output side.

That is, when the data rate of the input side and the data rate of the output side of the signal such as communication protocol processing are determined by external factors, respectively, and the speeds are different, a single programmable logic circuit can be used to obtain a desired circuit. Is impossible to achieve. Further, in the communication circuit, even if the data rate on the input side and the output side is single, in many cases, a single device processes a circuit that performs the opposite function of the two circuits of the receiving circuit and the transmitting circuit. In this case, the operating speed of the receiving circuit and the operating speed of the transmitting circuit are generally not completely synchronized. It is extremely difficult to construct such a circuit with a conventional single programmable logic circuit.

The present invention has been made in view of such a background, and an object thereof is to provide a programmable logic circuit capable of handling a plurality of clock signals having different frequencies in a single device. Another object of the present invention is to provide a programmable logic circuit capable of handling a plurality of clock signals in a single device by using a memory having a plurality of input / output ports.

[0007]

The present invention is characterized in that the inside of one programmable logic circuit is divided into a plurality of different speed regions by clock signals having different frequencies to form a logic circuit. That is, the first aspect of the present invention is
A plurality of logic blocks whose operation logic can be changed by external access, a plurality of registers provided on the output side of this logic block for temporarily holding the output logic value of this logic block, this logic block and / or this register The programmable logic circuit includes a wiring region that connects the two and can be changed by an external access, and an input / output terminal that inputs / outputs a signal to / from the external wiring region.

A feature of the present invention is that a plurality of clock signal input terminals for data writing and reading timing of the register are provided, and the register is externally connected to any one of the plurality of clock signal input terminals. There is a means for selectively connecting by accessing from.

Thus, the inside of one programmable logic circuit can be divided into a plurality of different speed regions for use.

The M registers are provided (M is a natural number), the clock signal input terminals are provided in two, and the means for selectively connecting are N (N is a natural number, N ≦ M) registers for the clock. It is desirable to provide means for selectively connecting to either one of the input terminals and means for selectively connecting (MN) registers to either of the clock input terminals.

As a result, the area composed of N registers and the area composed of (MN) registers can be operated at different speeds.

It is preferable that a memory having a plurality of input / output ports is provided, and the input / output ports are respectively connected to the wiring areas.

Thus, one memory can be commonly connected and used in respective areas having different speeds.

The memory area may be divided into a plurality of areas, a plurality of input / output ports may be provided in each of the memory areas, and the input / output ports may be connected to the wiring area. .

With this configuration, it is possible to independently write and read data at different speeds by using a plurality of divided memory areas.

As a second aspect of the present invention, a clock signal is wired by a program using input / output terminals and a wiring area without having a dedicated clock signal input terminal and wiring for a register, and a plurality of two or more clock signals are provided. It is possible to handle a plurality of clock signals in a single programmable logic circuit by using a memory having a plurality of input / output ports by inputting the clock signal of 1 to any register. In this way, a very flexible multi-clock synchronization system can be constructed. That is, a second aspect of the present invention is to provide a plurality of logic blocks whose operational logic can be changed by an external access, and a plurality of logic blocks that are provided on the output side of this logic block and temporarily hold the output logic value of this logic block. A programmable logic circuit that includes a register, a wiring area that connects this logic block and / or this register and can be changed by external access, and an input / output terminal that inputs and outputs signals to this wiring area from the outside. is there.

Here, a feature of the present invention is that the memory is provided with a plurality of input / output ports, the input / output ports are respectively connected to the wiring areas, and a clock signal is supplied to the input / output terminals. The register is provided with means for inputting a clock signal through the wiring area.

Also in this case, the memory area of the memory is divided into a plurality of areas, and a plurality of input / output ports are provided in each of the memory areas, and the input / output ports are connected to the wiring area, respectively. You can

[0019]

The plurality of clock signal input terminals and the register provided are selectively connected to any one of the plurality of clock signal input terminals by external access.

For example, M registers (M is a natural number) are provided, two clock signal input terminals are provided, and the means for selectively connecting is N (N is a natural number, N ≦ M) registers for the clock input. Selectively connect to either one of the terminals,
(MN) registers are selectively connected to either one of the clock input terminals.

Further, it is also possible to use a memory having a plurality of input / output ports by connecting them to the wiring regions.

As a result, N registers and (M-
N) The registers can be operated at different speeds. Therefore, it can be used as an interface between different speed systems. In this case, the memory can be operated as a FIFO memory or a memory map I / O.

If a memory having a plurality of divided memory areas is used, a plurality of input / output ports can be provided in each of the memory areas and used as a plurality of independent memories.

Further, the clock signal is supplied to the input / output terminal without providing the clock signal input terminal and the dedicated wiring for the clock signal from the clock signal input terminal to the register, and the register receives the clock signal through the wiring area. You may input it. For this, the memory having the plurality of input / output ports described above is used. This makes it possible to construct a very flexible multiple clock synchronization system.

That is, by arranging a memory inside the programmable logic circuit and selecting a clock input from a plurality of clock signals for the register, the data rate of the signal input side and the data rate of the output side of the signal such as communication protocol processing. When the circuits are determined by external factors and the speeds thereof are different, a desired circuit can be easily realized by the elements inside the programmable logic circuit. In addition, in a communication circuit, even if the data rate on the input side and the output side is single, in many cases, a single device processes a circuit that performs the opposite movement of the two circuits of the receiving circuit and the transmitting circuit. In general, the operating speed of the receiving circuit and the operating speed of the transmitting circuit are often not completely synchronized. Even for such a circuit, the present invention easily realizes the function with a single programmable logic circuit. it can.

[0026]

【Example】

(First Embodiment) The configuration of the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of a first embodiment device of the present invention. FIG. 2 is a block diagram of the memory subsystem.

According to the present invention, eight logic blocks 4 whose operation logic can be changed by an external access, and a plurality of logic blocks 4 provided on the output side of the logic block 4 for temporarily holding the output logic value of the logic block 4 are provided. Register 5 and a wiring area 3 which connects the logic block 4 and / or the register 5 and can be changed by an external access, and an input / output terminal 2 for inputting / outputting a signal to / from the wiring area 3.
It is a programmable logic circuit 1 provided with.

Here, the feature of the present invention is that two clock signal input terminals 7 and 8 for data writing and reading timing of the register 5 are provided, and the register 4 is provided with these two clock signal input terminals 7 and 8. Any one of them is provided with clock selection circuits 9 and 10 as means for selectively connecting by external access. The register 5 is provided with a clock terminal 6 for inputting a clock signal.

In the first embodiment of the present invention, as shown in FIG. 2, two I / O ports 12 are provided as the memory subsystem 14.
The memory 11 is provided with 1 and 13, and the input / output ports 12 and 13 are connected to the wiring region 3, respectively. The input / output ports 12 and 13 are composed of address terminals 15 and 17 and data terminals 16 and 18, respectively.

Next, the operation of the first embodiment of the present invention will be described. In order to realize a desired function inside the chip, first, a desired logic is programmed in the logic block 4. The input / output terminal 2 is a bidirectional terminal as it is, but a desired signal direction is fixed by a program. Then, predetermined wiring information is programmed in the wiring area 3.
The clock selection circuits 9 and 10 select two different clock signals from the clock signal input terminal 7 or 8 by a program according to the speed of the input / output signals related to the logic circuit realized by each logic block 4. To do. The selected clock signal is distributed to the clock terminal 6 of the register 5 on the output side of each logic block 4.

The memory subsystem 1 is programmed by programming the wiring regions 3 connected to the input / output ports 12 and 13 of the memory subsystem 14, respectively.
4 is determined, and a desired memory function is realized.

Next, an application example of the first embodiment of the present invention will be described with reference to FIGS. 3 to 5 are diagrams showing application examples of the first embodiment of the present invention. The circuit shown in FIG. 3 is an example of a so-called single-phase synchronous circuit in which the entire logic circuit operates at a single clock speed. The memory is also used as a single-port random access memory (hereinafter referred to as RAM). Here, in order to realize this circuit function by the device of the first embodiment of the present invention shown in FIGS. 1 and 2, it is necessary to select either one of the clock signal input terminals 7 or 8 for both the clock selection circuits 9 and 10. Programming. By performing programming in this way, a single in-phase clock is programmed into the programming logic circuit 1.
The entire register 5 can be spread. Also,
For the memory subsystem 14, address terminals 15
And only the data terminal 16 is wired by the wiring area 3,
The address terminal 17 and the data terminal 18 are made unused by not wiring. That is, by using only one of the input / output ports 12 or 13, the memory 11 which is a dual port can be used as a single port R.
Used as AM.

The circuit shown in FIG. 4 corresponds to the memory subsystem 1.
4 is an example in which 4 is used as a FIFO memory. The entire logic circuit is composed of the logic circuits A and F which are in the previous stage of the FIFO memory.
This is a form of being divided into two logic circuits called a logic circuit B in the subsequent stage of the IFO memory. In order to realize this circuit function by the device of the first embodiment of the present invention, first, regarding the clock signal, the clock selection circuit 9 selects the clock signal input terminal 7 and the clock selection circuit 10 selects the clock signal input terminal 8. Program as you would. Further, in the memory subsystem 14, the address area 15 and the data terminal 16 are connected to the logic circuit portion including the register 5 connected to the clock signal input terminal 7, that is, the wiring area so as to be connected to the logic circuit A equivalent portion. 3, while the address terminal 17 and the data terminal 18 are connected to the logic circuit part including the register 5 connected to the clock signal input terminal 8, that is, the part corresponding to the logic circuit B by the wiring area 3. The data terminals 16 are used as write-only terminals and the data terminals 18 are used as read-only terminals. In this way, it is possible to realize a logic circuit that interfaces between two subsystems operating at different speeds via a FIFO memory.

The circuit shown in FIG. 5 corresponds to the memory subsystem 1.
4 is used as a memory map I / O. The entire logic circuit uses the memory as an interface for the logic circuit A.
It is a form divided into two logic circuits, B and B.
In order to realize this circuit function by the device of the first embodiment of the present invention, first, regarding the clock signal, the clock selection circuit 9 selects the clock signal input terminal 7 and the clock selection circuit 10 selects the clock signal input terminal 8. Program as you would. Further, in the memory subsystem 14, the address area 15 and the data terminal 16 are connected to the logic circuit portion including the register 5 connected to the clock signal input terminal 7, that is, the wiring area so as to be connected to the logic circuit A equivalent portion. 3, while the address terminal 17 and the data terminal 18 are connected to the logic circuit portion including the register 5 connected to the clock signal input terminal 8, that is, the portion of the logic circuit B by the wiring area 3. Wire. The difference from FIG. 4 is that the circuit of FIG. 4 makes one input / output port 12 of the memory 11 write-only and the other input / output port 13 read-only, so that a relatively large amount of data differs in order. While suitable for passing to the speed system, the circuit of FIG. 5 differs in that the two subsystems exchange data with each other and the order of the data can be interchanged. In the example of FIG. 5, when a bidirectional signal is processed in one element in a communication system, the data speed is not completely synchronized depending on the signal direction, and the data is operated at a slightly different speed. Suitable for exchanging data between mutual subsystems.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram of the memory subsystem 14 according to the second embodiment of the present invention. The memory subsystem 14 in the second embodiment of the present invention is characterized in that the memory area of the memory 11 is divided into two. The overall configuration is the same as that of the first embodiment device of the present invention shown in FIG. The divided memory areas will be referred to as memory banks 20 and 21, respectively. The memory banks 20 and 21 that can be accessed can be switched by a signal from the memory bank switching terminal 19. Each of the memory banks 20 and 21 has an address terminal 1
5, input / output port 12 including data terminal 16 and address terminal 17, input / output port 13 including data terminal 18
Are connected.

The memory banks 20 and 21 are switched by switching from the memory bank switching terminal 19 to the memory banks 20 and 2.
When “1” is input to both of the 1 and 1, the memory bank 20 inputs / outputs data via the address terminal 15 and the data terminal 16 of the input / output port 12, and the memory bank 21 inputs / outputs the data. Data is input / output through the address terminal 17 and the data terminal 18. When "0" is input from the memory bank switching terminal 19 to both the memory banks 20 and 21, the opposite operation is performed. That is, the memory bank 20 is the input / output port 1
Data is input / output via the address terminal 17 and the data terminal 18 of No. 3, and the memory bank 21 inputs / outputs data via the address terminal 15 and the data terminal 16 of the input / output port 12.

Therefore, the outputs "1" and "0" of the memory bank switching terminal 19 are alternately set to the memory banks 20 and 2.
If it is input to 1, the memory banks 20 or 21 that the input / output ports 12 and 13 can access are switched alternately, and the input / output ports 12 and 13 can use the memory banks 20 and 21 in common. It is possible to operate equivalently to the single area memory 11 described in the first embodiment of the present invention. If the output of the memory bank switching terminal 19 is set to a fixed value of "1" or "0",
The memory bank 20 or 21 that can be accessed by the input / output port 12 or 13 is limited, and the memory bank 20 or 21 can operate equivalently to the existence of two independent memories.

Next, an application example of the second embodiment of the present invention will be described with reference to FIG. FIG. 7 is a diagram showing an application example of the second embodiment of the present invention. The circuit shown in FIG. 7 is an example in which the memory subsystem 14 is used as two independent logic circuits A and B and RAM _A and RAM _B as the memories. In order to realize this circuit function by the programmable logic circuit 1 of the second embodiment of the present invention, first, regarding the clock signal, the clock selection circuit 9 selects the clock signal input terminal 7, and the clock selection circuit 10 selects the clock signal. The signal input terminal 8 is programmed to be selected.
In the memory subsystem 14, the address terminal 15 and the data terminal 16 are the clock signal input terminal 7
A logic circuit part including a register 5 connected to
That is, the wiring region 3 is wired so as to be connected to a portion corresponding to the logic circuit A, while the address terminal 17 and the data terminal 18 include the register 5 connected to the clock signal input terminal 8, that is, the logic circuit portion. Wiring is performed by the wiring region 3 so as to be connected to the portion corresponding to the circuit B. The output of the memory bank switching terminal 19 is "1".
Of the memory bank 20,
The logic circuit B is configured to access the memory bank 21. Alternatively, if the output of the memory bank switching terminal 19 is set to a fixed value of "0", the logic circuit A accesses the memory bank 21 and the logic circuit B accesses the memory bank 20.

According to the second embodiment of the present invention, the two input / output ports 12 and 13 can access the memory at the same time, and since the accessed memory is different, the address conflict does not occur. High-speed 2-port memory access becomes possible.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a block diagram of the apparatus of the third embodiment of the present invention. In the third embodiment of the present invention, the clock terminal 6 of the register 5 is connected to the wiring area 3 and the input / output terminal 2 is used as a clock signal input terminal by a program. This is characterized by using the memory subsystem 14 of FIG. 2 or FIG. 6 shown in the first or second embodiment of the present invention.

In the third embodiment of the present invention, the clock signal is wired by the program using the input / output terminal 2 and the wiring region 3 without having a dedicated clock signal input terminal and wiring to the register 5, and two or more are provided. Input a plurality of clock signals to the arbitrary register 5. Further, the input / output ports 12 and 13 of the memory 11 of the memory subsystem 14
Can be used to handle a plurality of clock signals of different frequencies in a single device. In this way, a very flexible multi-clock synchronization system can be constructed.

[0042]

As described above, according to the present invention,
A programmable logic circuit capable of handling a plurality of clock signals with different frequencies in a single device can be realized. Further, according to the present invention, it is possible to realize a programmable logic circuit capable of handling a plurality of clock signals in a single device by using a memory having a plurality of input / output ports.

As a result, the data rate on the input side and the data rate on the output side of the communication protocol processing and other signals, which are not possible with the conventional programmable logic circuits, are determined by external factors, respectively, and the speeds are determined. Different circuits can be implemented by a single programmable logic circuit. In addition, in a communication circuit, even if the data rates on the input side and the output side are single, a single device often processes a circuit in which the two circuits of the receiving circuit and the transmitting circuit perform the opposite movements. In addition, although the operating speed of the receiving circuit and the operating speed of the transmitting circuit are often not completely synchronized, such a circuit can also be configured by a single programmable logic circuit.

That is, it becomes possible to programmatically configure a synchronous system that operates at a plurality of speeds, which has conventionally been configured using a plurality of programmable logic circuits and memories, in a single device, thus contributing to the reduction of the device mounting area. can do. Further, the present invention is a circuit configuration that is also effective when configuring a multichip module, and a plurality of synchronization systems such as a communication system can be realized by a single multichip module.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an apparatus according to a first embodiment of the present invention.

FIG. 2 is a block configuration diagram of a memory subsystem.

FIG. 3 is a diagram showing an application example of the first embodiment of the present invention.

FIG. 4 is a diagram showing an application example of the first embodiment of the present invention.

FIG. 5 is a diagram showing an application example of the first embodiment of the present invention.

FIG. 6 is a block configuration diagram of a memory subsystem according to a second embodiment of the present invention.

FIG. 7 is a diagram showing an application example of the second embodiment of the present invention.

FIG. 8 is a block configuration diagram of an apparatus according to a third embodiment of the present invention.

[Explanation of symbols]

 1 programmable logic circuit 2 input / output terminal 3 wiring area 4 logic block 5 register 6 clock terminal 7, 8 clock signal input terminal 9, 10 clock selection circuit 11 memory 12, 13 input / output port 14 memory subsystem 15, 17 address terminal 16 , 18 data terminals 19 memory bank switching terminals 20, 21 memory banks

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiro Tsutsui 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (72) Ichihisa Yamada 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (6)

[Claims] 1. A plurality of logic blocks whose operation logic can be changed by an external access, a plurality of registers provided on the output side of this logic block and temporarily holding an output logic value of this logic block, and this logic. In a programmable logic circuit having a wiring area that connects blocks and / or these registers and can be changed by an external access, and an input / output terminal that inputs / outputs signals from / to this wiring area, writing data to the register And a clock signal input terminal for read-out timing, and a means for selectively connecting the register to any one of the plurality of clock signal input terminals by external access. 2. The M registers (M is a natural number) are provided, two clock signal input terminals are provided, and the means for selectively connecting is N (N is a natural number, N ≦ M) registers. 2. The programmable logic circuit according to claim 1, further comprising means for selectively connecting to either one of the clock input terminals, and means for selectively connecting (MN) registers to either one of the clock input terminals. 3. The programmable logic circuit according to claim 1, further comprising a memory having a plurality of input / output ports, each of which is connected to the wiring region. 4. The memory according to claim 3, wherein the memory area is divided into a plurality of areas, each of the memory areas is provided with a plurality of input / output ports, and the input / output ports are respectively connected to the wiring area. Programmable logic circuit. 5. A plurality of logic blocks whose operation logic can be changed by an external access, a plurality of registers provided on the output side of this logic block and temporarily holding an output logic value of this logic block, and this logic. In a programmable logic circuit that has a wiring area that connects blocks and / or this register and that can be changed by external access, and an input / output terminal that inputs and outputs signals to this wiring area, A memory provided with the input / output port is connected to the wiring area, a clock signal is supplied to the input / output terminal, and the register includes means for inputting the clock signal through the wiring area. A programmable logic circuit characterized by the above. 6. The memory according to claim 5, wherein the memory area is divided into a plurality of areas, a plurality of input / output ports are provided in each of the memory areas, and the input / output ports are respectively connected to the wiring area. Programmable logic circuit.