JPH07321412A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH07321412A
JPH07321412A JP11498994A JP11498994A JPH07321412A JP H07321412 A JPH07321412 A JP H07321412A JP 11498994 A JP11498994 A JP 11498994A JP 11498994 A JP11498994 A JP 11498994A JP H07321412 A JPH07321412 A JP H07321412A
Authority
JP
Japan
Prior art keywords
layer
metal layer
solder
bonding
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP11498994A
Other languages
Japanese (ja)
Inventor
Yasuhiro Kito
泰浩 鬼頭
Akira Furuya
章 古谷
Hisao Sudo
久男 須藤
Akito Kuramata
朗人 倉又
Kazuhiko Horino
和彦 堀野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11498994A priority Critical patent/JPH07321412A/en
Publication of JPH07321412A publication Critical patent/JPH07321412A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body

Abstract

PURPOSE:To prevent the quality of a soldered part from being changed due to heat generated when an element is operated by a method wherein a barrier metal layer which does not cause a fusion reaction with both a contact metal and a bonding metal at a soldering temperature by indium solder is inserted between a contact metal layer and a bonding metal layer. CONSTITUTION:Since the uppermost layer of an electrode 6, for substrate connection, which is formed on a semiconductor element 1 is covered with a bonding metal layer 5 which is easily fused with In solder, an oxide film is excluded to the periphery due to surface tension, and a good connection can be performed. In addition, a barrier metal layer 4 which does not cause a fusion reaction with both a contact metal and a bonding metal at a soldering temperature is interposed between a contact metal layer 3 such as gold or the like at the lowermost layer of the electrode 6 for substrate connection and the bonding metal layer 5 at the uppermost layer. As a result, the contact metal is not fused into the In solder due to a temperature rise by heat generated in an operation, it is possible to prevent the plasticity of In from being degraded and the resistance of the In from being increased, and the relaibility of a semiconductor device is enhanced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置、特に半導体
素子をインジウムはんだを用いて実装基板上にはんだ着
け接続するII−VI族化合物半導体レーザ等の構造に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a II-VI group compound semiconductor laser or the like in which a semiconductor element is soldered and connected to a mounting substrate using indium solder.

【0002】II−VI族化合物半導体レーザのように高温
条件で特性劣化の生じやすい半導体素子においては、半
導体素子を放熱体からなる実装基板上に熱伝導性を有す
るはんだ等により搭載し、動作中に素子で発生する熱を
放散して半導体素子の温度上昇の抑制がなされるが、上
記半導体素子の放熱体基板上へのはんだ着け実装に際し
て、放熱性が良い構造で、且つ素子の活性層に歪みを生
じないように柔らかい材質で、しかも発熱を伴わないよ
うな低抵抗の接続が必要になる。
In a semiconductor element such as a II-VI compound semiconductor laser, which is liable to deteriorate in characteristics under high temperature conditions, the semiconductor element is mounted on a mounting substrate made of a heat radiator with solder having thermal conductivity, etc. Although the heat generated in the element is dissipated in the semiconductor element to suppress the temperature rise of the semiconductor element, when the semiconductor element is mounted on the radiator substrate by soldering, it has a structure with good heat dissipation and the active layer of the element is A soft material that does not cause distortion and a low resistance connection that does not generate heat are required.

【0003】[0003]

【従来の技術】例えば、青色レーザであるII−VI族化合
物半導体レーザの材料となるZnSe(亜鉛セレニウ
ム)系の化合物半導体の場合には、結晶成長温度が 250
℃と低く、 300℃以上に加熱すると高抵抗化してしまう
こと、結晶が III−V族化合物半導体と比較して軟らか
いために接続後に歪みが入り易いこと等の特徴があるた
めに、はんだ材に用いることができる材料は、約 156℃
の低融点を有し柔らかいインジウム(In)に限られ
る。
2. Description of the Related Art For example, in the case of a ZnSe (zinc selenium) -based compound semiconductor which is a material for a II-VI group compound semiconductor laser which is a blue laser, the crystal growth temperature is 250.
It has a low temperature of ℃, and increases the resistance when heated to 300 ℃ or more, and because the crystal is softer than the III-V group compound semiconductor, it is likely to be distorted after connection. The material that can be used is about 156 ℃
It has a low melting point and is limited to soft indium (In).

【0004】そして従来、上記半導体レーザは、素子の
放熱のために、放熱体基板(ヒートシンク)上にレーザ
素子の電極(コンタクト金属層)を上記Inはんだを用
いて200℃程度の温度で直にはんだ着け接続した構造に
形成されていた。
In the conventional semiconductor laser, in order to dissipate heat from the element, the electrode (contact metal layer) of the laser element is directly formed on the radiator substrate (heat sink) at a temperature of about 200 ° C. using the In solder. It was formed in a structure that was connected by soldering.

【0005】[0005]

【発明が解決しようとする課題】しかしInは非常に酸
化され易い金属であり、大気中では表面にすぐに酸化膜
が形成されてしまう。そして一度この酸化膜が形成され
てしまうと、 200℃程度のはんだ着け温度では、Inの
み溶けて表面の酸化膜は溶けずに残り、このInの酸化
膜がはんだ着けに際して、通常上記半導体レーザの電極
(コンタクト金属層)として多く用いられている金(A
u)等の金属層とIn半田との間に挟み込まれるため
に、上記電極とInはんだとの濡れ性が損なわれ、接続
不良を生じて抵抗を増大させるという問題を生じてい
た。また、この接続不良回避のため上記酸化膜をIn中
に溶かし込むためには約 400℃程度の高温加熱が必要で
あり、素子性能の劣化を伴うために実施は不可能であっ
た。
However, In is a metal which is very easily oxidized, and an oxide film is immediately formed on the surface in the atmosphere. Once this oxide film is formed, at a soldering temperature of about 200 ° C., only In melts and the oxide film on the surface remains unmelted. Gold (A) which is often used as an electrode (contact metal layer)
Since it is sandwiched between the metal layer such as u) and the In solder, the wettability between the electrode and the In solder is impaired, resulting in poor connection and increased resistance. Further, in order to avoid this connection failure, high temperature heating of about 400 ° C. is required to dissolve the oxide film into In, and this cannot be performed because the device performance is deteriorated.

【0006】そこで上記問題を回避するためには、レー
ザ素子のコンタクト金属層からなる電極全面の最上部
に、例えばInや錫(Sn)のようなInはんだと融合
し易いボンディング金属層を予め形成しておく必要があ
る。このようにすれば、ボンディング金属層とInはん
だとが融合した際にInの酸化膜ははんだ着け部の外面
に押し出されて濡れ性のよい良好なはんだ接続が可能に
なる。
Therefore, in order to avoid the above problem, a bonding metal layer which is easy to fuse with In solder such as In or tin (Sn) is formed in advance on the uppermost part of the entire surface of the electrode composed of the contact metal layer of the laser element. You need to do it. With this configuration, when the bonding metal layer and the In solder are fused, the In oxide film is pushed out to the outer surface of the soldered portion, and good solder connection with good wettability can be achieved.

【0007】しかしここで、前記ZnSe系等のII−VI
族化合物半導体レーザにおいては、活性層側のコンタク
ト材料に、通常、Au、Au/Pd(パラジウム)、A
u/Pt(白金)/Pd等のAu系のコンタクト金属が
用いられていることに起因して更に次のような問題を生
ずる。
However, here, II-VI such as ZnSe system is used.
In group III compound semiconductor lasers, the contact material on the active layer side is usually Au, Au / Pd (palladium), A
The following problems arise due to the use of Au-based contact metals such as u / Pt (platinum) / Pd.

【0008】即ち、上記コンタクト金属に含まれるAu
とはんだに用いるInとは、低温で反応し易く、特に上
記レーザの通電時の昇温によっても反応を起こしてIn
はんだ中にAuが溶け込み、はんだ着け部を硬化させて
活性層に歪みを与えたり、はんだ着け部の抵抗を増大さ
せたりして、上記レーザの特性に経時的な劣化を生じさ
せ、その信頼性を損なうという問題である。
That is, Au contained in the contact metal
And In used for solder easily react with each other at a low temperature, and particularly when the temperature rises when the laser is energized
Au melts into the solder and hardens the soldered part to give strain to the active layer, or increases the resistance of the soldered part, causing deterioration in the characteristics of the laser with time and its reliability. It is a problem that damages.

【0009】そこで本発明は、半導体素子の電極をIn
はんだを用い実装基板上にはんだ着けしてなる半導体装
置において、半導体素子動作時の発熱による素子はんだ
着け部の変質が防止される半導体素子の基板接続用電極
の構造を提供することを目的とする。
Therefore, in the present invention, the electrode of the semiconductor element is In
An object of the present invention is to provide a structure of an electrode for connecting a substrate of a semiconductor element in a semiconductor device which is soldered on a mounting substrate using solder and which prevents deterioration of an element soldering portion due to heat generation during operation of the semiconductor element. .

【0010】[0010]

【課題を解決するための手段】上記課題の解決は、半導
体素子をインジウムはんだを用いて実装基板上にはんだ
着け接続してなる半導体装置において、該はんだ着け接
続に用いられる該半導体素子の基板接続用電極が、最下
層に該半導体素子にオーミックに接続するコンタクト金
属層を有し最上層にインジウムはんだと融合し易い金属
からなるボンディング金属層を有し、且つ該コンタクト
金属層とボンディング金属層との間に該インジウムはん
だによるはんだ着け温度において該コンタクト金属及び
該ボンディング金属の何れとも融合反応を起こさないバ
リア金属層が挿入された構造を有する本発明による半導
体装置によって達成される。
To solve the above-mentioned problems, a semiconductor device in which a semiconductor element is soldered and connected to a mounting board using indium solder is used. The electrode for use has a contact metal layer for ohmic connection to the semiconductor element in the lowermost layer and a bonding metal layer made of a metal that easily fuses with indium solder in the uppermost layer, and the contact metal layer and the bonding metal layer. The semiconductor device according to the present invention has a structure in which a barrier metal layer that does not cause a fusion reaction with either the contact metal or the bonding metal at the soldering temperature with the indium solder is inserted between the two.

【0011】[0011]

【作用】図1は本発明の原理説明用の斜視図で、図中、
1は半導体素子(チップ)、2は実装基板(例えば放熱
体からなる)、3は金あるいは金合金等からなるコンタ
クト金属層、4はバリア金属層、5はIn、Sn等から
なるボンディング金属層、6は基板接続用電極、7はI
nはんだを示す。
FIG. 1 is a perspective view for explaining the principle of the present invention.
Reference numeral 1 is a semiconductor element (chip), 2 is a mounting substrate (for example, a radiator), 3 is a contact metal layer made of gold or gold alloy, 4 is a barrier metal layer, and 5 is a bonding metal layer made of In, Sn or the like. , 6 is a substrate connecting electrode, and 7 is I
n solder is shown.

【0012】本発明に係る半導体装置の構成に用いられ
る半導体素子(チップ)1は図1(a) に示すように、半
導体素子1にオーミックに接続するコンタクト金属層3
を半導体素子に直に接する最下層に有し、最上層にIn
はんだと融合し易い例えばIn、Sn等からなるボンデ
ィング金属層5を有し、且つ前記コンタクト金属層3と
上記ボンディング金属層5との間に、はんだ着け温度に
おいて前記コンタクト金属層3及びボンディング金属層
5の何れとも融合反応を起こさないバリア金属層4が挿
入されてなる基板接続用電極6を備えている。
As shown in FIG. 1A, a semiconductor element (chip) 1 used in the construction of a semiconductor device according to the present invention has a contact metal layer 3 which is ohmic-connected to the semiconductor element 1.
In the lowermost layer directly contacting the semiconductor element, and In in the uppermost layer.
It has a bonding metal layer 5 made of, for example, In, Sn or the like which is easily fused with solder, and the contact metal layer 3 and the bonding metal layer are provided between the contact metal layer 3 and the bonding metal layer 5 at a soldering temperature. 5 is provided with a substrate connecting electrode 6 in which a barrier metal layer 4 that does not cause a fusion reaction is inserted.

【0013】そして図1(b) に示すように、上記半導体
素子1を、Inはんだ7を介し該Inはんだ7に前記基
板接続用電極6を接して放熱体等からなる実装基板2上
に載置し、昇温してInはんだ7を溶融し(この際、I
nはんだ7とボンディング金属層5とは一体化する)、
図1(c) に示すように実装基板2上に半導体素子1をは
んだ着け接続した構造を有する。なおここで、Inはん
だ7を搭載した実装基板2を昇温してInはんだ7を溶
融した後、この溶融したInはんだ7上に前記素子1を
搭載することによって、素子1のボンディング金属層5
を溶融しているInはんだ7と溶融一体化させることで
はんだ着けしてもよい。
Then, as shown in FIG. 1 (b), the semiconductor element 1 is mounted on a mounting substrate 2 composed of a heat radiator or the like with the In solder 7 being in contact with the substrate connecting electrode 6 through the In solder 7. Then, the temperature is raised to melt the In solder 7 (in this case, I
n solder 7 and bonding metal layer 5 are integrated),
As shown in FIG. 1 (c), it has a structure in which a semiconductor element 1 is soldered and connected onto a mounting substrate 2. Here, after the mounting substrate 2 having the In solder 7 mounted thereon is heated to melt the In solder 7, the device 1 is mounted on the molten In solder 7 to bond the bonding metal layer 5 of the device 1.
It may be soldered by melting and integrating with the melted In solder 7.

【0014】本発明においては、半導体素子1に設けら
れる前記基板接続用電極6の最上層がInはんだと融合
し易いボンディング金属層5で覆われるので、たとえそ
の表面及びInはんだ7の表面に酸化膜が形成されてい
てもInはんだ7と上記ボンディング金属層5との融合
に際し表面張力によって上記酸化膜は周辺に排除され、
良好な電気的及び機械的接続がなされる。
In the present invention, since the uppermost layer of the substrate connecting electrode 6 provided on the semiconductor element 1 is covered with the bonding metal layer 5 which easily fuses with the In solder, even if the surface and the surface of the In solder 7 are oxidized. Even if a film is formed, the oxide film is eliminated to the periphery by surface tension when the In solder 7 and the bonding metal layer 5 are fused.
Good electrical and mechanical connections are made.

【0015】また基板接続用電極6の最下層の金或いは
金合金等からなるコンタクト金属層3と最上層の上記ボ
ンディング金属層5との間には、はんだ着け温度におい
てコンタクト金属及びボンディング金属の何れとも融合
反応を起こさないバリア金属層4が介在せしめられてい
るので、はんだ着け時、或いは装置完成後の動作時の発
熱時の昇温によってコンタクト金属がInはんだ中に溶
け込むことがなく、Inの可塑性の劣化(硬くなるこ
と)及び抵抗の増大が防止されて、Inはんだにより実
装基板上に搭載される半導体装置の信頼性が向上する。
Further, between the lowermost contact metal layer 3 made of gold or gold alloy of the substrate connecting electrode 6 and the uppermost bonding metal layer 5 at the soldering temperature, either contact metal or bonding metal is used. In addition, since the barrier metal layer 4 that does not cause a fusion reaction is interposed, the contact metal does not melt into the In solder due to the temperature rise during heat generation during soldering or during operation after completion of the device. Deterioration of plasticity (hardening) and increase of resistance are prevented, and reliability of the semiconductor device mounted on the mounting substrate is improved by the In solder.

【0016】[0016]

【実施例】以下本発明を、金系のコンタクト金属を用い
たZnSe系の半導体レーザにおける一実施例につい
て、図2の斜視模式図及び図3の製造工程断面図を参照
して具体的に説明する。
EXAMPLES The present invention will be specifically described below with reference to an example of a ZnSe based semiconductor laser using a gold based contact metal with reference to the perspective schematic view of FIG. 2 and the manufacturing process sectional view of FIG. To do.

【0017】本発明に係るZnSe系半導体レーザに用
いるレーザ素子11は、例えば図2(a) に示すように、通
常通り、n+ 型ガリウム砒素(GaAs)基板11a 上
に、n型亜鉛硫黄セレニウム(ZnSSe)クラッド層
11b 、n型ZnSe光ガイド層11c 、カドミウム亜鉛セ
レニウム(CdZnSe)活性層11d 、p型ZnSe光
ガイド層11e 、p型ZnSSeクラッド層11f 、ストラ
イプ状p型ZnSeコンタクト層11g が順次積層され、
ストライプ状p型ZnSeコンタクト層11g の両側の段
差部がポリイミド等の絶縁層18で平坦に埋められ、活性
層11d に近い前記ストライプ状のp型ZnSeコンタク
ト層11g 及びその両側の段差部を埋める前記絶縁層18の
上部には、p型ZnSeコンタクト層11g とオーミック
に接続して両側の絶縁層18上まで延在する例えばAu、
Au/Pd、Au/Pt/Pd等の3000Å程度の厚さを
有するAu系コンタクト金属層13と、その上に積層され
た例えば厚さ 500Å以上程度のバリア用ニッケル(N
i)層14と、更にその上に積層された例えば厚さ3μm
程度のボンディング用In層15とからなる本発明に係る
基板接続用電極16が形成され、前記GaAs基板11a の
下面には従来通りのIn層からなるn電極19が形成され
た構造を有する。
The laser element 11 used in the ZnSe semiconductor laser according to the present invention is, as shown in FIG. 2 (a), an n-type zinc-sulfur-selenium substrate on an n + -type gallium arsenide (GaAs) substrate 11a as usual. (ZnSSe) clad layer
11b, an n-type ZnSe light guide layer 11c, a cadmium zinc selenium (CdZnSe) active layer 11d, a p-type ZnSe light guide layer 11e, a p-type ZnSSe cladding layer 11f, and a striped p-type ZnSe contact layer 11g are sequentially stacked,
The step portions on both sides of the striped p-type ZnSe contact layer 11g are evenly filled with an insulating layer 18 such as polyimide, and the striped p-type ZnSe contact layer 11g near the active layer 11d and the step portions on both sides thereof are filled. On the insulating layer 18, for example, Au, which is ohmic-connected to the p-type ZnSe contact layer 11g and extends to the insulating layers 18 on both sides,
An Au-based contact metal layer 13 having a thickness of about 3000 Å such as Au / Pd or Au / Pt / Pd, and a barrier nickel (N) having a thickness of about 500 Å or more laminated thereon.
i) Layer 14 and further laminated thereon, for example 3 μm thick
A substrate connecting electrode 16 according to the present invention is formed of a bonding In layer 15 to a certain extent, and a conventional n electrode 19 of an In layer is formed on the lower surface of the GaAs substrate 11a.

【0018】そして本発明に係る上記ZnSe系半導体
レーザにおいては、図2(b) に示すように、ヒートシン
ク12上の所定の位置に、例えば上記レーザ素子11とほぼ
等しい平面形状を有する厚さ3μm程度のInはんだ17
を予め配設しておき、このヒートシンク12をはんだ着け
温度の 200℃程度に加熱してInはんだ17を溶融した
後、このヒートシンク12上に前記レーザ素子11を基板接
続用電極16の全面が前記Inはんだ17に接するように位
置合わせして搭載し、図2(c) に示すように、レーザ素
子11の基板接続用電極16最上層の前記Inからなるボン
ディング金属層15とInはんだ17とを溶融一体化してレ
ーザ素子11とヒートシンク12との接続がなされる。
In the ZnSe based semiconductor laser according to the present invention, as shown in FIG. 2B, a thickness of 3 μm having a plane shape substantially equal to that of the laser element 11 is provided at a predetermined position on the heat sink 12. About In Solder 17
Is placed in advance, the heat sink 12 is heated to a soldering temperature of about 200 ° C. to melt the In solder 17, and then the laser element 11 is mounted on the heat sink 12 so that the entire surface of the substrate connecting electrode 16 is It is mounted so as to be in contact with the In solder 17, and as shown in FIG. 2C, the bonding metal layer 15 made of In, which is the uppermost layer of the substrate connecting electrode 16 of the laser element 11, and the In solder 17 are mounted. The laser element 11 and the heat sink 12 are connected by fusion and integration.

【0019】上記実施例のZnSe系半導体レーザにお
いては、レーザ素子11の基板接続用電極16の最上層がI
nはんだ17と融合し易いボンディング用In層14で形成
されており、はんだ着けに際しInはんだ17とボンディ
ング用In層14とは融合し一体化するので、その際、ボ
ンディング用In層14及びInはんだ17の表面に形成さ
れている酸化膜は表面張力によって周辺部に排除され、
良好な電気的及び機械的接続がなされる。
In the ZnSe based semiconductor laser of the above embodiment, the uppermost layer of the substrate connecting electrode 16 of the laser element 11 is I.
It is formed of a bonding In layer 14 that easily fuses with the n solder 17, and the In solder 17 and the bonding In layer 14 are fused and integrated during soldering. At that time, the bonding In layer 14 and the In solder The oxide film formed on the surface of 17 is removed to the periphery by surface tension,
Good electrical and mechanical connections are made.

【0020】また、基板接続用電極16の素子に直に接す
る最下層の前記金系コンタクト金属層13と最上層のボン
ディング用In層14との間には何れの金属とも融合しな
いバリア用Ni層14が介在せしめられているので、上記
はんだ着けに際してInはんだ17中にコンタクト金属層
13の金系の金属が溶け込むことがなく、はんだ着け部の
可塑性は十分に柔らかく維持される。よって、はんだ着
けによりレーザ素子11の活性層11d に歪みを与えること
がなく、更に、レーザ動作時のレーザ素子11の発熱によ
りヒートシンク12との間に熱膨張率の差によって生ずる
ストレスも上記可塑性を有するはんだ着け部で十分に吸
収され、動作時に活性層11d がストレスを受けて歪むこ
ともなくなる。
Further, between the lowermost gold-based contact metal layer 13 which is in direct contact with the element of the substrate connecting electrode 16 and the uppermost bonding In layer 14, a barrier Ni layer which does not fuse with any metal is provided. Since 14 is interposed, a contact metal layer is formed in the In solder 17 during the above soldering.
The 13 gold-based metals do not melt, and the plasticity of the soldered part is kept sufficiently soft. Therefore, the active layer 11d of the laser element 11 is not distorted by soldering, and the stress caused by the difference in the thermal expansion coefficient between the laser element 11 and the heat sink 12 due to the heat generation of the laser element 11 during the laser operation also causes the plasticity. Sufficiently absorbed by the soldering portion of the active layer 11d, the active layer 11d is not stressed and distorted during operation.

【0021】以上に述べたように上記実施例に係るZn
Se系半導体レーザにおいては、レーザ素子をヒートシ
ンク上にはんだ接続する際及び動作時の昇温により活性
層に歪みを与えることがなく、またレーザ素子とヒート
シンクとの間の電気的接続及びそれに伴う熱伝導的な接
続も十分に良好に保たれるので、経時的な特性劣化が防
止されて信頼性が向上する。
As described above, Zn according to the above embodiment
In the Se-based semiconductor laser, the active layer is not distorted due to the temperature rise during solder connection of the laser element to the heat sink and during operation, and the electrical connection between the laser element and the heat sink and the heat generated thereby Since the conductive connection is sufficiently maintained, deterioration of characteristics over time is prevented and reliability is improved.

【0022】以下に本発明を、上記ZnSe系半導体レ
ーザの製造方法について、図3の工程断面図を参照して
更に詳しく説明する。 図3(a) 参照 n+ 型GaAs基板11a 上に例えば分子線エピタキシャ
ル(MBE)成長法を用い、n型ZnSSeクラッド層
11b 、n型ZnSe光ガイド層11c 、CdZnSe活性
層11d 、p型ZnSe光ガイド層11e 、p型ZnSSe
クラッド層11f、p型ZnSeコンタクト層11g を順次
積層成長させる。
Hereinafter, the present invention will be described in more detail with reference to the process cross-sectional views of FIGS. 3A and 3B regarding the method of manufacturing the above ZnSe based semiconductor laser. See FIG. 3 (a). An n-type ZnSSe cladding layer is formed on the n + -type GaAs substrate 11a by, for example, molecular beam epitaxial (MBE) growth method.
11b, n-type ZnSe light guide layer 11c, CdZnSe active layer 11d, p-type ZnSe light guide layer 11e, p-type ZnSSe
A clad layer 11f and a p-type ZnSe contact layer 11g are sequentially grown.

【0023】図3(b) 参照 次いで上記p型ZnSeコンタクト層11g を所定の幅の
ストライプ状にパターニングする。パターニングには通
常のフォトリソグラフィが用いられ、エッチングには臭
素(Br)系エッチャントによるウェットエッチング手段が
主として用いられる。
Next, referring to FIG. 3B, the p-type ZnSe contact layer 11g is patterned into a stripe pattern having a predetermined width. Ordinary photolithography is used for patterning, and wet etching using a bromine (Br) -based etchant is mainly used for etching.

【0024】次いで、積層基板の上面に前記ストライプ
状にパターニングしたp型ZnSeコンタクト層11g を
完全に埋める厚さに例えばCVD-SiO2からなる絶縁膜18を
堆積する。
Next, an insulating film 18 made of, for example, CVD-SiO 2 is deposited on the upper surface of the laminated substrate to a thickness that completely fills the p-type ZnSe contact layer 11g patterned in the stripe shape.

【0025】図3(c) 参照 次いで、上記絶縁膜18に例えばドライエッチング手段に
よりp型ZnSeコンタクト層11g の上面を選択的に表
出する溝を形成した後、該積層基板上にAu、Au/P
d、Au/Pt/Pd等からなる厚さ3000Å程度の金系
コンタクト金属層13、厚さ 500Å程度のバリア用Ni層
14及び厚さ3μm程度のボンディング用In層15を順次
蒸着手段により形成する。ここでレーザ素子のp電極で
ある基板実装用電極16が完成する。
Next, as shown in FIG. 3C, a groove for selectively exposing the upper surface of the p-type ZnSe contact layer 11g is formed in the insulating film 18 by, for example, a dry etching method, and then Au, Au is formed on the laminated substrate. / P
d, Au / Pt / Pd, etc., with a thickness of about 3000Å, a gold-based contact metal layer 13, and a thickness of about 500Å, a Ni layer for barrier.
14 and a bonding In layer 15 having a thickness of about 3 μm are sequentially formed by vapor deposition means. Here, the substrate mounting electrode 16 which is the p electrode of the laser element is completed.

【0026】図3(d) 参照 次いで、n+ 型GaAs基板11a の裏面に厚さ3μm程
度のInからなるn電極19を蒸着手段により形成する。
Next, as shown in FIG. 3D, an n electrode 19 made of In and having a thickness of about 3 μm is formed on the back surface of the n + type GaAs substrate 11a by vapor deposition means.

【0027】図3(e) 参照 次いで、上記積層基板をチップ状にダイシングしてZn
Se系レーザ素子11が形成される。
Next, referring to FIG. 3 (e), the above-mentioned laminated substrate is diced into chips to obtain Zn.
The Se-based laser element 11 is formed.

【0028】図3(f) 参照 一方、ヒートシンク12上のレーザ素子搭載位置に予め厚
さ3μm程度のInはんだ17を形成しておく。
On the other hand, the In solder 17 having a thickness of about 3 μm is previously formed on the heat sink 12 at the position where the laser element is mounted.

【0029】図3(g) 参照 次いで、ヒートシンク12をInの融点(156℃) 以上で且
つ前記MBEによる結晶成長温度(250℃) 以下の温度の
例えば 200℃に加熱し、Inはんだ17が溶融したのを確
認した後、該ヒートシンク12上に、前記完成したZnS
e系レーザ素子11を、その基板接続用電極16がInはん
だ17上に接するように位置合わせして搭載する。
3 (g), the heat sink 12 is heated to a temperature not lower than the melting point of In (156 ° C.) and not higher than the crystal growth temperature by MBE (250 ° C.), for example, 200 ° C., and the In solder 17 is melted. After confirming that the completed ZnS
The e-type laser element 11 is aligned and mounted so that the substrate connecting electrode 16 is in contact with the In solder 17.

【0030】図3(h) 参照 そして、基板接続用電極16のボンディング用In層15が
溶融し、Inはんだ17と一体化した後、冷却して前記レ
ーザ素子11がヒートシンク12上にInはんだ17により接
続された本発明に係るZnSe系半導体レーザが完成す
る。
Referring to FIG. 3 (h), the bonding In layer 15 of the substrate connecting electrode 16 is melted and integrated with the In solder 17, and then cooled to cause the laser element 11 to be placed on the heat sink 12 so that the In solder 17 is formed. The ZnSe based semiconductor laser according to the present invention connected by the above is completed.

【0031】なお、上記接続では溶融したInはんだ17
とボンディング用In層15とが融合一体化して接続がな
されるので、Inはんだ17及びボンディング用In層15
の表面に形成されていた酸化膜は融合に際し表面張力で
周辺に排除され、融合接続部は酸化膜の介在しない良好
な接続構造になる。従って、十分に低い接続抵抗が得ら
れる。
In the above connection, molten In solder 17
Since the bonding In layer 15 and the bonding In layer 15 are integrated and connected to each other, the In solder 17 and the bonding In layer 15 are formed.
The oxide film formed on the surface of the is removed at the periphery due to surface tension during fusion, and the fused connection portion has a good connection structure with no oxide film interposed. Therefore, a sufficiently low connection resistance can be obtained.

【0032】また、レーザ素子11に設けられる基板接続
用電極16の最下層のAu系コンタクト金属層13と最上層
のボンディング用In層15との間にははんだ着け温度に
おいて何れの金属とも融合反応を起こさないバリア用N
i層14が介在せしめられているので、上記はんだ着けに
際しAu系のコンタクト金属がInはんだ17中に溶け込
んで、Inはんだ17を硬化させる(可塑性を失わせる)
ことはない。また、レーザ動作中の発熱による温度上昇
においても同様である。
Further, between the lowermost Au-based contact metal layer 13 of the substrate connecting electrode 16 provided on the laser element 11 and the uppermost bonding In layer 15, a fusion reaction occurs with any metal at the soldering temperature. N for barrier that does not cause
Since the i layer 14 is interposed, the Au-based contact metal dissolves in the In solder 17 at the time of the soldering, and the In solder 17 is hardened (the plasticity is lost).
There is no such thing. The same applies to the temperature rise due to heat generation during laser operation.

【0033】以上実施例においては本発明に係る半導体
素子(レーザ素子)の基板接続用電極の最上層に形成す
るボンディング金属層にIn層を用いたが、このボンデ
ィング金属層はInはんだと融合し易い金属であれば上
記Inに限られるものではなく、Sn等も勿論使用され
る。またバリア金属には、実施例に示したNi以外に、
マンガン(Mn)、クロム(Cr)等の高融点金属が用
いられる。
In the above embodiments, the In layer is used as the bonding metal layer formed on the uppermost layer of the substrate connecting electrode of the semiconductor element (laser element) according to the present invention. This bonding metal layer is fused with In solder. The metal is not limited to In as long as it is an easy metal, and Sn or the like may be used. Further, as the barrier metal, other than Ni shown in the examples,
Refractory metals such as manganese (Mn) and chromium (Cr) are used.

【0034】[0034]

【発明の効果】以上説明したように本発明によれば、例
えばレーザ素子等の半導体素子がヒートシンク等の実装
基板にInはんだを用いて接続される半導体レーザ等の
半導体装置において、上記接続を十分に低い接続抵抗
で、しかもInはんだの柔らかい可塑性を維持した状態
で行うことができる。
As described above, according to the present invention, in a semiconductor device such as a semiconductor laser in which a semiconductor element such as a laser element is connected to a mounting substrate such as a heat sink using In solder, the above-mentioned connection is sufficiently performed. It can be performed with a very low connection resistance and while maintaining the soft plasticity of the In solder.

【0035】そのため、はんだ着けによる昇温時及び素
子動作による昇温時にレーザ素子等の半導体素子と実装
基板との間に熱膨張率の差によって生ずるストレスは前
記Inはんだの柔らかい可塑性によって吸収され、半導
体素子の活性層に歪みを与えることがなくなる。従っ
て、本発明によれば上記活性層の結晶歪みに起因した特
性劣化は防止され、且つ実装基板との電気的接続も十分
に低く形成されるので、ヒートシンク等の実装基板に半
導体レーザ等の半導体素子がInはんだを用いて接続さ
れる半導体レーザ等の半導体装置の信頼性が向上する。
Therefore, the stress caused by the difference in the coefficient of thermal expansion between the semiconductor element such as the laser element and the mounting substrate during the temperature rise due to soldering and the temperature rise due to the element operation is absorbed by the soft plasticity of the In solder, Strain is not applied to the active layer of the semiconductor element. Therefore, according to the present invention, the characteristic deterioration due to the crystal strain of the active layer is prevented, and the electrical connection with the mounting substrate is formed sufficiently low, so that the semiconductor substrate such as the semiconductor laser is mounted on the mounting substrate such as the heat sink. The reliability of a semiconductor device such as a semiconductor laser in which elements are connected using In solder is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の原理説明用斜視図FIG. 1 is a perspective view for explaining the principle of the present invention.

【図2】 本発明の一実施例の斜視模式図FIG. 2 is a schematic perspective view of an embodiment of the present invention.

【図3】 本発明の一実施例に係る製造工程断面図FIG. 3 is a sectional view of a manufacturing process according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 実装基板 3 コンタクト金属層 4 バリア金属層 5 ボンディング金属層 6 基板接続用電極 7 Inはんだ 11 ZnSe系半導体レーザ素子 11a n+ 型GaAs基板 11b n型ZnSSeクラッド層 11c n型ZnSe光ガイド層 11d CdZnSe活性層 11e p型ZnSe光ガイド層 11f p型ZnSSeクラッド層 11g p型ZnSeコンタクト層 12 ヒートシンク 13 Au系コンタクト金属層 14 バリア用Ni層 15 ボンディング用In層 16 基板接続用電極 17 Inはんだ 18 絶縁層 19 n電極1 Semiconductor Element 2 Mounting Substrate 3 Contact Metal Layer 4 Barrier Metal Layer 5 Bonding Metal Layer 6 Substrate Connecting Electrode 7 In Solder 11 ZnSe Semiconductor Laser Element 11a n + Type GaAs Substrate 11b n Type ZnSSe Clad Layer 11c n Type ZnSe Optical Guide Layer 11d CdZnSe active layer 11e p-type ZnSe optical guide layer 11f p-type ZnSSe clad layer 11g p-type ZnSe contact layer 12 heat sink 13 Au-based contact metal layer 14 Ni layer for barrier 15 In layer for bonding 16 substrate connection electrode 17 In solder 18 Insulation layer 19 n-electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 倉又 朗人 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 堀野 和彦 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akito Kuramata 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Kazuhiko Horino 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子(1) をインジウムはんだ(7)
を用いて実装基板(2) 上にはんだ着け接続してなる半導
体装置において、該はんだ着け接続に用いられる該半導
体素子(1) の基板接続用電極(6) が、最下層に該半導体
素子(1) にオーミックに接続するコンタクト金属層(3)
を有し最上層にインジウムはんだ(7)と融合し易い金属
からなるボンディング金属層(5)を有し、且つ該コンタ
クト金属層(3) とボンディング金属層(5) との間に該イ
ンジウムはんだ(7) によるはんだ着け温度において該コ
ンタクト金属及び該ボンディング金属の何れとも融合反
応を起こさないバリア金属層(4) が挿入された構造を有
することを特徴とする半導体装置。
1. An indium solder (7) for a semiconductor element (1)
In a semiconductor device formed by soldering connection on a mounting substrate (2) using, the substrate connecting electrode (6) of the semiconductor element (1) used for the soldering connection has the semiconductor element ( Contact metal layer for ohmic connection to (1) (3)
And a bonding metal layer (5) made of a metal that is easy to fuse with the indium solder (7) and has between the contact metal layer (3) and the bonding metal layer (5). A semiconductor device having a structure in which a barrier metal layer (4) that does not cause a fusion reaction with either the contact metal or the bonding metal at the soldering temperature according to (7) is inserted.
【請求項2】 前記ボンディング金属層がインジウムあ
るいは錫からなることを特徴とする請求項1記載の半導
体装置。
2. The semiconductor device according to claim 1, wherein the bonding metal layer is made of indium or tin.
【請求項3】 前記バリア層がニッケルまたはマンガン
からなることを特徴とする請求項1記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the barrier layer is made of nickel or manganese.
【請求項4】 前記コンタクト金属層が金を含む導電材
料からなることを特徴とする請求項1記載の半導体装
置。
4. The semiconductor device according to claim 1, wherein the contact metal layer is made of a conductive material containing gold.
【請求項5】 前記半導体素子がII−VI族化合物半導体
レーザ素子からなることを特徴とする請求項1記載の半
導体装置。
5. The semiconductor device according to claim 1, wherein the semiconductor element is a II-VI group compound semiconductor laser element.
JP11498994A 1994-05-27 1994-05-27 Semiconductor device Withdrawn JPH07321412A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11498994A JPH07321412A (en) 1994-05-27 1994-05-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11498994A JPH07321412A (en) 1994-05-27 1994-05-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH07321412A true JPH07321412A (en) 1995-12-08

Family

ID=14651580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11498994A Withdrawn JPH07321412A (en) 1994-05-27 1994-05-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH07321412A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002118294A (en) * 2000-04-24 2002-04-19 Nichia Chem Ind Ltd Flip chip type light-emitting diode and manufacturing method thereof
GB2380061A (en) * 2001-05-16 2003-03-26 Hitachi Ltd Semiconductor laser array
JP2006173371A (en) * 2004-12-16 2006-06-29 Mitsubishi Electric Corp Semiconductor device
JP2007053242A (en) * 2005-08-18 2007-03-01 Fuji Xerox Co Ltd Semiconductor laser device and manufacturing method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002118294A (en) * 2000-04-24 2002-04-19 Nichia Chem Ind Ltd Flip chip type light-emitting diode and manufacturing method thereof
GB2380061A (en) * 2001-05-16 2003-03-26 Hitachi Ltd Semiconductor laser array
GB2380061B (en) * 2001-05-16 2005-06-01 Hitachi Ltd Semiconductor laser array
JP2006173371A (en) * 2004-12-16 2006-06-29 Mitsubishi Electric Corp Semiconductor device
JP2007053242A (en) * 2005-08-18 2007-03-01 Fuji Xerox Co Ltd Semiconductor laser device and manufacturing method thereof

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