JPH07321342A - Junction field-effect transistor - Google Patents

Abstract

PURPOSE:To make it possible to arrange source wires with influence of wiring resistance suppressed and a smaller number of pads. CONSTITUTION:A plurality of linear high-concentration source regions 2 of a first conductivity type and a plurality of linear high-concentration gate regions 3 of a second conductivity type, are alternately placed on the entire surface of a medium-concentration semiconductor of the first conductivity type. A high- concentration drain region of the first conductivity type is placed on the entire reverse side of the semiconductor to form a vertical junction field-effect transistor. In this transistor, length of each of the source regions 2 is set to sq. rt. (rhoc/Rs)= Le or below, where Rs is sheet resistance of the wiring material led from the source regions 2, and rhoc is ON-time resistance/unit area of source contact.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical junction field effect transistor.

[0002]

2. Description of the Related Art A field effect transistor (FET) has been conventionally known as one of high speed switching devices. This FET is a junction type FET (JF
ET) and MOS type (MOS-FET). Compared with MOS-FET, J-FET generally has a lower on-resistance (R _on ), less change in on-resistance with respect to input level, etc. Easy to handle without problems of dielectric breakdown, high switching speed, etc. There are advantages.

Here, the conventional J-FET is constructed as a planar type in which a gate, a source and a drain are arranged on the same surface. In such a planar type, since the gate region is formed by impurity diffusion, it is difficult to reduce the size, and the on-state resistance is generally as high as several 100Ω. On the other hand, in order to reduce the on-state resistance, a vertical J-FET has been considered in which a current is made to flow in the substrate thickness direction and sources are two-dimensionally arranged to increase the effective source length. For example, BJBaliga, “A PowerJuncti
on Gate Field-Effect Transisitor Structure with Hi
gh Blocking Gain ”, IEEE Trans.Electron Dev.ED27, pp
In the FET shown in the document 368-373,1980, since a high drain voltage (400 V or more) is switched, a thick epitaxial substrate with a low impurity concentration is used, and the on-state resistance is about 20 Ω with 60 sources. ing.

[0004]

By the way, in recent years, battery-powered portable electronic devices such as notebook type personal computers and mobile phones have been remarkably spread. It is desirable that these portable electronic devices have low power consumption, and low power consumption is achieved by lowering the power supply voltage of the electronic device used and reducing the _on- resistance R _on of the device. There is.

In the vertical type J-FET described above, it is easy to shorten the distance between the source and the drain. When the power supply voltage is low, a thin epitaxial substrate with a high impurity concentration can be used. Since it is easy to effectively increase the source length by arranging the gates alternately or two-dimensionally in a cell shape, it is possible to reduce the on-time resistance R _on .

However, the longer the effective source length, the lower the _on- resistance R _on of the device can be made, but the input capacitance due to the gate becomes large in proportion to this source length. The source length is limited in terms of device loss.

In this respect, the simplest method of laying out the effective source length in a two-dimensional manner is to divide the effective source length into unit source lengths of an appropriate length, and use these unit source lengths. It can be realized by arranging a plurality of sources in parallel and electrically connecting them by a source wiring material. As an example of this, FIG. 6 shows a simplified layout of the wiring between the gate G and the source S on the device surface.

However, in the device designed to have a small on-state resistance R _on due to the higher concentration and thinner layer of the epitaxial substrate, the source wiring resistance from the source region to the pad, which has not been a problem in the past, cannot be ignored. If the unit source length is too long, the wiring resistance will increase, and it will be impossible to expect a reduction in resistance corresponding to the source length.

[0009]

A linear source region having a high concentration of the first conductivity type and a high-concentration second conductivity type are formed on a semiconductor surface having a medium concentration of the first conductivity type. In the vertical junction field effect transistor, a plurality of linear gate regions are alternately arranged, and a high-concentration drain region of the first conductivity type is arranged on the entire back surface of the semiconductor. Where R _{S is} the sheet resistance of the wiring material and ρ _C is the on-resistance per unit area of the source contact, the length of each of the source regions to be arranged is √ (ρ _C / R _S ) Set as below.

[0010]

With regard to the layout of the source wiring of the vertical junction field effect transistor, in order to realize the source length required to satisfy the electrical characteristics, the length per source region to be arranged is set as follows. Since the wiring resistance per unit length and the device conductance are set to appropriate values, it is possible to suppress the influence of the wiring resistance and perform layout with a small number of pads.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. First, referring to FIG. 2 which schematically shows the cross-sectional structure and resistance component of a unit vertical J-FET,
The outline of T will be described including the above-mentioned problems. Here, an n-channel J-FET will be described as an example, where the first conductivity type is n-type and the second conductivity type is p-type. On the surface of the n-type Si epitaxial layer (medium-concentration n-type semiconductor) 1, a source region 2 formed of a high-concentration n-type Si region and a gate region 3 formed of a high-concentration p-type Si region are linearly formed. Has been formed. On the back surface side of the n-type Si epitaxial layer 1, a high-concentration n-type Si substrate is entirely arranged as a drain region 4. In FIG. 2, wiring from the source terminal and the drain terminal is omitted in order to avoid complication of the drawing.

According to this, the on-time resistance R _on is _equal to JF
ET resistance R _j , spreading resistance R _{epi of} n-type Si epitaxial layer 1, substrate resistance R _sub, and source contact resistance R _c1
It can be seen that it is the sum of the drain contact resistance R _c2 and the drain contact resistance R _c2 . Generally, in such a vertical J-FET, a method of reducing the on-time resistance R _on by reducing the unit device is adopted. However, as mentioned above, reducing the size of the unit device also reduces the area of the source contact,
The source contact resistance R _c1 increases. Since the source contact resistance R _c1 thus increased contributes to the increase of the overall on-time resistance R _on , it can be understood that the effect of reducing the on-time resistance R _on by device miniaturization is insufficient.

By the way, the effective source length is selected so that the power loss of the FET is minimized. Here, the power loss in the switching FET is the sum of conduction loss and switching loss. The drain current is I _d , the input capacitance is C _i , the gate voltage is V _g , the switching frequency is f, and the duty is D. Then, the power loss P _loss is represented by P _loss = I _d ² × R _on × D + C _i × V _g ² × f (1). Furthermore, R _on = R _L / L, C _i = C _L ×
L, L; If it is an effective source length, P _loss = I _d ² × ( _RL / L) × D + _CL × L × V _g ² × f (2)

As a result, for example, the source contact width 1
μm, R _L = 3.1 × 10 ⁴ Ω · μm, C _L = 3.4
× 10 to ¹⁵ F / μm, I _d = 8 A, V _g = 7 V, D = 5
When 0% and f = 3 MHz, the device loss curve with respect to the source length is as shown in FIG. 3, and the effective source length L giving the minimum loss can be estimated to be 1.4 × 10 ⁶ μm.

In order to two-dimensionally lay out such an effective source length, a linear source and gate repeating pattern is formed (see FIG. 6) and electrically connected in parallel by a wiring material such as aluminum. Easy to implement.

However, as described above, if the unit source length is increased to reduce the number of source and gate pads, the contact resistance due to the resistance of the source wiring material increases, and conversely, the unit source. If the length is too short, the number of pads will increase and the mounting will be complicated.

A more detailed description will be given with reference to FIG. 4, which schematically shows the device configuration for one source. When an electrode is taken out from one end of the source pad to the source region 2 by a metal wiring 5 such as aluminum, the electric circuit thereof is considered to be a distributed constant circuit as shown in FIG. Therefore, in such a device, the on-time resistance R _on needs to be examined with a distributed constant circuit including the resistance R of the metal wiring 5 and the conductance G in the semiconductor (n-type Si epitaxial layer 1).

Now, the sheet resistance of the source electrode is R _S , each resistance R _j in the semiconductor (n-type Si epitaxial layer 1),
_Assuming that the resistance per unit source contact area considering R _epi and R _sub is ρ _C , the source-drain resistance R is given by the equation (3) from the transmission line model. In addition,
In the formula (3), Le = √ (ρ _C / R _S ).

[0019]

[Equation 1]

For example, the source electrode has a resistivity of 2.8 × 10.
Made of aluminum of ⁶ Ω · cm, width 2μm, thickness 0.6μ
m, the source contact width W = 1 μm, and the resistance inside the semiconductor (n-type Si epitaxial layer 1) is the resistance per unit source contact area ρ _C = 3.0 Ω · cm ²
When the dependence of the on-time resistance R _on in one case on the source length is obtained, it is as shown in FIG. In FIG. 4, the calculation results when the source wiring resistance is not taken into consideration are also plotted. According to the characteristics shown in FIG. 5, the on-state resistance R _on is inversely proportional to the effective source length L when the wiring resistance is not taken into consideration.
When the wiring resistance is taken into consideration, it can be seen that the decrease of the on-time resistance R _on is saturated and becomes a substantially constant value when the source length is Le or more.

Therefore, in order to increase the effective source length L and decrease the _on- resistance R _on , it is necessary to lay out a plurality of parallel unit source lengths with an appropriate length. As an appropriate unit source length, Le = √
It is also understood that the effect of the source wiring resistance can be suppressed if it is (ρ _C / R _S ) or less.

Therefore, in the vertical J-FET of this embodiment,
The unit source length is calculated from the sheet resistance R _S of the source wiring and the resistance ρ _C per unit source contact area in the semiconductor.
With the value Le obtained as Le = √ (ρ _C / R _S ), as an upper limit, the layout is performed so that the length is less than or equal to this Le. This makes it possible to provide a device having a low on-state resistance R _on while suppressing the influence of wiring resistance as much as possible.

With respect to such a structure, the effect will be clarified based on a concrete example. Here, a vertical J-FET was prototyped on an n-type Si epitaxial substrate with a repeating pitch of 7 μm. Here, n in the n-type Si epitaxial substrate
The thickness of the type Si epitaxial layer 1 is 5 μm, the concentration N _d is 5 × 10 ¹⁵ / cm ³ , and the drain region 4 forming the substrate has such a concentration and thickness that the substrate resistance R _sub is sufficiently small. The p-type gate region 3 has a diffusion depth of about 2 μm, and the distance between the gate regions 3 is about 1.9 μm. Also,
The material of the metal wiring 5 with respect to the source region 2 is aluminum, the width is 2 μm, the thickness is 0.6 μm, and the contact width W with the source region 2 is 1 μm. Further, the source region 2 is doped with As ions at 30 k by the ion implantation method.
It is injected with eV at a dose of 2 × 10 ¹⁵ / cm ² so that the contact resistance between the aluminum of the metal wiring 5 and the surface of the semiconductor (n-type Si epitaxial layer 1) is reduced.

At this time, the unit source length was set as follows. The resistance inside the semiconductor (n-type Si epitaxial layer 1) when the gate structure as described above is ρ _C = 3.54 Ω · cm ² per unit area at the source contact.
Is expected to be. Also, the usage conditions are the drive frequency f
= 3 MHz, switching drain current I _d = 8
A, gate voltage V _g = 7 V, and duty D = 50%. In this case, the source length that minimizes the loss is calculated to be about 1.4 × 10 ⁶ μm. Next, the optimum unit source length for realizing this source length with a plurality of sources was determined to be the method of the present embodiment as described above, that is, Le or less. In this case, Le is 1232 μm, so in this specific example, the unit source length is 800 μm.
Set to. Therefore, the number of sources is 1760 and 1
The layout configuration is such that four blocks are prepared with 440 blocks per block. FIG. 1 schematically shows the layout of such source and gate wirings. The designed value of the on-time resistance R _on of the device designed in this way is 34
It is as small as mΩ. Furthermore, as a result of measuring the characteristics of the device prototyped on the basis of such design values, the actual measured value of the on-time resistance R _on was as small as 40 mΩ. It should be noted that this actually measured value is measured by applying a needle to the source pad, and is not in the mounted state. In summary, the on-time resistance R _on is as shown in Table 1.

[0025]

[Table 1]

The results shown in Table 1 show that the design value in consideration of the wiring resistance and the measured value are substantially equal to each other, and there is an increase in the on-time resistance R _on due to the wiring resistance. It is clear that the longer the source length is, the greater the influence of the wiring resistance becomes.

In this embodiment, the n-channel J-FE is used.
Although T has been described as an example, it goes without saying that the same can be applied to the case of a p-channel J-FET.

Incidentally, in the case of a J-FET in which source pads can be formed at both ends, the unit source length is L
Obviously, it can be doubled.

[0029]

According to the junction field effect transistor of the present invention, the semiconductor surface of the first conductivity type of medium concentration has
A plurality of high-concentration linear source regions of the first conductivity type and a plurality of high-concentration linear gate regions of the second conductivity type are alternately arranged, and the high-concentration linear source regions are formed on the entire back surface of the semiconductor. In the vertical junction field effect transistor in which the drain region of the first conductivity type is arranged, the sheet resistance of the wiring material from the source region is R _S , and the on-state resistance of the source contact per unit area is ρ. _{When C} is set, the length of each of the plurality of source regions to be arranged is set to √ (ρ _C / R _S ) or less. Can be laid out in numbers.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a layout of gate and source wirings according to an embodiment of the present invention.

FIG. 2 is a cross-sectional structure diagram showing a breakdown of on-state resistance of a vertical J-FET.

FIG. 3 is a characteristic diagram showing the relationship between the effective source length and device loss.

FIG. 4 is a perspective view for explaining a distributed constant circuit for one source.

FIG. 5 is a characteristic diagram showing unit source length dependence of on-time resistance R _on per source.

FIG. 6 is a schematic view showing a layout of a conventional gate and source wiring.

[Explanation of reference numerals] 1 semiconductor 2 source region 3 gate region 4 drain region

Claims (1)

[Claims] 1. A linear source region having a high concentration of the first conductivity type and a linear gate having a high concentration of the second conductivity type on a semiconductor surface of the medium concentration first conductivity type. In a vertical junction field effect transistor in which a plurality of regions are alternately arranged and a high-concentration drain region of the first conductivity type is arranged on the entire back surface of the semiconductor, a wiring material from the source region is used. Where R _{S is} the sheet resistance and ρ _C is the on-resistance per unit area of the source contact, the length per source region to be arranged is set to √ (ρ _C / R _S ) or less. A junction type field effect transistor characterized in that.