JPH07319804A - Scsi bus monitoring device and bus monitoring system - Google Patents

Abstract

PURPOSE:To execute the monitoring/tracing operation of an SCSI signal on a bus over a long period without lacking it. CONSTITUTION:This SCSI bus monitoring device 31 is provided with an event detecting circuit 8a for detecting an event to be recorded based upon the transition of an SCSI signal received by a bus receiving part and a trace memory 10 for successively storing the state of the SCSI signal as trace data at the time of detecting an event and constituted so as to output an alarm when the storage capacity of the memory 10 exceeds a set point, detect transition to a bus free state before time when all information processors connected to the bus regard the bus as the bus-free state and output a busy signal to the bus at the time of detecting the bus-free state in the output state of the alarm. During the output period of the busy signal, trace data 23 stored in the memory 10 are transfered to the external.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to communication contents such as control signals and data signals flowing on a computer bus, for example.
The present invention relates to a SCSI bus monitor device for monitoring in accordance with the CSI standard and a bus monitor system incorporating the SCSI bus monitor device.

[0002]

2. Description of the Related Art A large number of input / output ports are provided on an external bus connected to a computer incorporating elements such as a CPU (central processing unit), ROM, and RAM for executing various types of information processing.
Various control signals for controlling external storage devices such as FDD and HDD, and peripheral devices such as printers flow.

In a bus interface for exchanging such various control signals between peripheral devices or between a computer and a peripheral device, the combination of control signals is technically significant. Multiple phases
e) SCSI (Small Computer S)
ystem Interface) standard has been standardized and generally widely used.

In this way, each control signal on the bus is sent to the SC.
If expressed in the phase based on the SI standard, communication information on a complicated bus can be easily understood. Development of peripheral devices adopting this SCSI standard bus interface
When performing maintenance, etc., in order to improve work efficiency,
A SCSI bus monitor device is used which monitors (monitors) whether or not each signal line of the bus transits in a state satisfying the SCSI standard and stores and retains it.

FIG. 8 is a schematic configuration diagram of a general SCSI bus monitor device. In FIG. 8, the SCSI to be measured
In addition to a personal computer, a plurality of information processing devices 2 including external storage devices such as the above-mentioned FD and HDD and peripheral devices such as printers are connected to the bus 1 through which a standard SCSI signal flows. An adapter 3 is connected to this bus 1. The adapter 3 connects the bus 1 to the SCSI bus monitor 5 via the cable 4.
Branch to.

The bus receiving unit 6 in the SCSI bus monitor 5 sends the input SCSI signal 7 to the event detection circuit 8 and the bus signal latch 9. The event detection circuit 8 is
From the state of the SCSI signal 7 and signal transition, for example, S
An event to be recorded and held in the trace memory 10 such as a change point of the CSI phase is detected. Then, the event detection circuit 8 sends an event detection signal 11 to the next monitor sequencer 12 and the bus signal latch 9 at the time when the event is detected.

The bus signal latch 9 has an event detection signal 11
Latch the SCSI signal 7 at the moment when
It is sent to the next trace memory 10 as I signal data 13.

The time stamp generating circuit 14 also applies time stamp data 15 indicating the current time to the trace memory 10. Further, the memory address 17 from the memory address generating circuit 16 is applied to the trace memory 10. The memory address generation circuit 16 updates the memory address 17 output in response to the address change signal 18 from the monitor sequencer 12. Further, the memory address generation circuit 16 sends an overflow signal 19 to the monitor sequencer 12 when the write address of the trace memory 10 reaches the final position.
Is sent.

When the monitor sequencer 12 receives the event detection signal 11, it checks the overflow signal 19 and sends the memory write signal 20 to the trace memory 10 if the trace memory 10 is not yet full. Output. As a result, the trace data 23 including the SCSI signal data 13 and the time stamp data 15 is written in the designated memory address 17 in the trace memory 10. When the process of writing the trace data 23 to the trace memory 10 is completed, the monitor sequencer 12 sends out the address change signal 18 and advances the memory address 17 by one.

As described above, every time an event occurs, the trace memory 23 sequentially stores the trace data 23 including the SCSI signal data 13 and the time stamp data 15 in time series. .

The monitor sequencer 12, which has detected the overflow signal 19 when the trace memory 10 is full,
The trace operation for the SCSI bus 1 is interrupted, and the transfer processing of the trace data 23 to the host collection device 21 is started.

That is, the monitor sequencer 12 is
The trace operation is interrupted, and the address change signal 18 resets the memory address 17 to the start address in the trace memory 10 at the start point of the trace. The monitor sequencer 12 then sends the memory read signal 2 to the trace memory 10.
2 is transmitted, and the trace recorded in the trace memory 10
The data 23 is read to the host bus interface circuit 24.

Thereafter, the monitor sequencer 12 outputs the transfer request signal 25 to the host bus interface circuit 24, and the trace data 23 is used as the host transfer data 26 for the external host collecting device 21. Transfer to.

The host collection device 21, which has received the trace data 23, analyzes the trace data 23 and analyzes the trace data SCS.
It has a function of displaying how the I signal 7 is operating on the display screen of the CRT display device or recording and holding it in an external recording device such as an HDD or FD connected to itself.

When the monitor sequencer 12 completes the transfer processing of all the trace data 23 recorded in the trace memory 10 to the host collection device 21, the memory sequence 1
7 is reset again and the trace operation is restarted.

[0016]

However, the above-mentioned SCSI bus monitor device 5 still has the following problems to be solved. That is, the storage capacity of the race memory 10 provided in the SCSI bus monitor device 5 naturally has a certain limit. In this type of monitor device, the trace memory 2 has a storage capacity of 32 to 64 K (km) data due to the manufacturing cost and the like.
3 is memorable.

However, in recent years, there has been a demand for monitoring the SCSI signal 7 transmitted on the bus 1 for a long time. In order to monitor the SCSI signal 7 for a long period of time, the number of trace data to be stored and stored may increase significantly, for example, 1 M (mega) data or more.

When the trace data 23 having such a large capacity is collected by using the conventional SCSI bus monitor device 5, the trace memory 10 becomes full during the trace operation, which is inevitable. Therefore, it is necessary to temporarily suspend the trace operation, transfer the trace data 23 accumulated in the trace memory 10 to the external host collection device 21, and then restart the trace operation.

If such a method is adopted, a memory or HD (hard disk) built in the host collection device 21
It is possible to store the trace data 23 up to the storage capacity of the MT, MT (magnetic tape), etc. However, in the conventional SCSI bus monitor device 5 shown in FIG. The data 23 and the host collection device 21
During the transfer to the bus, the trace signal cannot be monitored for the transition of the SCSI signal 7 transmitted on the bus 1 to be measured, and all the transition information of the SCSI signal 7 during that period is lost. Will end up. That is, in the conventional SCSI bus monitor device 5, since the monitor trace of the SCSI bus is an intermittent trace, the important trace data 23 is lost even if the measurement is performed for a long time. There is a problem that cannot be denied.

In order to eliminate such inconvenience, the trace data 23 collected during the trace operation may be transferred to the host collection device 21 at the same time (real time).
There are the following problems in actualizing such a system.

That is, in order to realize such a system, an expensive special memory such as a read-write FIFO memory or dual port memory must be adopted as the trace memory 10. further,
It is necessary to set the transfer speed for transferring the collected trace data 23 to the host collection device 21 to be higher than the operating speed of the SCSI bus to be measured, including the addition of the time stamp data 15.

In order to realize such a transmission interface on the side of the host collection device 21, a transmission speed characteristic far exceeding the SCSI standard (the maximum transfer rate in the present standard is 10 M transfer / sec) is provided. It is necessary to build an interface that has However, development of such a special interface requires enormous amount of time and labor, and even if it can be realized, high-speed components must be adopted in the transmission interface circuit on the host side. As a matter of course, since the manufacturing cost of the SCSI bus monitor device 5 is significantly increased, it is very difficult to adopt this method as a practical problem.

The present invention has been made in view of the above circumstances, and when the storage amount of the trace memory exceeds a set value, the busy signal is forcibly transmitted to the bus to be accumulated in the trace memory. The loss of the transition information of the SCSI signal during the period when the trace data is transferred is prevented, and the monitor trace operation of the SCSI signal is lost for a long time at low cost without using special parts. It is an object of the present invention to provide a SCSI bus monitor device that can be implemented without a need and a bus monitor system incorporating the SCSI bus monitor device.

[0024]

SUMMARY OF THE INVENTION In order to solve the above problems, a SCSI bus monitor device of the present invention includes a bus receiving unit for receiving a SCSI signal transmitted on a bus connecting information processing devices, and a bus receiving unit. The event detection means for detecting an event to be recorded from the transition of the SCSI signal captured by the unit, and the SC when the event detection means detects the event.
A trace memory that sequentially stores the state of the SI signal as trace data, a memory monitoring unit that outputs an alarm when the storage amount of the trace memory exceeds a set value, and all the information processing devices connected to the bus are connected to the bus. The bus-free state detection means that detects the transition to the bus-free state and the memory monitoring means output an alarm before the time considered as the bus-free state, and the bus-free state detection means detects the bus-free state. At this time, a busy signal output means for outputting a busy signal to the bus, a trace data transfer means for transferring the trace data stored in the trace memory to the outside after outputting the busy signal, and a trace data transfer means for transferring the trace data In response to the end of transfer,
And a busy signal canceling means for canceling the busy signal.

According to another aspect of the present invention, the memory monitoring means described above includes a set value input means for setting a set value from the outside and converting the set value into a corresponding set address, and a set value input means. The address comparison means compares the converted setting address with the write address for writing the trace data in the trace memory, and outputs an alarm when the write address exceeds the set address.

Further, in another invention, the bus-free state detection time in the above-mentioned bus-free state detecting means is detected when all the information processing devices connected to the bus release the busy signal to the bus. And the busy signal output time in the busy signal output means described above is after the bus-free state detection time and the time when the busy signal to be output reaches all the information processing devices. Is set before the time when the bus is considered to be free.

Further, the bus monitor system of the present invention includes a SCSI bus monitor device having the above-mentioned configuration and the S bus monitor device.
It is configured with a host collection device that processes the trace data transferred from the CSI bus monitor device to the outside.

Further, the host collection device in this bus monitor system specifies a buffer memory for temporarily storing the trace data sequentially output from the SCSI bus monitor device, and the trace data stored in the buffer memory from the outside. The trace data extracting means for extracting the trace data corresponding to the occurred event and the external recording device for storing and holding the trace data extracted by the trace data extracting means are provided.

[0029]

In the SCSI bus monitor thus constructed, the memory monitoring means outputs an alarm when the storage amount of the trace memory in which the trace data is sequentially stored exceeds the set value.

Further, the bus-free state detecting means monitors the signal state of the busy signal output from each information processing device on the bus, and all the information processing devices connected to this bus connect the bus to the bus. The transition to the bus free state is detected before the time considered as the free state.

When the bus-free state is first detected after the alarm is output, the busy signal is forcibly output to the bus. That is, the SCS immediately before the bus enters the bus free state defined by the SCSI standard.
By sending a busy signal from the I-bus monitor to the bus, each information processing device connected to this bus determines that the busy signal is a busy signal output by another information processing device, and outputs a SCSI signal to the bus. It does not output and waits for the release of this busy signal.

The timing at which the busy signal is sent from the SCSI bus monitor device to the bus is immediately before the bus shifts to the bus free state.
It does not interfere with the CSI signal.

Then, in the SCSI bus monitor device, a busy signal is sent out on the bus, and the SCSI signal is sent on the bus.
The trace data accumulated in the trace memory is transferred to the external host collection device during the period when the signal is not transmitted. When the transfer process is completed, the busy signal is released. When the busy signal is released, the SCSI signal is output again from each information processing device on the bus.
The bus monitor restarts event detection and accumulation of trace data in the trace memory.

As described above, by outputting the busy signal to the bus during the transfer of the trace data to the outside so that the SCSI signal is not output on the bus,
It is possible to prevent the monitor trace of the SCSI signal from being lost.

Further, in another invention, a set value serving as a criterion for outputting an alarm can be arbitrarily set from the outside. Further, since the alarm is output when the write address to the trace memory exceeds the set address corresponding to the set value, the memory monitoring can be easily realized.

Further, in another invention, the busy signal output time to the bus is such that after all the information processing apparatuses release the busy signal to the bus, all the information processing apparatuses output the busy signal via the bus. Receivable time, that is, until the bus free state defined by the SCSI standard is considered. During this time, there are no SCSI signals on the bus.

Further, in the bus monitor system of the present invention, the trace data sequentially output from the SCSI bus monitor device to the outside is selected by the host collecting device, and only the trace data corresponding to the event designated from the outside is selected. It is recorded and held in the recording device. That is, the operator can select and record only the necessary trace data in this host collection device.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of the bus monitor system of the embodiment. The bus monitor system of this embodiment is composed of a SCSI bus monitor device 31 and a host collection device 32, as shown in the figure. The same parts as those of the conventional SCSI bus monitor device 5 shown in FIG. 8 are designated by the same reference numerals. Therefore, detailed description of the overlapping portions will be omitted.

In the SCSI bus monitor device 31 in the system of this embodiment, a memory monitor circuit 33 and a busy signal generation circuit 34 are added to the conventional SCSI bus monitor device 5 shown in FIG.

That is, the memory monitoring circuit 33 refers to the memory address 17 sent from the address generation circuit 16 to the trace memory 10 to constantly determine the amount of the trace data 23 cumulatively recorded in the trace memory 10. When the memory amount of the trace data 23 is monitored and exceeds a preset amount, an alarm signal 35 as an alarm is sent to the busy signal generating circuit 34.

FIG. 2 is a block diagram showing a detailed structure of the memory monitoring circuit 33. As shown in the figure, the memory monitoring circuit 33 takes in the alarm set value 37 input from the external controller 36 and outputs the set address.
It is composed of 9 and 9.

In the memory monitoring circuit 33 having such a configuration, among the memory addresses 17 output from the memory address generation circuit 16, the most significant 2 bits ADR15 and ADR14 are not only the trace memory 10 but also the comparison circuit 39.
Is input at one end of. It is assumed that a 16-bit space is allocated as the memory address 17 in the apparatus of the embodiment.

On the other hand, for example, an external controller 36 such as a CPU provided inside the SCSI bus monitor device 31.
From the desired alarm set value 37 set by the user.
Is input to the alarm setting register 38. From the alarm setting register 38, signals SET15 and SET14 for instructing when the amount of storage in the trace memory 10 becomes greater than or equal to the time when the alarm signal 35 is generated are output, and the other end of the comparison circuit 39. Is input to.

The truth table shown in FIG. 3 is stored in the comparison circuit 39, and the comparison circuit 39 uses the ADR15-A.
When the address value indicated by DR14 becomes equal to or larger than the set value indicated by SET15-14, the alarm signal 35 is output.

In the embodiment, the memory monitoring circuit 33 has a circuit configuration in which only the most significant 2 bits of the memory address 17 are compared with each other. It goes without saying that it is possible to configure a circuit that generates the alarm signal 35 under the condition of (set value).

Next, the operation of the event detection circuit 8a will be described. The event detection circuit 8a receives the SCSI signal 7 as in the conventional event detection circuit 8 shown in FIG.
In addition to the function of detecting the event to be recorded from the transition of the CSI signal 7 and outputting the event detection signal 11, the S
It has a function of detecting the instant when the CSI bus 1 transits to the bus-free state (phase) and outputting the bus-free detection signal 40 to the monitor sequencer 12a and the busy signal generating circuit 34.

The bus-free state is SCSI here.
As defined in the standard, this means a state in which all the information devices 2 connected on the SCSI bus 1 are not using the bus 1.

The busy signal generating circuit 34 outputs the bus free detection signal 4 while the alarm signal 35 is being output.
When 0 is input, the busy signal 41 is output to the bus 1 via the adapter 3 (active side according to the SCSI standard). Further, the busy signal generation circuit 34 receives the busy stop signal 42 from the monitor sequencer 12a,
Release the busy signal 41 that was output to bus 1 (SCSI
Inactive side by standard).

The bus free detection signal 40 of the event detection circuit 8a and the busy signal 4 of the busy signal generation circuit 34
The timing of occurrence of 1 will be described in detail using the detailed time chart based on the worst mounting case of FIG.

The worst mounting case shown in FIG. 4 is that the maximum length cable (bus 1) allowed by the SCSI standard is provided between the devices A and B of the bus 1 to be measured. This is a case where the SCSI bus monitor device 31 is connected, and at this time, the propagation delay time (propagation delay time) TD from the devices A and B to the SCSI bus monitor device 31 becomes maximum.

In FIG. 4, the propagation delay time TD due to the cable is
Is set to 1 m = 5.4 nsec (maximum allowable value in the SCSI-3 standard), and the longest cable within the SCSI standard is 25 m (S in the differential mode).
The maximum allowable value in the CSI-3 standard), so the propagation delay time TD from the devices A and B to the SCSI bus monitor device 31
Is 135 nsec.

According to the SCSI standard, SE indicating that a partner device to exchange information with a busy signal may be selected
Bus in which both the L (selection enable) signal and the inactive signal are set to 400 nsec
It is specified that the bus-free state will occur when the Settle Delay Time is exceeded.

For example, in FIG. 5, since the propagation delay time TD between the devices A and B is 0 nsec, the device B is stopped when 400 nsec has passed since the device A stopped the busy signal.
Detects a bus-free condition.

In the apparatus of the embodiment, before all the information processing apparatuses 2 connected to the bus 1 detect the bus free state, that is, from the moment when the apparatus A releases the busy signal (inactive) in FIG. Within 400 nsec, the busy signal 41 is forcibly output (active side) at the timing of reaching all the information processing devices 2 on the bus 1.

In the case of FIG. 4, the SCSI bus monitor device 3
1 detects the release of the busy signal after the device A stops the busy signal after the propagation delay time TD of 135 nsec elapses, and therefore 100 nse from the time when the bus free is detected.
After c, the busy signal 41 is forcibly output to the bus 1. Then, the busy signal 41 from the SCSI bus monitor device 31 reaches the devices A and B on the bus 1 370 nsec after the device A releases the busy signal, and the device B is in the bus free state. It becomes possible to set the bus 1 to the busy state again 30 nsec before the timing of detecting the signal.

Therefore, even if the information processing apparatus 2 which has been using the bus 1 releases the bus 1 and releases the bus 1 by releasing both the busy signal and the SEL signal, the above-mentioned Bus Settle Delay starts from that point. Time (= 400nsec)
Since the bus 1 is in the busy state again before the time elapses, the timing specification of the bus free state in the SCSI standard cannot be satisfied, and all the information processing devices 2 on the SCSI bus cannot detect the bus free state.

In this way, the SCSI bus monitor device 31
While the busy signal 41 is being output to the bus 1 at the above timing, the bus 1 is frozen, and all the information processing devices 2 connected to this bus 1 are in the next bus free state, that is, SCSI. The access operation to the bus 1 is forcibly interrupted until the bus monitor device 31 releases the busy signal 41.

The operation of the SCSI bus monitor device 31 configured as described above will be described with reference to the flow chart shown in FIG. 5 and the time chart shown in FIG. The flowchart of FIG. 5 and FIG.
In the time chart of, for example, the host collection device 32
When a monitor trace operation start command is received from time t ₁ from time t _{1, the} bus reception unit 6 is received at P (program step) 1.
Also, the event detection circuit 8a is activated to start the trace work. During the trace operation period, the trace data 23 consisting of the SCSI signal data 13 and the time stamp data 15 at that time is traced in response to the occurrence of the event detected by the event detection circuit 8a. -The amount of trace data is increased by sequentially recording in the trace memory 10 and updating the memory address 17 of the trace memory 10 one by one.

At time t ₂ , when the trace data amount exceeds the set value, the memory monitoring circuit 33 sends an alarm signal 35 to the busy signal generating circuit 34 (P2).
Busy signal generation circuit 34 that has received the alarm signal 35
Is a bus-free detection signal 4 from the monitor sequencer 12a.
Wait for 2 input.

Upon receiving the bus-free detection signal 42 at time t _3, the busy signal generation circuit 34 receives the predetermined delay time 10
At time t ₄ after 0 nsecn (P4), the S
The busy signal 41 is forcibly output to the CSI bus (P5).

When the SCSI bus monitor device 31 outputs the busy signal 41 on the bus 1, all the information processing devices 2 connected to the bus 1 cannot use the bus 1, so that the bus 1 is frozen. Then, the monitor sequencer 12a
At time t ₅ , the transfer request signal 23 is sent to the host bus interface circuit 24 to start the transfer processing of the race data 23 accumulated in the trace memory 10 to the host collecting device 32 (P6).

Then, at time t _{6, the} trace memory 10
When the trace data 23 therein falls below the set value, the alarm signal 35 is released. Moreover, Tre at time t ₇ - All Torre Sumemori 10 - scan de - the transfer processing of data 23 is completed (P7), busy stop signal 42 is outputted from the monitor sequencer 12a, at time t _8, Bus 1
The busy signal 41 output upward is released (P
8).

If the specified trace operation is not completed (P9), the trace operation is restarted and the process returns to P2 to wait for the alarm signal 35 again. If the trace operation is finished, all the operations are stopped at that point.

In the SCSI bus monitor device 31 thus constructed, the SCSI signals transmitted between the information processing devices 2 connected to the bus 1 can be monitored without omission, and the event to be recorded can be traced with certainty. It can be stored in memory.

Next, the configuration and operation of the host collection device 32 will be described. FIG. 7 is a block diagram showing a schematic configuration of the host collection device 32. The host transfer data 26 input from the SCSI bus monitor device 31 is temporarily stored in the buffer memory 43. On the other hand, a save selection item table 49 is created based on the user key input 48 input from the user using the keyboard 47. This save selection item table 49 is actually a trace of any kind among various kinds of trace data 23 composed of the time stamp data 15 and the SCSI signal data 13 recorded in the trace memory 10. It is a table that specifies whether the data 23 is recorded and held in an external recording device 46 such as a hard disk or magnetic tape connected to the host collecting device 32, or an optical disk device.

The selection item extracting section 44 is provided in the buffer memory 4
Of each trace data 23 temporarily stored in 3,
The trace data 23 of the type corresponding to the type (save item) 50 registered in the save selection item table 49 is extracted and sent as save data 51 to the next data compression unit 45. The data compression unit 45 inputs the save data 5
And compress the compressed data 52 that has been compressed by the external recording device 4
Write to 6.

As described above, the host collection device 32 has the SC
Of the host transfer data 26 transferred from the SI bus monitor device 31, only the trace data 23 of the type specified by the user (operator) with the keyboard 47 is transferred to the external recording device 4.
6 can be recorded and held.

Incidentally. Since this external recording device 46 has a storage capacity that is significantly larger than the trace memory 10 of the SCSI bus monitor device 31, it is not necessary to consider the storage capacity as a problem, but unlike the device of the embodiment, data storage The storage capacity of the external storage device 46 can be used more effectively by compressing and storing.

In the SCSI bus monitor device 31 and the bus monitor system configured as described above, when the storage amount of the trace data 23 sequentially stored in the trace memory 10 exceeds a set value that can be arbitrarily set by the user,
Busy signal 41 is automatically output to bus 1,
The transmission of the SCSI signal 7 from all the information processing devices 2 to the bus 1 is blocked. Then, the trace data 23 accumulated in the trace memory 10 is transferred to the external host collection device 32 within the busy signal output period.

Therefore, the SCSI signal 7 is not sent from the other information processing device 2 to the bus 1 during the busy signal output period. Therefore, even if the storage capacity of the trace memory 10 is small, the trace data 23 The SCSI signal 7 can be monitored without omission during the collection process, and the event to be recorded can be reliably traced and stored.

The present invention is not limited to the above embodiment. For example, as the simplest method of realizing the memory monitoring circuit 33, the most significant bit of the memory address 17 can be used as it is as the alarm signal 35.

In this case, the recorded trace data 23
Since the most significant bit of the memory address 17 becomes "1" when exceeds 50% of the total storable capacity of the trace memory 10, the trace data 23 is accumulated in more than half of the trace memory 10. Then, the busy signal generator 34 receives the next bus free detection signal 40 from the monitor sequencer 12a.
After that, the busy signal 41 may be forcibly output onto the bus 1.

[0073]

As described above, in the SCSI bus monitor device of the present invention, when the storage amount of the trace memory exceeds the set value, a busy signal is forcibly sent to the bus and another bus is sent to the bus. The output of the SCSI signal from the information processing device is interrupted. Therefore, it becomes possible to transfer the trace data accumulated in the trace memory to the external host collection device during this interruption period.

As a result, it is possible to prevent the transition information of the SCSI signal from being lost during the transfer period of the trace data, and to inexpensively monitor and operate the trace of the SCSI signal for a long time without using special parts. Can be implemented without omission.

Furthermore, even in the host collection device, the SC
Of the trace data input from the SI bus monitor device, only the trace data of the type that the user particularly needs can be extracted and stored and held, so that the storage capacity of the external storage device can be effectively used. At the same time, the analysis work on the trace data can be efficiently advanced at a later date.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a SCSI bus monitor device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a memory monitoring circuit in the device of the embodiment.

FIG. 3 is a diagram showing a truth table stored in a comparison circuit of the memory monitoring circuit.

FIG. 4 is a time chart for explaining bus-free detection timing and busy signal output timing in the apparatus of the embodiment.

FIG. 5 is a flowchart showing the operation of the apparatus according to the embodiment.

FIG. 6 is a time chart showing the operation of the apparatus of the embodiment.

FIG. 7 is a block diagram showing a schematic configuration of a host collection device incorporated in a bus monitor system according to an embodiment of the present invention.

FIG. 8 is a block diagram showing a schematic configuration of a conventional SCSI bus monitor device.

[Explanation of symbols]

1 ... Bus, 2 ... Information processing device, 3 ... Adapter, 6 ... Bus receiving section, 8a ... Event detection circuit, 9 ... Bus signal latch, 10 ... Trace memory, 12a ... Monitor sequencer, 14 ... Time stamp generating circuit, 16 ... memory address generation circuit, 24 ... host bus interface circuit,
32 ... Host collecting device, 33 ... Memory monitoring circuit, 34 ...
Busy signal generation circuit, 38 ... Alarm setting register, 3
9 ... Comparison circuit, 43 ... Buffer memory, 44 ... Selection item extraction unit, 45 ... Data compression unit, 46 ... External recording device, 4
7 ... Keyboard, 49 ... Save selection item table

Claims (4)

[Claims] 1. A bus receiving section for taking in a SCSI signal transmitted on a bus connecting between information processing apparatuses, and an event to be recorded is detected from a transition of the SCSI signal taken in by the bus receiving section. Event detection means, a trace memory that sequentially stores the state of the SCSI signal when the event detection means detects the event as trace data, and an alarm is issued when the storage amount of the trace memory exceeds a set value. A memory monitoring unit for outputting; a bus-free state detecting unit for detecting a transition to the bus-free state before a time when all the information processing devices connected to the bus consider the bus to be in the bus-free state; When the monitoring means outputs an alarm and the bus-free state detecting means detects a bus-free state, a busy signal is sent to the bus. A busy signal output means for outputting, a trace data transfer means for transferring the trace data stored in the trace memory to the outside after the output of the busy signal, and a trace data transfer means for responding to the end of the transfer of the trace data by the trace data transfer means. And a bus signal canceling means for canceling the busy signal. 2. The memory monitoring means makes it possible to set the set value from the outside, and the set value input means converts the set value into a corresponding set address, and the setting converted by the set value input means. An address comparing means for comparing an address with a write address for writing the trace data in the trace memory and outputting the alarm when the write address exceeds a set address. Item 3. The SCSI bus monitor device according to Item 1. 3. The bus-free state detection time in the bus-free state detecting means is a time at which all the information processing devices connected to the bus have released a busy signal to the bus, The busy signal output time in the busy signal output means is after the bus free state detection time and when the busy signal to be output reaches all the information processing devices, all the information processing devices are on the bus. 3. The SCSI bus monitor device according to claim 1, wherein the SCSI bus monitor device is set before the time to be regarded as a free state. 4. A bus monitor system comprising: the SCSI bus monitor device according to claim 1; and a host collection device that processes trace data transferred from the SCSI bus monitor device to the outside. Is a buffer memory for temporarily storing the trace data sequentially output from the SCSI bus monitor device, and a trace for extracting trace data corresponding to an event designated from the outside from the trace data stored in the buffer memory. Data extraction means,
An external recording device which stores and holds the trace data extracted by the trace data extracting means.