JPH0731629B2 - アドレス・ジエネレータ - Google Patents

アドレス・ジエネレータ

Info

Publication number
JPH0731629B2
JPH0731629B2 JP61078087A JP7808786A JPH0731629B2 JP H0731629 B2 JPH0731629 B2 JP H0731629B2 JP 61078087 A JP61078087 A JP 61078087A JP 7808786 A JP7808786 A JP 7808786A JP H0731629 B2 JPH0731629 B2 JP H0731629B2
Authority
JP
Japan
Prior art keywords
array
address
index
displacement
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61078087A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61231639A (ja
Inventor
アラン・ジエイ・デイアフイールド
サン‐チ・シウ
Original Assignee
レイセオン カンパニ−
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by レイセオン カンパニ− filed Critical レイセオン カンパニ−
Publication of JPS61231639A publication Critical patent/JPS61231639A/ja
Publication of JPH0731629B2 publication Critical patent/JPH0731629B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
JP61078087A 1985-04-05 1986-04-04 アドレス・ジエネレータ Expired - Lifetime JPH0731629B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US72033085A 1985-04-05 1985-04-05
US720330 1985-04-05

Publications (2)

Publication Number Publication Date
JPS61231639A JPS61231639A (ja) 1986-10-15
JPH0731629B2 true JPH0731629B2 (ja) 1995-04-10

Family

ID=24893595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61078087A Expired - Lifetime JPH0731629B2 (ja) 1985-04-05 1986-04-04 アドレス・ジエネレータ

Country Status (5)

Country Link
EP (1) EP0201174B1 (forum.php)
JP (1) JPH0731629B2 (forum.php)
AU (2) AU582632B2 (forum.php)
CA (1) CA1250370A (forum.php)
DE (1) DE3650754T2 (forum.php)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4882683B1 (en) * 1987-03-16 1995-11-07 Fairchild Semiconductor Cellular addrssing permutation bit map raster graphics architecture
JP2690932B2 (ja) * 1988-03-18 1997-12-17 株式会社日立製作所 ディジタル信号処理プロセッサおよびディシタル信号処理プロセッサシステム
US6170046B1 (en) * 1997-10-28 2001-01-02 Mmc Networks, Inc. Accessing a memory system via a data or address bus that provides access to more than one part
GB0130534D0 (en) * 2001-12-20 2002-02-06 Aspex Technology Ltd Improvements relating to data transfer addressing
JP5811099B2 (ja) * 2010-11-24 2015-11-11 日本電気株式会社 メモリ制御装置、及びメモリ制御方法
CN113282314B (zh) * 2021-05-12 2024-04-12 聚融医疗科技(杭州)有限公司 一种超声扫描控制参数下发方法及系统
US12105625B2 (en) * 2022-01-29 2024-10-01 Ceremorphic, Inc. Programmable multi-level data access address generator

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051551A (en) * 1976-05-03 1977-09-27 Burroughs Corporation Multidimensional parallel access computer memory system
JPS6051732B2 (ja) * 1978-08-31 1985-11-15 富士通株式会社 デ−タ・ベ−スを有するデ−タ処理システム

Also Published As

Publication number Publication date
AU602293B2 (en) 1990-10-04
CA1262968C (forum.php) 1989-11-14
DE3650754D1 (de) 2001-08-02
JPS61231639A (ja) 1986-10-15
DE3650754T2 (de) 2001-09-20
CA1250370A (en) 1989-02-21
AU5486086A (en) 1986-10-09
AU3478789A (en) 1989-09-07
AU582632B2 (en) 1989-04-06
EP0201174A3 (en) 1988-12-14
EP0201174A2 (en) 1986-11-12
EP0201174B1 (en) 2001-05-16

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