JPH07307653A - Switching element driving circuit - Google Patents

Abstract

PURPOSE:To control the duty ratio of the driving signal or a switching element, which is obtained from a driving circuit using a pulse transformer and a clamping circuit, in a wide range. CONSTITUTION:A control signal 6 which has the duty ratio controlled and is obtained from a control circuit 2a has the frequency divided by a frequency dividing circuit 7 to obtain first and second control signals 81 and 82 where the high level period and the low level period are alternately arranged. First and second driving circuits 91 and 92 are synchronously controlled by these signals 81 and 82 to obtain first and second driving signals 101 and 102, and these signals 101 and 102 are synthesized by diodes D3 and D4 to generate a driving signal 3, and a switching element Q is driven. Consequently, the duty ratio is controlled in a wide range regardless of restrictions on the clamp voltage when first and second driving circuits consist of pulse transformers and clamping circuits having back electromotive forces of these pulse transformers, and the performance of the switching power conversion device is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power converter for switching a primary side input power by a switching element to obtain a power converted output to a secondary side.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram conceptually showing a conventional switching power converter. In FIG. 5, the input AC voltage is converted into a DC voltage by the rectifier circuit 1, and this DC voltage is the drive signal 3 obtained from the switch element drive circuit 2.
Is converted into pulsed AC power by the switch element Q which is ON / OFF controlled by and is output via the transformer 4.

The switch element drive circuit 2 is configured to include, for example, a PWM control circuit and the like, and is configured to output a drive signal 3 having a duty ratio suited to the purpose.

Since such a switching power converter is small and has high efficiency, it is widely used in various industrial equipment and consumer equipment as a switching regulator, an inverter for driving a motor, and the like.

As the switch element Q, for example, elements such as bipolar transistors, FETs, IGBTs, SITs, various thyristors and the like are used.

The switching operation is performed by these elements transitioning between two states of conduction and non-conduction by the drive signal 3. However, if the transition time is long, the energy loss of the elements becomes large. Further, it is generally said that the switching power converter can be downsized when the switching frequency of the switch element Q is high.

Therefore, in recent years, it has been required to further increase the switching frequency. At present, switching elements such as bipolar transistors, FETs, IGBTs, SITs, etc. are used at a switching frequency of several tens of KHz or more, and a switching element drive circuit 2 is designed according to the characteristics of these elements.

FIG. 6 shows a conventional switch element drive circuit 2 when a bipolar transistor Q ₁ is used as a switch element, and FIG. 7 shows a conventional switch element drive circuit 2 when an FET Q ₂ is used as a switch element. Show.

[0009] In FIGS. 6 and 7, the control circuit 2a driving signal 3 obtained from the capacitor C for speed-up, the base terminal or gate terminal of the FETs Q ₂ of the bipolar transistor Q ₁ via the resistor R ₁ that includes a PWM circuit Added to. When the drive signal 3 is a positive voltage, the drive current is supplied from the base terminal of the bipolar transistor Q ₁ .
FETQ bipolar transistor Q ₁ and the driving voltage is applied to the gate terminal at _2, FETQ ₂ is rendered conductive.

[0010] When the drive signal 3 becomes zero, the bipolar transistor Q ₁ driving voltage of the driving current and the FETs Q ₂ of the bipolar transistor Q ₁ is turned to zero, FETs Q ₂
Transitions to the non-conducting state. At this time, the electric charge accumulated in the input capacitance parasitic on the bipolar transistor Q ₁ and the FET Q ₂ is discharged, and the discharge current flows through the resistor R 2. In this way, the switching operation of the bipolar transistor Q ₁ and the FET Q ₂ as switching elements is performed.

Next, in the switch element drive circuit 2 as described above, when the power supply voltage V is a high voltage, the emitter voltage of the bipolar transistor Q ₁ or the FET Q.
_When the drain voltage of ₂ fluctuates, it is necessary to insulate the switch element from a part of the switch element drive circuit 2 and ground it separately, and a pulse transformer is used for this insulation.

FIG. 8 shows a configuration example in which a pulse transformer Tr is used in the switch element drive circuit 2 using the FET Q ₂ as a switch element. In FIG. 8, the control circuit 2a
The drive signal 3 obtained from the above is configured to control the FET Q ₂ via the pulse transformer Tr. The diode D ₁ is provided to prevent the discharge current of the input capacitance from flowing to the pulse transformer Tr side when the FET Q ₂ is turned off. By using the pulse transformer Tr in this way, the control circuit 2a and the switch element can be easily electrically insulated.

[0013] When using the pulse transformer Tr, will release the counter electromotive force of the excitation energy of the pulse transformer Tr in the off, transistors or the like for the current supply that is included in the FETs Q ₂ and the control circuit 2a by a counter electromotive force is May be destroyed.

Therefore, in this circuit, the clamp circuit 5 for clamping the voltage of the counter electromotive force to a constant value is provided. In FIG. 8, a clamp circuit 5 including a diode D ₂ and a Zener diode Dz is provided on the secondary side of the pulse transformer Tr. However, pulse transformer Tr
In order to perform steady operation, the excitation energy accumulated in the pulse transformer during the on period must be released during the off period.

FIG. 9 shows a voltage waveform diagram between the primary side terminals of the pulse transformer Tr of FIG. For the above reasons, on,
The following conditions must always be satisfied between the off times T _on and T _off and the input pulse voltage V _PL and the clamp voltage V _CL .

V _PL · T _on ≦ V _CL · T _off (1) Here, the on and off times T _on and T _off are represented by the switching frequency F and the duty ratio D: T _on = D · (1 / F ) (2) T _off = (1-D) · (1 / F) (3) When the above equations (2) and (3) are used in the equation (1), they are transformed into the following equation (4). . V _PL · {D / (1-D)} ≦ V _CL (4)

[0017]

From the above equation (4), it is understood that the clamp voltage V _CL has to be increased as the duty ratio D increases. For example, when the duty ratio D is 0.75, the clamp voltage V _CL needs to be 3 · V _PL or more. In practice the clamp voltage V _CL which can be set to prevent the destruction of other elements by the clamp voltage V _CL as described above is limited, the upper limit of the usable duty ratio D has been limited to reverse thereto. The duty ratio D is a factor that determines the voltage conversion rate of the switching power converter, and there is a problem that if the duty ratio D is limited, the capacity of the power converter is deteriorated.

The present invention has been made to solve the above problems, and in a switch element drive circuit for driving a switch element via a pulse transformer, the limitation of usable duty ratio due to a clamp voltage is improved. However, it is intended to improve the performance of the switching power converter.

[0019]

According to a first aspect of the present invention, a first drive signal generating circuit for generating a first drive signal consisting of a pulse and the first drive signal have a high level period and a low level. A second drive signal generating circuit for generating a second drive signal composed of pulses in which level periods are alternately arranged, a signal obtained by synthesizing the first drive signal and the second drive signal. Is provided as a drive signal for driving the switching element.

In a second aspect of the present invention, a control circuit for generating a control signal composed of pulses whose duty ratio is controlled, and a high level period and a low level period are alternately arranged by dividing the control signal. And a frequency dividing circuit for outputting the first and second control signals, a pulse transformer and a clamp circuit for clamping a counter electromotive voltage generated in the pulse transformer, and operates in synchronization with the first control signal. The first drive circuit for generating the first drive signal, the pulse transformer, and the clamp circuit for clamping the counter electromotive voltage generated in the pulse transformer are configured to synchronize with the second control signal. A second drive circuit for generating a second drive signal in which a high level period and a low level period are alternately arranged with the first drive signal, It synthesizes the drive signal and the second driving signal and the combined signal is provided to a combining circuit which forms a driving signal for driving the switching element.

[0021]

According to the first aspect of the invention, the first and second drive signals in which the high level period and the low level period are alternately arranged are obtained from the first and second drive signal generation circuits, and these signals are obtained. Since the switching element is driven by the combined signal, the duty ratio of the drive signal can be controlled in a wide range even if a pulse transformer is used for each drive signal generation circuit.

According to the second aspect of the present invention, the duty ratio controlled control signal is divided to obtain the first and second control signals in which the high level period and the low level period are alternately arranged. First and second drive signals are obtained by controlling the first and second drive circuits, each of which is composed of a pulse transformer and a clamp circuit, in synchronization with the first and second control signals. Since the switching element is driven by the combined signal of the two, even if the clamp voltage of the clamp circuit that controls the counter electromotive voltage of the pulse transformer is controlled, the two drive circuits are driven in synchronization with the control signal, and The ratio can be controlled over a wide range.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram conceptually showing a switch element drive circuit according to the present invention. In FIG. 1, reference numeral 2a is a control circuit, which generates a control signal 6 composed of pulses whose duty ratio D is controlled. Reference numeral 7 denotes a frequency dividing circuit for dividing the control signal 6, which is a first control signal 8 ₁ and a second control signal 8 _{1 in} which an ON period (high level period) and an OFF period (low level period) of the control signal 6 are alternately distributed. And the control signal 8 ₂ of.

[0024] 9 ₁ first driving circuit for outputting a first drive signal 10 ₁ receives the first control signal 8 _1, 9 ₂ second
Of the first and second drive circuits 9 ₁ and 9 ₂ which output the _second drive signal 10 ₂ in response to the control signal 8 ₂ of
Are each configured to include a pulse transformer, a clamp circuit, and the like.

D ₃ and D ₄ are the first and second drive signals 1
This is a diode for obtaining the drive signal 3 by combining 0 ₁ , 10 ₂ . The drive signal 3 is configured to drive the switching element Q.

The control circuit 2a, the frequency dividing circuit 7 and the first driving circuit 9 ₁ constitute a first driving signal generating circuit, and the control circuit 2a, the frequency dividing circuit 7 and the second driving circuit 9 ₂
Thus, the second drive signal generating circuit is configured. Also,
The diodes D ₃ and D ₄ form a combining circuit.

Next, the operation will be described. FIG. 2A shows the control signal 6 input to the frequency dividing circuit 7, and FIG.
(B) and (c) are first and second control signals 8 ₁ and 8 output from the frequency divider circuit 7 to the first and second drive circuits 9 ₁ and 9 _2.
3 is a timing chart showing ₂ . The first and second control signals 8 ₁ and 8 ₂ input to the first and _second drive circuits 9 ₁ and 9 ₂ each including a pulse transformer are the control signal 6
The pulses are alternately distributed, and the length of the off time is extended by one cycle. As a result, the apparent cycle is doubled, while the on-time does not change. Therefore, the apparent duty ratio D ₁ in the pulse transformer is always equal to the duty ratio D of the control signal 6.

D ₁ = (1/2) D (5) As a result, the magnitude of the clamp voltage V _CL becomes equal to or lower than the pulse voltage V _PL at the maximum from the formula (4), and it is not necessary to set it high as in the conventional case. As a result, the limitation of the duty ratio D, which was limited by the clamp voltage V _CL , is removed, and the duty ratio D can be changed in a wide range from 0 to almost 1, thus improving the voltage conversion capability of the switching power converter. can do.

The first and second drive signals 1 which have been frequency-divided and processed by the first and second drive circuits 9 ₁ and 9 ₂ as described above.
0 ₁ and 10 ₂ are input to the input terminals of the same switching element Q via the diodes D ₃ and D ₄ , respectively, and as a result, the drive signal 3 corresponding to the control signal 6 is transmitted to the switch element Q. .

In FIG. 3, the FET Q is used as the switching element Q.
A specific configuration example of the switch element drive circuit according to the present invention when ₂ is used will be shown. In FIG. 3, first and second drive circuits 9 ₁ and 9 ₂ connected in parallel to each other drive a pulse transformer in accordance with input first and second control signals 8 ₁ and 8 ₂ , respectively. It includes transistors Q ₃₁ and Q ₃₂ , pulse transformers T _r1 and T _r2, and clamp circuits 5 ₁ and 5 ₂ including diodes D ₂₁ and D ₂₂ and zener diodes D _Z1 and D _Z2 . The first and second drive signals 1 output from the first and second drive circuits 9 ₁ and 9 ₂
0 ₁ , 10 ₂ are FETs Q through diodes D ₃ , D ₄
Input to the gate terminal of ₂ .

At the input terminals of the first and second drive circuits 9 ₁ and 9 ₂ , the control signal 6 is alternately divided so that the drive circuits are alternately driven every cycle. Type flip-flop FF and two AND gate circuits AND
A frequency divider circuit 7 composed of 1 and AND2 is connected.

FIG. 4 shows a timing chart of the voltage at each point in FIG. (A) is a control signal 6 inputted to the frequency dividing circuit 7, (b) and (c) are first and second control signals inputted from the frequency dividing circuit 7 to the first and second drive circuits 9 ₁ , 9 ₂ . The two control signals 8 ₁ , 8 ₂ , (d) and (e) are the first and second drive signals 10 ₁ , 10 ₂ , (f) as the voltage between the secondary terminals of the pulse transformers T _r1 , T _r2. ) Indicates the drive signal 3 input to the gate terminal.

As shown in FIG. 4, the control signal 6 (a) is divided into the ON signal by the frequency dividing circuit 7 into the first and second control signals 8 ₁ , 8 ₂ (b) and (c). Two pulse transformers T _r1 and T _r2 are driven in synchronization with the control signal 6. (D) As shown in (e), the voltage waveform between the secondary terminals of the pulse transformer (first and second drive signals 1
0 ₁ , 10 ₂ ) generate a counter electromotive voltage corresponding to the voltage-time product during the on-time during the off-period during a certain time. However, since the off period becomes long for the reason described above, even if the clamp voltage V _CL determined by the Zener voltage is not high, it is reset during the off period and the stable operation can be continued.

[0034]

As described above, according to the first aspect of the present invention, the first and second drive signal generating circuits are arranged such that the high level period and the low level period are alternately arranged. Since the drive signal is obtained and the switching element is driven by a signal obtained by combining these signals, even if a pulse transformer is used for each drive signal generation circuit, the duty ratio of the drive signal can be controlled in a wide range. There is an effect that the performance of the switching power converter can be improved.

According to the second aspect of the present invention, the duty ratio controlled control signal is divided to obtain the first and second control signals in which the high level period and the low level period are alternately arranged. First and second drive signals are obtained by controlling the first and second drive circuits, each of which is composed of a pulse transformer and a clamp circuit, in synchronization with the first and second control signals, and these are obtained. Since the switching element is driven by the combined signal, even if the clamp voltage of the clamp circuit that limits the counter electromotive voltage of the pulse transformer is limited, the duty ratio can be controlled in a wide range, improving the performance of the switching converter. There is an effect that can be made.

[Brief description of drawings]

FIG. 1 is a block diagram conceptually showing a switch element drive circuit according to the present invention.

FIG. 2 is a timing chart conceptually showing the operation of the frequency dividing circuit shown in FIG.

FIG. 3 is a circuit diagram showing an embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 5 is a block diagram conceptually showing a conventional switching power converter.

FIG. 6 is a circuit diagram showing a conventional switch element drive circuit when a bipolar transistor is used as a switch element.

FIG. 7 is a circuit diagram showing a conventional switch element drive circuit 2 when an FET is used as a switch element.

FIG. 8 is a circuit diagram showing a configuration example in which a pulse transformer Tr is used in a switch element drive circuit 2 using a FET Q ₂ as a switch element.

9 is a waveform diagram showing a voltage waveform between primary terminals of the pulse transformer shown in FIG.

[Explanation of symbols]

Q switching element Q ₂ FET 3 drive signal 5 clamp circuit 6 control signal 7 frequency divider circuit 8 ₁ first control signal 8 ₂ second control signal 9 ₁ first drive circuit 9 ₂ second drive circuit 10 ₁ first 1 drive signal 10 ₂ 2nd drive signal D ₃ , D ₄ diode T _r1 , T _r2 pulse transformer

Claims (2)

[Claims] 1. A first drive signal generation circuit for generating a first drive signal composed of a pulse, and the first drive signal comprises a pulse in which a high level period and a low level period are alternately arranged. A second drive signal generating circuit for generating a second drive signal, combining the first drive signal and the second drive signal,
A switching element drive circuit comprising a combination circuit which forms a combined signal with a drive signal for driving a switching element. 2. A control circuit for generating a control signal composed of pulses whose duty ratio is controlled, and a first circuit and a second circuit in which a high level period and a low level period are alternately arranged by dividing the control signal. And a clamp circuit that clamps a counter electromotive voltage generated in the pulse transformer, and operates in synchronization with the first control signal. And a clamp circuit that clamps a counter electromotive voltage generated in the pulse transformer, and operates in synchronization with the second control signal. A second drive circuit for generating a second drive signal in which a high level period and a low level period are alternately arranged with the first drive signal, the first drive signal and the second drive circuit And the dynamic signal synthesis,
A switching element drive circuit comprising a combination circuit which forms a combined signal with a drive signal for driving a switching element.