JP2016092747A - Switching element drive circuit, heater device and image formation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow for driving of a switching element based on a pulse width modulation signal not having any limitation in the DUTY ratio, without using a signal having a frequency higher than that of the pulse width modulation signal.SOLUTION: A switching element drive circuit 1 generates a plurality of split pulse width modulation signals S4, S5 by splitting a pulse width modulation signal S1, drives a plurality of pulse transformers 31, 32 by using the split pulse width modulation signals, and generates a gate signal S10 for driving a switching element 5 by synthesizing pulse signals S11, S12 outputted from the secondary of the pulse transformer. Means for generating a gate signal S10 includes a plurality of diodes 51, 52 having one ends connected with the secondary of respective pulse transformers for the purpose of performing OR operation of the pulse signal, and a capacitor 53 connected to the side where the other ends of diodes are connected each other, and smoothing the gate signal S10 by smoothing the pulse signal.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a circuit for driving a switching element, a heater device including the circuit, and an image forming apparatus.

  When the switching element is switched by a pulse width modulation signal (PWM signal), a method of transmitting the PWM signal to the switching element via a pulse transformer is used. According to the pulse transformer, it is possible to insulate the control system that generates the PWM signal from the load circuit including the switching element. In addition, since power can be transmitted together with the signal, it is not necessary to provide a power source for signal transmission on the load circuit side.

  There are the following prior arts for driving a switching element using a pulse transformer.

  The switching transistor drive circuit described in Patent Document 1 performs an AND operation on each of a rectangular wave signal having a frequency higher than that of a pulse width modulation signal and an on-time ratio of approximately 50% and its inverted signal, and the pulse width modulation signal. To generate a first signal and a second signal. In response to each of the first signal and the second signal, a current that induces a magnetic flux in the opposite direction in the common magnetic path of the pulse transformer is returned to one coil of the pulse transformer. Then, the voltage induced in the other coil of the pulse transformer is rectified and applied to the control electrode of the switching transistor.

  The switching element driving circuit described in Patent Document 2 divides a control signal controlled by a duty ratio obtained from a control circuit, and first and second high level periods and low level periods are alternately arranged. Get control signal. The first and second pulse transformers are synchronously controlled by these control signals to obtain the first and second signals. Then, these signals are combined by two diodes to generate a drive signal, and the switching element is driven.

JP-A-4-105416 JP-A-7-307653

  In the prior art of Patent Document 1, a PWM signal is transmitted by push-pull drive using a single pulse transformer. In push-pull drive in which current flows in one or the other two directions opposite to each other with respect to the primary side coil, the transfer characteristic deteriorates due to accumulation of magnetization as one of the non-energized states continues. In order to reduce the deterioration of the transfer characteristic, in this prior art, it is necessary to make the frequency of the rectangular wave signal for performing the logical product operation with the PWM signal sufficiently higher than the frequency of the PWM signal. If the frequency of the rectangular wave signal is the same as the frequency of the PWM signal, the logical product of the rectangular wave signal or its inverted signal and the PWM signal becomes 0 when the DUTY ratio (duty ratio) of the PWM signal is 50% or less. Therefore, push-pull drive without energization of one side is performed.

  As described above, in the prior art of Patent Document 1, a rectangular wave signal having a frequency sufficiently higher than that of the PWM signal is generated in order to generate a signal for driving the pulse transformer when transmitting a PWM signal having a DUTY ratio of 50% or less. There was a problem that was necessary. For this reason, for example, in order to increase the frequency of the PWM signal in order to reduce the size of the switching element, a high-performance pulse transformer adapted to a higher frequency must be used.

  In addition, in push-pull drive, the output of the pulse transformer is composed of positive and negative pulses, so that a single polarity pulse composed of these pulses by a rectifier circuit is distorted with a reduced amplitude at the joint of the composite. There was also a problem that it was easy to become a pulse.

  On the other hand, in the prior art of Patent Document 2, first and second drive signals for driving two pulse transformers are generated by a frequency dividing circuit that alternately distributes each pulse of a PWM signal that is a pulse train signal. Since each pulse of the PWM signal is distributed alternately, when the DUTY ratio of the PWM signal is 100% (signal value is constant), a desired drive signal cannot be obtained and the pulse transformer cannot be driven correctly. That is, there is a problem that the DUTY ratio of the PWM signal that can be transmitted is limited to less than 100%.

  The present invention has been made in view of such a problem, and is capable of driving a switching element based on a pulse width modulation signal with no limit on the DUTY ratio without using a signal having a higher frequency than the pulse width modulation signal. The purpose is to be.

  A switching element driving circuit according to an embodiment of the present invention is a switching element driving circuit for driving a switching element by a gate signal generated based on a pulse width modulation signal, and the pulse width modulation signal is within one cycle. And dividing means for generating a plurality of divided pulse width modulation signals and pulse driving for respectively driving primary sides of a plurality of pulse transformers provided independently using the plurality of divided pulse width modulation signals And gate signal generation means for generating the gate signal by synthesizing pulse signals output from secondary sides of the plurality of pulse transformers. The gate signal generating means includes a plurality of diodes having one end connected to the secondary side of each pulse transformer and a plurality of other ends of the plurality of diodes connected to each other in order to perform an OR operation of the plurality of pulse signals. And a capacitor for smoothing the gate signal synthesized by smoothing the pulse signal.

  In a preferred embodiment, a MOSFET is connected as the gate signal generating means in place of each of the plurality of diodes, and a body diode built in each of the MOSFETs functions as the diode. The MOSFET is controlled to turn on in synchronization with a signal obtained by inverting the pulse width modulation signal.

  According to the present invention, the switching element can be driven based on a pulse width modulation signal with no limitation on the DUTY ratio without using a signal having a higher frequency than the pulse width modulation signal.

It is a circuit diagram which shows the outline | summary of a structure of the switching element drive circuit which concerns on one Embodiment of this invention. It is a timing chart which shows the mutual relationship of the some signal in FIG. It is a wave form diagram which shows the function of the capacitor | condenser of the gate signal production | generation part in a switching element drive circuit. It is a circuit diagram which shows the detail of a structure of a switching element drive circuit. 5 is a timing chart showing the mutual relationship among a plurality of signals in FIG. It is a block diagram which shows the modification of a structure of the division part in a switching element drive circuit. It is a timing chart which shows the mutual relationship of the some signal containing the signal produced | generated by the division part of FIG. It is a circuit diagram which shows the structure of the heater apparatus provided with the switching element drive circuit. It is a figure which shows the schematic structure of the image forming apparatus provided with the heater apparatus of FIG. 3 is a flowchart of heater control in the image forming apparatus. 3 is a flowchart of heater control in the image forming apparatus.

  FIG. 1 shows an outline of the configuration of a switching element drive circuit 1 according to an embodiment of the present invention.

  The switching element driving circuit 1 is a circuit for driving the switching element 5 by a gate signal S10 generated based on a pulse width modulation signal (hereinafter referred to as PWM signal) S1. The switching element driving circuit 1 includes a dividing unit 20, a pulse driving unit 40, and a gate signal generating unit 50.

  The dividing unit 20 is a dividing unit that divides the PWM signal S1 provided by the PWM circuit 10 within one period to generate a plurality of divided pulse width modulation signals. The dividing unit 20 includes a rectangular wave oscillator 21, a NOT gate 22, and two AND gates 23 and 24.

  The rectangular wave oscillator 21 generates a rectangular wave signal S2 having the same frequency as the PWM signal S1 and having a DUTY ratio of 50%. The NOT gate 22 generates an inverted rectangular wave signal S3 that is a signal obtained by inverting the rectangular wave signal S2.

  The AND gate 23 is a first modulation unit that performs a logical product operation of the PWM signal S1 and the rectangular wave signal S2 to generate a first divided PWM signal S4 that is one of the divided pulse width modulation signals. The AND gate 24 is a second modulation unit that performs a logical product operation of the PWM signal S1 and the inverted rectangular wave signal S3 to generate a second divided pulse width modulation signal S5 that is another one of the divided pulse width modulation signals. is there.

  The pulse drive unit 40 is a pulse drive unit that drives the primary sides of a plurality of independently provided pulse transformers 31 and 32 using the first divided PWM signal S3 and the second divided PWM signal S4. The pulse driving unit 40 includes transistors 41 and 42 and resistors 43 and 44.

  The transistors 41 and 42 intermittently flow current to the primary side of the pulse transformers 31 and 32 in accordance with the first divided PWM signal S4 or the second divided PWM signal S5 input to the respective bases via the resistors 43 and 44. . As a result, a pulse signal S11 synchronized with the first divided PWM signal S4 is output from the secondary side of the pulse transformer 31, and a pulse signal S12 synchronized with the second divided PWM signal S5 is output from the secondary side of the pulse transformer 32. The

  Commutating diodes 33 and 34 are connected to the primary sides of the pulse transformers 31 and 32, respectively. The primary side and the secondary side of each of the pulse transformers 31 and 32 are electrically insulated, and the dividing unit 20 and the pulse driving unit 30 provided on the primary side are connected to the power source 7 for the switching element 5. Are operated by another insulated power supply 8.

  The gate signal generator 50 is a gate signal generator that combines the pulse signals S11 and S12 output from the secondary sides of the plurality of pulse transformers 31 and 32 to generate the gate signal S10. The gate signal generation unit 50 smoothes the plurality of diodes 51 and 52 for performing a logical sum operation of the plurality of pulse signals S11 and S12 and the gate signal S10 synthesized by smoothing the pulse signals S11 and S12. And a capacitor 53.

  The plurality of diodes 51 and 52 have one end (anode) connected to the secondary side of each of the pulse transformers 31 and 32 and the other ends (cathodes) connected to each other. The capacitor 53 is connected to the cathode side of the plurality of diodes 51 and 52 that are connected to each other.

  The gate signal S10 generated by the gate signal generation unit 50 is divided by the resistors 54 and 55 and input to the switching element 5. When the switching element 5 is driven by the gate signal S10, the power supply from the power source 7 to the load 6 is turned on and off.

  FIG. 2 shows the mutual relationship among a plurality of signals related to the operation of the switching element drive circuit 1.

  The PWM signal S1 is a signal for controlling ON / OFF DUTY of the switching element 5. The frequency of the PWM signal S1 is set to an arbitrary value within a range of 10 k to 50 kHz, for example. In the switching element drive circuit 1, the duty ratio (ratio of the on-level period to the period T) of the PWM signal S1 may be an arbitrary value within a range of 0 to 100%. FIG. 2 shows, as an example, a case where the DUTY ratio of the PWM signal S1 is 100%, 70%, and 30%. The same applies to FIGS. 5 and 7 described later.

  The DUTY ratios of the rectangular wave signal S2 and the inverted rectangular wave signal S3 are both 50%, and are constant regardless of the DUTY ratio of the PWM signal S1. However, the DUTY ratio of the rectangular wave signal S2 and the DUTY ratio of the inverted rectangular wave signal S3 do not necessarily have to be the same, and the sum of these may be 100%.

  The PWM signal S1 and the rectangular wave signal S2 have the same polarity and the same phase. Since the frequency of the PWM signal S1 and the frequency of the rectangular wave signal S2 are the same as described above, the frequency of the inverted rectangular wave signal S3 obtained by inverting the rectangular wave signal S2 is also the same as the frequency of the PWM signal S1 and the rectangular wave signal S2. .

  The first divided PWM signal S4 is a logical product of the PWM signal S1 and the rectangular wave signal S2, and the second divided PWM signal S5 is a logical product of the PWM signal S1 and the inverted rectangular wave signal S3. Signal.

  The pulse signal S11 corresponds to the first divided PWM signal S4, and the pulse signal S12 corresponds to the second divided PWM signal S5. A signal obtained by ORing these pulse signals S11 and S12 is a gate signal S10.

  As shown in the figure, when the DUTY ratio of the PWM signal S1 is 100%, the DUTY ratios of the pulse signal S11 and the pulse signal S12 are both 50%, and the DUTY ratio of the gate signal S10 is 100%, which is the same as that of the PWM signal S1. is there.

  When the DUTY ratio of the PWM signal S1 is 70%, the DUTY ratio of the pulse signal S11 is 50%, the DUTY ratio of the pulse signal S12 is 20%, and the DUTY ratio of the gate signal S10 is the same as the PWM signal S1. %.

  When the DUTY ratio of the PWM signal S1 is 30%, the DUTY ratio of the pulse signal S11 is 30%, the DUTY ratio of the pulse signal S12 is 0%, and the DUTY ratio of the gate signal S10 is the same as that of the PWM signal S1. Same 30%.

Thus, according to the switching element drive circuit 1, the DUTY ratio of the PWM signal S1 is 10
Whether the signal is 0% or less than 100%, the gate signal S10 having the same DUTY ratio as the PWM signal S1 can be output.

  FIG. 3 shows the function of the capacitor 53 of the gate signal generation unit 50. The capacitor 53 reduces the amount of decrease (sag) in the amplitude of the pulse signals S11 and S12, and smoothes the pulse waveform of the gate signal S10 obtained by synthesizing these pulse signals S11 and S12.

  FIG. 4 shows the details of the configuration of the switching element driving circuit 1, and FIG. 5 shows the mutual relationship among a plurality of signals in FIG. 4, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted or simplified. The relationship between each signal from the PWM signal S1 to the pulse signal S12 depicted in the upper half of FIG. 5 is the same as that in FIG.

  Referring also to FIG. 1, in the switching element drive circuit 1 of FIG. 4, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 56, instead of the plurality of diodes 51 and 52 in the gate signal generation unit 50 of FIG. 57 is connected.

  In the present embodiment, the MOSFETs 56 and 57 are n-channel enhancement type. The sources of the MOSFETs 56 and 57 are connected to one end on the secondary side of the pulse transformers 31 and 32, and the drains are connected to the capacitor 53. Since it is an enhancement type, the MOSFETs 56 and 57 when the voltage is not applied to the gate are in an off state (normally off).

  In the MOSFETs 56 and 57, the source electrode layer is joined to the internal p layer (bulk). For this reason, the MOSFETs 56 and 57 incorporate so-called body diodes 561 and 571 each having a pn junction between the bulk and the drain (n layer). The anodes of the body diodes 561 and 571 are connected to the secondary side of the pulse transformers 31 and 32, and the cathode is connected to the capacitor 53. That is, the body diodes 561 and 571 incorporated in the respective MOSFETs 56 and 57 function as the diodes 51 and 52 in the circuit of FIG.

  The switching element drive circuit 1 is provided with an inverted gate signal generation unit 60 as second gate signal generation means for controlling the MOSFETs 56 and 57. The inverted gate signal generation unit 60 controls the MOSFETs 56 and 57 to be turned on in synchronization with the inverted PWM signal S6 obtained by inverting the PWM signal S1.

  The inverted gate signal generator 60 includes a transistor 61 that is turned on / off based on the PWM signal S1, a second pulse transformer 62 driven by the transistor 61, a commutation diode 63, and a NOT gate 64 that inverts the PWM signal S1. And have. The pulse transformer 62 includes a plurality of secondary windings 622 and 623 for outputting gate signals S6 'for the MOSFETs 56 and 57, respectively. The commutation diode 63 is connected to the primary side of the pulse transformer 62.

  The transistor 61 intermittently supplies a current to the primary side of the pulse transformer 62 in accordance with the inverted PWM signal S6 from the NOT gate 64. As a result, the gate signals S7 and S8 corresponding to the inverted PWM signal S6 are output from the secondary windings 622 and 623 of the pulse transformer 62. The gate signal S7 is divided by resistors 65 and 66 and input to the MOSFET 56, and the gate signal S8 is divided by resistors 67 and 68 and input to the MOSFET 57.

  Referring also to FIG. 5, since the gate signals S7 and S8 correspond to the inverted PWM signal S6 obtained by inverting the PWM signal S1, when the inverted PWM signal S6 is at the off level, that is, when the PWM signal S1 is at the on level, the MOSFET 56 , 57 are turned off. At this time, current Ia flows from each of the pulse transformers 31 and 32 to the capacitor 53 via the body diodes 561 and 571. That is, the pulse signals S11 and S12 are combined by the body diodes 561 and 571, and the switching element 5 is turned on as the gate signal S10.

  On the other hand, when the inverted PWM signal S6 is on level, that is, when the PWM signal S1 is off level, the MOSFETs 56 and 57 are turned on. As a result, the excitation energy accumulated in the pulse transformers 31 and 32 is released as a current Ib opposite to the current Ia. In addition to commutation on the primary side, the excitation energy is forcibly discharged on the secondary side, so that the pulse transformers 31 and 32 can be quickly operated even when the DUTY ratio of the PWM signal S1 is large and a large amount of excitation energy is accumulated. Reset.

  That is, even when the upper limit of the variable range of the DUTY ratio of the PWM signal S1 is set high, the signal transmission characteristics of the pulse transformers 31 and 32 can be kept good and the switching element 5 can be driven stably.

  FIG. 6 shows a modification of the configuration of the dividing unit 20 in the switching element driving circuit 1, and FIG. 7 shows the mutual relationship among a plurality of signals including the signal generated by the dividing unit 20b of FIG. ing.

  In the dividing unit 20b of FIG. 6, in order to extend the time width of the pulse dividing circuit 25, which is an extending means for extending the time width (pulse width) of the first divided PWM signal S4, and the second divided PWM signal S5. The pulse extension circuit 26 is provided.

  The pulse extension circuit 25 generates a rectangular wave signal S2 'in which the time width of the rectangular wave signal S2 is extended by delaying the falling edge of the rectangular wave signal S2. The extension amount may be, for example, about 5 to 10% of the time width of the rectangular wave signal S2. Similarly, the pulse extension circuit 26 generates an inverted rectangular wave signal S3 'in which the time width of the inverted rectangular wave signal S3 is extended.

  The AND gate 23 performs a logical product operation of the PWM signal S1 and the rectangular wave signal S2 'to generate a first divided PWM signal S4' obtained by extending the first divided PWM signal S4. Further, the AND gate 24 performs an AND operation on the PWM signal S1 and the inverted rectangular wave signal S3 'to generate a second divided PWM signal S5' obtained by extending the second divided PWM signal S5.

  Since the first divided PWM signal S4 ′ and the second divided PWM signal S5 ′ generated by the dividing unit 20b drive the pulse transformers 31 and 32 as in the example of FIG. 1, the transistors 41 and 42 of the pulse driving unit 40 are used. To be applied.

  As shown in FIG. 7, a part of the pulse of the first divided PWM signal S4 'and a part of the pulse of the second divided PWM signal S5' overlap with each other in time. As a result, when the pulse signals S11 and S12 based on the first divided PWM signal S4 ′ and the second divided PWM signal S5 ′ are combined, it is possible to prevent a gap between the pulses from being generated at the joint, and to obtain a favorable waveform. The switching element 5 can be driven by the gate signal S10b.

  FIG. 8 shows a configuration of the heater device 70 provided with the switching element drive circuit 1, and FIG. 9 shows a schematic configuration of the image forming apparatus 100 provided with the heater device 70 of FIG.

  In FIG. 8, a heater device 70 includes a switching element driving circuit 1, a switching element 5b driven by the switching element driving circuit 1, and a halogen heater 77 whose electric power supplied from the power source 9 is controlled by the switching element 5b. Have. The switching element 5b is an IGBT (insulated gate bipolar transistor), and the switching element drive circuit 1 is used as an IGBT drive circuit.

  AC power is supplied from the power source 9 to the rectifier 71, and the rectified power is input to the high-frequency chopper circuit via a noise filter including capacitors 72 and 73 and a coil 74. The high frequency chopper circuit includes a switching element 5 b, a diode 75, a coil 76, and a halogen heater 77.

  The coil 76, the halogen heater 77, and the collector / emitter of the switching element 5b are connected in series in this order, and a diode 75 is connected in parallel to the coil 76 and the halogen heater 77. The diode 75 is provided to flow magnetic energy accumulated in the coil 76 as a regenerative current.

  The switching element 5b is driven by a gate signal S10 from the switching element drive circuit 1. The gate signal S10 is a pulse-width modulated pulse train signal whose frequency is 20 kHz or higher, which is higher than the audible frequency band. The DUTY ratio of the gate signal S10 is the same as the DUTY ratio of the PWM signal S1 generated by the PWM circuit 10 included in the switching element drive circuit 1.

  The switching element driving circuit 1 generates a PWM signal S1 having a DUTY ratio designated by the controller 101, and outputs a gate signal S10 corresponding to the PWM signal S1 as described above.

  The controller 101 changes the DUTY ratio with respect to the switching element drive circuit 1 so as to increase or decrease the temperature of the fixing device 68 in accordance with the temperature detected by the temperature sensor 79 incorporated in the fixing device 68 together with the halogen heater 77. Instruct.

  The controller 101 may be provided with the PWM circuit 10 and the controller 101 may input the PWM signal S1 to the switching element drive circuit 1. In that case, the switching element drive circuit 1 may not include the PWM circuit 10.

  An image forming apparatus 100 shown in FIG. 9 is an electrophotographic color printer including a tandem image forming unit 20. However, the present invention is not limited to this, and a monochrome printer, a copier, a multifunction machine, or a facsimile machine may be used.

  The image forming apparatus 100 takes out the paper P one by one from the paper feed cassette 65 and feeds it to the transport path 66, and transports the paper P in the M1 direction. The toner image created by the image forming unit 20 is once transferred to the transfer belt, and the toner image is transferred from the transfer belt to the paper P. Then, after fixing the toner image on the paper P by the fixing device 68, the paper P is discharged to the paper discharge tray 69.

  The fixing device 68 includes a heating roller and a pressure roller, and is configured to apply heat and pressure to the paper P with these rollers. The above-described halogen heater 77 is incorporated as a heat source in the heating roller. When the paper P passes through the fixing device 68, the heater device 70 is controlled by the controller 101 so that the heating roller has a temperature suitable for fixing.

  10 and 11 show a flow of heater control in the image forming apparatus 100. FIG.

  As described above, the switching element drive circuit 1 provided in the image forming apparatus 100 can handle the wide-range PWM signal S1 having a DUTY ratio (ON-DUTY) of 0 to 100%. Therefore, the controller 101 of the image forming apparatus 100 sets the DUTY ratio of the PWM signal S1 within a range of 0 to 100% according to the status of the image forming apparatus 100 as follows.

  When the power switch of the image forming apparatus 100 is turned on (# 11), the controller 101 detects the temperature detected by the temperature sensor 79 (hereinafter, whether the “current temperature Tx” is equal to or higher than a predetermined warm-up completion temperature T1). A check is made (# 12).

  When the current temperature Tx is not equal to or higher than the warm-up completion temperature T1 (NO in # 12), in order to complete the warm-up as soon as possible, the controller 101 sets the DUTY ratio to 100% of the upper limit and turns on the halogen heater 77 (# 13). Thereafter, the current temperature Tx is continuously monitored, and the lighting state in which the DUTY ratio is 100% is maintained during the warm-up until the current temperature Tx becomes equal to or higher than the warm-up completion temperature T1.

  When the current temperature Tx is equal to or higher than the warm-up completion temperature T1 (YES in # 12), the controller 101 sets the status of the image forming apparatus 100 to “warm-up completion” (# 14). In response to this, processing such as display for notifying the completion of warm-up is performed on an operation panel (not shown).

  Subsequently, the controller 101 checks whether a print job is given to the image forming apparatus 100, that is, whether there is a job instruction (# 15). If there is no job instruction (NO in # 15), the flow proceeds to step # 22 in FIG. 11, and the controller 101 sets the status to “standby state”.

  On the other hand, if there is a job instruction (YES in # 15), the controller 101 starts executing the job (# 16), and sets the DUTY ratio to a value within the range of 50% or more (50 to 100%). Then, the halogen heater 77 is turned on (# 17). That is, since heat is taken away by the paper P when the paper P passes through the fixing device 68, the range of the duty ratio during execution of the job is set to the upper limit side of the variable range in order to be able to quickly compensate for the amount of heat taken away. Set to the range.

  Until the job is completed, the controller 101 reduces or increases the DUTY ratio within a range of 50 to 100% so that the current temperature Tx is maintained at the job holding temperature T2 suitable for fixing. (# 18, # 19, # 20, # 21).

  When the job is finished (YES in # 21), the controller 101 sets the status to “standby state” (# 22).

  In the standby state, the controller 101 sets the DUTY ratio to a value within the range of 50% or less (0 to 50%), turns on the halogen heater 77 (# 23), and maintains the current temperature Tx at the standby holding temperature T3. As a result, the DUTY ratio is reduced or increased within a range of 0 to 50% (# 24, # 25, # 26). The standby state continues until a new print job is given (# 15, # 22 to # 26). In the standby state, heat escapes from the fixing device 68 to the air, but the amount of heat is smaller than the amount of heat taken away by the paper P during execution of the job. Therefore, the range of the DUTY ratio in the standby state may be the lower limit side of the variable range.

  When a heater device capable of raising the temperature to the job holding temperature T2 in a short time is mounted, the halogen heater 77 may not be turned on by setting the DUTY ratio in the standby state to 0%. .

  In the above embodiment, the MOSFETs 56 and 57 of the switching element drive circuit 1 are not limited to the n-type, and a circuit can be configured using a p-type MOSFET having a built-in body diode. In addition, the entire or partial configuration of the switching element driving circuit 1, the heater device 70, and the image forming apparatus 100, a control flow, and the like can be appropriately changed in accordance with the spirit of the present invention.

  In the above-described embodiment, the image forming apparatus 100 is described as a printer. However, the image forming apparatus 100 may be provided with a switching element driven by a pulse width modulated signal, and may be a copying machine, a facsimile machine, or a multifunction machine. It may be.

DESCRIPTION OF SYMBOLS 1 Switching element drive circuit 5, 5b Switching element 7, 9 Power supply (Power supply for switching elements)
8 Power supply (another power supply)
20 Dividing part (dividing means)
21 rectangular wave oscillator 23 AND gate (first modulation means)
24 AND gate (second modulation means)
25 Pulse extension circuit (extension means)
31, 32 Pulse transformer 40 Pulse drive unit (pulse drive means)
41, 42 Transistor 50 Gate signal generator (gate signal generator)
51, 52 Diode 53 Capacitor 56, 57 MOSFET
561,571 Body diode 60 Inverted gate signal generator (second gate signal generator)
62 Second pulse transformer 622, 623 Secondary winding S1 PWM signal (pulse width modulation signal)
S2 Rectangular wave signal S3 Inverted rectangular wave signal (inverted rectangular wave signal)
S4, S4 ′ First divided PWM signal (first divided pulse width modulation signal)
S5, S5 ′ Second divided PWM signal (second divided pulse width modulation signal)
S6 Inverted PWM signal (inverted pulse width modulation signal)
S10, S10b Gate signal S11, S12 Pulse signal T Period 70 Heater device 77 Halogen heater 100 Image forming device 101 Controller

Claims (10)

A switching element driving circuit for driving a switching element by a gate signal generated based on a pulse width modulation signal,
Dividing means for dividing the pulse width modulated signal within one period to generate a plurality of divided pulse width modulated signals;
Pulse driving means for respectively driving primary sides of a plurality of independently provided pulse transformers using a plurality of the divided pulse width modulation signals;
Gate signal generating means for combining the pulse signals output from the secondary side of the plurality of pulse transformers to generate the gate signal;
The gate signal generating means includes
A plurality of diodes having one end connected to the secondary side of each pulse transformer in order to perform a logical sum operation of the plurality of pulse signals;
A capacitor for smoothing the gate signal synthesized by smoothing the pulse signal, the other ends of the plurality of diodes being connected to each other,
A switching element driving circuit. As the gate signal generating means, a MOSFET is connected instead of each of the plurality of diodes,
A body diode built in each MOSFET performs the function of the diode,
Controlling the MOSFET to turn on in synchronization with a signal obtained by inverting the pulse width modulation signal;
The switching element driving circuit according to claim 1. Second gate signal generation means is provided for controlling the plurality of MOSFETs,
The second gate signal generation means includes:
A transistor that turns on and off based on the pulse width modulation signal;
A second pulse transformer that is driven by the transistor and includes a plurality of secondary windings that respectively output gate signals for the plurality of MOSFETs.
The switching element driving circuit according to claim 2. The dividing means includes
A rectangular wave oscillator that generates a rectangular wave signal having the same frequency as the pulse width modulation signal and a DUTY ratio of 50 percent;
First modulation means for performing a logical product operation of the pulse width modulation signal and the rectangular wave signal to generate a first divided pulse width modulation signal that is one of the divided pulse width modulation signals;
Second modulation means for generating a second divided pulse width modulation signal that is another one of the divided pulse width modulation signals by performing an AND operation on the pulse width modulation signal and a signal obtained by inverting the rectangular wave signal And comprising
The switching element drive circuit according to claim 1. An extension means for extending the time width of the first divided pulse width modulation signal is provided.
The switching element drive circuit according to claim 4. The rectangular wave signal has the same polarity as the pulse width modulation signal.
The switching element drive circuit according to claim 4 or 5. The primary side and the secondary side of the pulse transformer are electrically insulated,
The dividing means and the pulse driving means provided on the primary side are operated by another power source that is insulated from the power source for the switching element.
The switching element drive circuit according to claim 1. A switching element driving circuit according to any one of claims 1 to 7,
A switching element driven by the switching element drive circuit;
A halogen heater in which power supplied from a power source is controlled by the switching element;
A heater device comprising:   An electrophotographic image forming apparatus comprising the heater device according to claim 8. ON-DUTY of the pulse width modulation signal is controlled to be 100% during warm-up, 50% or more during printing, and 50% or less during standby.
The image forming apparatus according to claim 9.

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