JPH07306245A - Formation of test pattern - Google Patents

Abstract

PURPOSE:To provide a method for forming a test pattern easily at a high speed from an operating condition data of a mounting machine. CONSTITUTION:An LSI tester comprises a logic analyzer 12 for acquiring an operational data of an LSI 21 to be measured, a circuit 13 for converting the operational data into an input pattern, a circuit 15 for receiving an input pattern from a data memory 14 and generating an input pattern for the LSI 21, a circuit 16 setting a power supply voltage threshold value for the LSI 21, a circuit 17 for measuring the terminal current of the LSI 21, a circuit 18 for extracting FAIL information from a current value measured by the current measuring circuit 17, and a memory 19 for storing the FAIL information. The data converting circuit 13 combines an input data and the FAIL information to form a test pattern for the LSI tester.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern creating system, and in particular, creates a predetermined test pattern from the mounting machine itself by referring to the operating state of a mounting machine of a semiconductor integrated circuit (hereinafter referred to as LSI). Regarding the test pattern creation method.

[0002]

2. Description of the Related Art Conventionally, as a first conventional example of this type of test pattern creating method, a terminal waveform of a measuring LSI mounted on a mounting machine is sampled and
It is customary to create a test pattern for inspecting the LSI by using the data obtained by manually adding the input / output information obtained from the creator of the mounting machine using a waveform editor or the like. is there. The quality of the test pattern completed in this test pattern creating method depends on how accurate the input / output information submitted by the creator of the mounting machine is. However, L for measurement
In the case where the SI terminal has a terminal whose input / output state can be switched frequently by software, it is very difficult as a practical matter for the creator of the mounting machine to accurately grasp the input / output information. That is.

As a second conventional example that addresses the above problem, a test pattern creating method has been proposed in which the input / output information is directly extracted from a mounting machine. In this conventional example, a potential difference is set to each of the power supply level and the GND level of the measuring LSI and the mounting machine, the potential difference between the input signal to the LSI and the output signal from the LSI is detected, and the input / output information is extracted. Is the way to do it. FIG. 4 is a partial circuit diagram showing an extracted example of a connecting portion between a measuring LSI and a mounting machine in the conventional example. In FIG. 4, L
Taking the input / output terminal 43 between the SI 41 and the mounter 42 as an example, the power supply voltage VDD of the LSI 41 is set to 4.5V and the GND voltage is set to 0.5V. Further, in the mounting machine 42, the power supply voltage VDD is set to 5 V, and G
The ND voltage is set to 0V. FIG. 5A shows an example of signal waveforms at the input / output terminals 43 of the LSI 41 when the mounting machine 42 is operated by such voltage setting.

In FIG. 4, the LSI is mounted from the mounting machine 42 side.
When a signal is input to the side of 41, the input / output terminal 43
Has a potential level of 5V or 0V. On the other hand, LSI4
When a signal is output from the 1 side to the mounting machine 42, the potential level of the input / output terminal 43 becomes 4.5V or 0.5V. Therefore, during a series of operations, the input / output terminal 4
The signal waveform in 3 is as shown in FIG. In addition, in FIGS. 5A, 5B, and 5C, the timing and the LS from the mounting machine 42 side.
The timing when the signal is input to the I41 side is shown, and the timing is the timing when the signal is output from the LSI 41 side to the mounting machine 42.

When data of the signal waveform at the input / output terminal 43 is sampled by a probe having a threshold value of 2.5 V, as shown in FIG. 5B, at the timing of "1", Data that is "0" at the timing, "1" at the timing, and "0" at the timing is collected as pattern data. At the same time, the signal waveform at the input / output terminal 43 is set to 4.75 V and 0.
With a probe that has two thresholds of 25V and that judges "0" for the level between the two thresholds and "1" for other levels. When the data is collected, as shown in FIG. 5C, the data is “1” at the timings of and, and is “0” at the timing of. Input / output information is extracted by defining "1" and "0" of the data shown in FIG. 5C as an input and an output, respectively. That is, in this conventional example, the data shown in FIG. 5C is the input / output information to be sought.

As a third conventional example, a method of utilizing a signal propagation delay is used to collect signal waveforms at two points on the same wiring and the timing at which the signal waveform change occurs is the LSI side. There is a method of detecting which is on the mounting machine side first and extracting the input / output information. Figure 6
FIG. 4 is a partial conceptual block diagram showing an extracted example of a connecting portion between a measuring LSI and a mounting machine in the conventional example, in which two wirings are provided on the same wiring between the LSI 61 and the mounting machine 62. Two probe points 601 and 602 are set. This probe point 601 and 602
If the signal delay amount at is a measurable amount, it can be left as it is, but if the delay amount is so small that it is difficult to measure, it is possible to measure the timing at which the signal waveform changes. For example, as shown in FIG.
A delay circuit 63 is provided between the two probe points 601 and 602. As the delay circuit 63, it is necessary to use a delay circuit of a level that does not hinder the operation of the mounting machine 62 by inserting and connecting the delay circuit 63. Examples of signal waveforms at the probe points 601 and 602 when the mounting machine 62 is operated in this connection state are shown in FIGS. 7A and 7B, respectively. 7A and 7B, at the timings of and, the change of the signal waveform at the probe point 602 is
A state before the change of the signal waveform at 01 is shown, and at the timings of and, the change of the signal waveform at the probe point 601 is before the change of the signal waveform at the probe point 602. Shows.

As shown in FIG.
When the signal is input to the side of 61, the change of the signal at the probe point 602 is
It occurs before the change in signal at 1. On the other hand, LS
When a signal is output from the I61 side to the mounter 62, the signal change at the probe point 601 occurs before the signal change at the probe point 602. Detect which of the probe points 601 and 602 the change in the signal at these two probe points occurs first, and if the change is detected first at the probe point 601, it is defined as an output. If the change is detected first at the probe point 602, the input / output information is extracted as shown in FIG. 7C by defining the input as input.

In the above-mentioned second and third conventional examples, the mounting machine itself needs to be modified, and the power supply voltage and the GND voltage for the LSI and the mounting machine are
There is a problem that it is necessary to set different voltages to each other. Further, in the third conventional example, in order to measure the timing at which the signal waveform changes, the delay amount between the LSI and the mounting machine is increased, whereby the delay amount is kept at a certain level. If it exceeds, it becomes impossible to maintain the normal operation of the mounting machine, so there is a limit to the countermeasures by the delay amount of the delay circuit, and in order to cope with this, it is very accurate. There is a problem that a timing difference detecting means is required.

As a method other than the first, second and third conventional examples, in the "test pattern automatic generation method" of Japanese Patent Laid-Open No. 64-78331, all the collected data are used for LSI test. To the input pattern of
A method has been proposed in which input / output information is extracted on an SI tester and fed back to an input pattern to create an inspection test pattern. 8 (a), (b), (c)
And (d) are diagrams showing an outline of a conversion process into a test pattern in the fourth conventional example proposed above. In FIG. 8, the input pattern is displayed as “0” or “1” according to its logic, and the output pattern is
Corresponding to the high level, low level and high impedance of the expected value, they are displayed as "H", "L" and "Z", respectively. Further, in the pattern in FIG. 8, the terminals of the LSI are arranged in the horizontal direction, and the arrangement corresponding to the time series is shown in the vertical direction.

First, the mounting machine is operated to collect a pattern 801 of the operating LSI as shown in FIG. This pattern 801 is converted into the input pattern 802 shown in FIG. This pattern 802
Is a pattern formed by converting “H” and “L” in the pattern 801 into “1” and “0”, respectively, as shown in FIG. 8B. Here, it is judged whether or not the high impedance "Z" is correct, and then converted into an output pattern bit by bit. In the pattern 803 shown in FIG. 8C,
The bit “0” of channel 1 of the first pattern is changed from the input pattern (pattern 802) to the output pattern (pattern 8).
It has been returned to "L" in 01). In this state, a test is performed using an LSI tester, and if PASS, the first channel of the first pattern is determined to be an output and is determined as "L", and if FAIL, it is determined to be an input. Then, the pattern of "0" is determined.
By repeating this procedure in the range of the specified pattern of the specified channel,
A desired test pattern for inspection as shown in (d) can be obtained, and input / output information can be extracted.

[0011]

In the above-mentioned conventional test pattern creating method, in the case of the first conventional example, when the input / output information is received from the creator of the mounting machine, it is submitted by the creator. Depending on the accuracy of the input / output information
There is a problem that the quality of the created test pattern is affected, but as a practical matter, it is extremely difficult for the creator to accurately grasp input / output information in pattern units and clock units. In addition, the quality of the test pattern cannot be guaranteed.

Further, in the case of the second conventional example in which the power supply voltage and the GND voltage set in the mounting machine and the LSI are provided and the potential difference is detected to extract the input / output information, the mounting machine is modified. And the need for a highly accurate detector capable of accurately detecting the potential difference, and in the case of the third conventional example, similarly, a mounting machine needs to be modified. In addition, there is a drawback in that a highly accurate detector capable of accurately detecting the delay time is required under the condition that the mounting machine is normally operated.

Further, in the case of the fourth conventional example in which all the collected patterns are converted into input patterns and the input / output information is extracted on the LSI test, the input patterns are converted into output patterns for each pattern. , PASS / FAIL
Since it is necessary to repeat the procedure of determining the input / output information and determining and extracting the input / output information, it takes a very long time to obtain the input / output information of all patterns.

[0014]

A test pattern creating method of the present invention collects operation data at a terminal of the semiconductor device during operation of a mounting machine having a semiconductor device to be measured, and obtains the operation data. In a test pattern creating method for creating an inspection test pattern for an LSI tester for inspecting the semiconductor device for measurement using, operation data at a terminal of the semiconductor device for measurement is acquired, and a predetermined input pattern is obtained. Pattern generation means for generating and holding,
While maintaining normal operation of the semiconductor device to be measured, at least one or more specific terminals designated for current measurement in the semiconductor device, the input current and the output current generated by the drive input of a predetermined input pattern In order to provide a difference between the current values, the power supply voltages V _DD , Hi
gh level input voltage VIH, low level input voltage VI
A voltage including L and the ground potential VG is set to V _DD >VIH> V
By setting the potential level defined by the relationship of IL> VG and sending the voltage to the semiconductor device and the input pattern output from the pattern generation means and applying it to the specific terminal, Measuring the input current and the output current generated at the specific terminal,
An input / output information extraction unit that detects a difference between the input current and the output current, determines PASS / FAIL in the input pattern, extracts predetermined FAIL information, and holds the FAIL information. A test test pattern corresponding to the semiconductor device is created by synthesizing the generated test input pattern and the FAIL information output from the input / output information extraction unit in the pattern generation unit. I am trying.

As the pattern generation means, a logic analyzer for probing a terminal of the semiconductor device under test in an operating state and collecting signal waveform data at the terminal, and an output from the logic analyzer A test data input circuit for converting the data to be input into a test input pattern, and a data memory for sequentially inputting and storing the input pattern output from the data conversion circuit. The input test pattern and the FAIL information output from the input / output information extraction means may be combined in the data conversion circuit to create the inspection test pattern.

As the input / output information extraction means,
An input pattern generation circuit for receiving a test input pattern output from the pattern generation means and outputting a drive input pattern for the specific terminal of the semiconductor device under test in an operating state; Inserted and connected between the generation circuit and a terminal of the LSI tester side directly connected to a specific terminal of the semiconductor device for measurement,
A current measuring circuit for measuring a current value of an input current and an output current generated at a specific terminal of the semiconductor device to be measured by the input pattern for driving, and an input current and an output current output from the current measuring circuit. A FAIL information extraction circuit that receives the current value of F, determines PASS / FAIL in the input pattern by referring to the current value, extracts predetermined FAIL information, and outputs the FAIL information;
A FAIL information memory for inputting and storing FAIL information output from the AIL information extraction circuit, and the FAIL information output from the FAIL information memory is
It may be sent to the input pattern generating means in order to synthesize the test pattern for inspection.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a conceptual block diagram showing a partial system configuration of an essential part of one embodiment of the present invention, which is formed corresponding to a mounting machine including an LSI to be measured. As shown in FIG. 1, the logic analyzer 12, the data conversion circuit 13, the data memory 14, the input pattern generation circuit 15, and the voltage setting circuit 1 are associated with the LSI 21 in the mounting machine 20.
6, a current measuring circuit 17, a FAIL information extracting circuit 18, and a FAIL information memory 19 are provided. Also,
FIG. 2 is a flow chart showing a processing procedure for creating a test pattern in this embodiment, and FIG. 3 is a diagram showing a procedure for acquiring FAIL information between the LSI to be measured 21 and the LSI tester 11 in this embodiment. FIG. 3 is a partial conceptual block diagram showing an extracted connection example of the input / output dual-purpose terminal 36 designated for current measurement, showing an LSI tester 11 including an ammeter 31 and a MOS transistor 3;
An LSI 21 including 4 and 35 is connected via respective input / output terminals 36 and 33. Less than,
The operation of this embodiment will be described with reference to FIGS. 1, 2 and 3.

In the flowchart of FIG. 2, in step 201, the terminals of the LSI 21 mounted on the mounting machine 20 of FIG. 1 are probed, and the logic analyzer 12 collects the waveform data of the LSI 21 during actual operation. To be done. Then step 20
In 2, the waveform data collected by the logic analyzer 12 is input to the data conversion circuit 13,
It is converted into an input pattern used as a test pattern, output, and stored in the data memory 14. In this case, all input patterns corresponding to all terminals of the LSI 21 are generated and stored in the data memory 14. In some cases, the pattern corresponding to the input-only terminal and the input-output only terminal is converted as the input pattern, and the pattern corresponding to the output-only terminal pattern is converted as the output pattern.

In step 203, the test conditions on the LSI tester 11 are set. That is, in the voltage setting circuit 16, the power supply voltage V _DD and the high-level voltages VIH and L are supplied to the LSI 21.
ow level voltage VIL and GND level voltage VG
Is set such that V _DD >VIH>VIL> VG, and the threshold value required for current measurement is set. The above set voltage is the LSI2 to be measured.
It is a necessary condition that 1 is a voltage value within a range in which it normally operates. As an example, in this embodiment, V _DD = 5
V, VIH = 4.5V, VIL = 0.5V, VG = 0V
Shall be set. When the input / output combined terminal in the LSI 21 is in the input state, the input / output combined terminal is in a high impedance state, and almost no current flows through the terminal. Conversely, when the input / output combined terminal is in the output state, a current flows through the output buffer to the input / output combined terminal due to the potential difference between V _DD and VIH or the potential difference between VG and VIL. It becomes a state. The threshold value is set in the voltage setting circuit 17 and supplied to the LSI 21 so that the difference in current in this case can be detected. In the present embodiment, as an example, a threshold value of 10 μA is set as the upper limit and a threshold value of −10 μA is set as the lower limit. In this case, it is necessary to pay sufficient attention to the direction of current when setting the threshold value.

Next, in step 204, the LSI
An input / output terminal to be used for current measurement in 21 is designated. In this case, if it is possible to measure all the input / output terminals by one measurement at the time of measurement, all the input / output terminals may be designated, and the measurement corresponding to all the input / output terminals may be performed. If not possible, the current measurement terminal designation and the current measurement may be repeated several times. In Step 205, the Step 20
3 and the conditions set in step 204, the current is measured in the LSI tester 11 using the test pattern created in step 202. By this current measurement, FAIL information indicating in what pattern FAIL has occurred at the input / output combined terminal designated as the current measurement terminal in step 204 is acquired. In the FAIL information acquisition method in this case, as shown in FIG. 3, the LSI 2 designated by the LSI tester 11 as a current measurement terminal is used.
An input waveform as shown in FIG. 3B is input to the one input / output terminal 36. This input waveform is shown in Figure 3.
As shown in (b), VIH = 4.5V, VIL =
It is 0.5V. When the input / output combined terminal 36 is in the input state, both the MOS transistors 34 and 35 are in the OFF state, and the input / output combined terminal 36 is in the high impedance state. Therefore, no matter what voltage level of VIH or VIL is applied to the input / output combined terminal 36, no current flows in that terminal. On the other hand, when the I / O terminal 36 is in the High level output state,
The MOS transistor 34 is turned on and the MOS transistor 35 is turned off. Therefore, VIH = 4.5V as an input waveform to the input / output terminal 36
Is applied, a current flows from the LSI 21 side to the LSI tester 11 side due to the potential difference between V _DD = 5V and VIH = 4.5V. Also, the input / output terminal 36 is Lo
When in the w level output state, the MOS transistor 3
4 is turned off, and the MOS transistor 35 is turned off.
The state becomes N. As a result, VIL =
When 0.5V is applied, VG = 0V and VIL = 0.5
Due to the potential difference of V, the LSI 2 from the LSI tester 11 side
Current flows to the 1 side. These two kinds of currents are respectively measured by the ammeter 31 (included in the current measuring circuit 17 of FIG. 1). The PASS / FAIL judgment is made in the FAIL information extraction circuit 18 by the ammeter 3
It is determined by detecting the difference between two types of current measurement values according to 1. The threshold value of the current set in the voltage setting circuit 16 is set so that the current measuring circuit 17 can effectively detect the difference in the current value. Similar to the example shown at 203, the thresholds are 10 μA and −1.
It is set as 0 μA, and if the measured current value is 10 μA or less or −10 μA or more, it is determined to be PASS, and otherwise it is determined to be FAIL. By executing the measurement test on the LSI 21 under such condition setting, the FAIL information extraction circuit 18 determines the PASS / FAIL F as described above.
AIL information is obtained, and the FAIL information is input and stored in the FAIL information memory 19.

In step 206, step 20
After completing the processing steps up to 5, it is determined whether there is any other input / output terminal to be measured,
If there are other terminals to be measured, step 20
Returning to step 4, the processing procedure after step 204 is repeatedly executed. If there is no other input / output terminal to be measured in step 206, this measurement ends,
In step 207, the FAIL information output from the FAIL information memory 19 is fed back to the data conversion circuit 13. In the data conversion circuit 13, the mounting machine 2
0 is collected from the LSI 21 and the input pattern generated in the data conversion circuit 13 and the FAIL information are added to combine the test pattern for the LSI 21 with the test pattern.
It is input and stored in the memory 14. After the inspection test pattern is created, it is confirmed that it is possible to determine the quality of the LSI operation in the LSI tester, and then the inspection test pattern is first completed as a desired inspection test pattern.

That is, in the present invention, the LS to be measured is
In order to secure the normal operation state of I21 and to provide a difference between the input current and the output current at the I / O terminal, the power supply voltage V _DD and the high-level voltage VIH,
Low level voltage VIL and GND level voltage V
The voltage including G is set by the voltage setting circuit 16 and the LSI
The FAIL information extraction circuit 18 is supplied to the FAIL information extraction circuit 18 by measuring the current flowing through the I / O terminal with the input pattern supplied to the LSI 21 through the I / O terminal designated for current measurement. FAIL information is extracted at
By returning the L information to the data conversion circuit 13 and synthesizing it with the input pattern, the test for inspection can be carried out without depending on manpower and without needing to modify the mounting machine or use a highly accurate detector. It is possible to create a pattern, and it is possible to significantly reduce the time required to create the test pattern for inspection. For example, in the fourth conventional example proposed in Japanese Patent Laid-Open No. 64-78331, it is desirable to determine PASS / FAIL while determining input / output while switching input / output for each pattern. It takes a very long time to acquire the test pattern. As an example, consider a case where data is collected during 1 second of operation of the mounting machine to create a test pattern. In this case, assuming that there are 100 test patterns, the input pattern is converted into an output pattern for each pattern and the PASS / F
The procedure of determining the input / output by performing AIL judgment is 1
It is necessary to repeat it 00 times. Therefore, in order to obtain a desired test pattern, 1 sec × 100 = 1
It takes a time of 00 sec.

That is, although the timing at which input / output switching is performed in the semiconductor device under test itself is unknown in the entire series of patterns, even in this state, in the fourth conventional example, Since the logic test is used, it is still necessary to switch the input / output of only one pattern for each pattern and determine PASS / FAIL by the logic test of only the one pattern.
Therefore, in the conventional example, it is necessary to repeat the same test for each of the one pattern included in all the patterns, and as described above, PA is applied to all the patterns.
It takes a lot of time to determine SS / FAIL and obtain a desired test pattern by this.

However, in the present invention, the LSI tester is provided with means capable of measuring a current for each input / output terminal of the semiconductor device to be measured,
Tests can be performed without any switching operation for each pattern.
By applying the test pattern only once and measuring the corresponding current, it is possible to obtain the test pattern corresponding to all the patterns within an extremely short time. For example, when citing the numerical examples used in the above-mentioned fourth conventional example, in the present invention, 100s according to the conventional example is cited.
It becomes possible to acquire a desired test pattern in 1 second as compared with the time required for ec.

[0026]

As described above, according to the present invention, the power supply voltage V _DD and the voltage at the high level are set in order that the LSI to be measured operates normally and the difference between the input current and the output current is provided. VIH, Low level voltage VIL and GN
The voltage including the voltage VG of the D level is set by the voltage setting circuit and supplied to the LSI, and the current flowing through the I / O terminal by the input pattern applied to the LSI through the I / O terminal designated for current measurement. Is measured by a current measuring circuit, and the difference in the current value of the current is detected, so that the FAIL information extracted by the FAIL information extracting circuit is fed back to the data converting circuit and combined with the input pattern in the data converting circuit. By doing so, it is possible to create a test pattern for inspection without depending on manpower, and without the need to modify the mounting machine or use a high-precision detector. In addition, there is an effect that a test pattern for inspection can be created.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a flow chart of test pattern creation in the embodiment.

FIG. 3 is a partial block diagram between the LSI / LSI tester of the embodiment.

FIG. 4 is a partial block diagram between an LSI / mounting machine of a second conventional example.

FIG. 5 is a diagram showing waveforms at an input / output terminal between the LSI and the mounting machine of the second conventional example.

FIG. 6 is a partial block diagram between an LSI / mounting machine of a third conventional example.

FIG. 7 is a diagram showing waveforms at an input / output terminal between the LSI / mounting machine of the third conventional example.

FIG. 8 is a diagram showing a process of converting into a test pattern of a fourth conventional example.

[Explanation of symbols]

11 LSI Tester 12 Logic Analyzer 13 Data Conversion Circuit 14 Data Memory 15 Input Pattern Generation Circuit 16 Voltage Setting Circuit 17 Current Measurement Circuit 18 FAIL Information Extraction Circuit 19 FAIL Information Memory 20, 42, 62 Mounting Machine 21, 41, 61 LSI 31 Ammeter 32 Output buffer 33, 36, 43, 64, 65 Input / output terminals 34, 35, 44 to 47 MOS transistor 63 Delay circuit 201 "Sucking up operation pattern of mounting machine" Step 202 "Conversion of all pattern input patterns" Step 203 "Set test conditions on LSI tester" Step 204 "Specify current measurement terminal (input / output terminal)"
Step 205 “Test → Acquisition of FAIL information” Step 206 “Are there other terminals to measure?” Step 207 “Composition of test pattern for inspection by FAIL information and input pattern” Step

Claims (3)

[Claims] 1. An LSI tester for collecting operation data at a terminal of the semiconductor device during operation of a mounting machine having the semiconductor device under test, and inspecting the semiconductor device under test using the operation data. In a test pattern creating method for creating a test pattern for inspection, a pattern generating means for acquiring operation data at a terminal of the semiconductor device to be measured and generating and retaining a predetermined input pattern, In addition to maintaining normal operation of the semiconductor device for use in the semiconductor device, at least one or more specific terminals designated for current measurement in the semiconductor device have a current value of an input current and an output current generated by driving input of a predetermined input pattern. In order to make a difference, the power supply voltages V _DD , Hi
gh level input voltage VIH, low level input voltage VI
A voltage including L and the ground potential VG is set to V _DD >VIH> V
By setting the potential level defined by the relationship of IL> VG and sending it to the semiconductor device, and receiving the input pattern output from the pattern generation means and applying it to the specific terminal, The input current and the output current generated at the specific terminal are measured, and the difference between these input current and output current is detected,
Input / output information extraction means for judging PASS / FAIL in the input pattern and extracting and holding predetermined FAIL information, and a test input pattern generated by the pattern generation means, and the input / output information A test pattern creating method characterized in that an inspection test pattern corresponding to the semiconductor device is created by synthesizing the FAIL information output from the extracting means with the pattern creating means. 2. A logic analyzer for probing a terminal of a semiconductor device under test in an operating state and collecting signal waveform data at the terminal, the pattern generating means outputting the signal from the logic analyzer. Data conversion circuit for converting the data to be input into a test input pattern, and a data memory for sequentially inputting and storing the input pattern output from the data conversion circuit. 2. The test pattern creation according to claim 1, wherein said test pattern is created by synthesizing the input pattern for the test and the FAIL information output from said input / output information extraction means in said data conversion circuit. Method. 3. The input / output information extraction means receives a test input pattern output from the pattern generation means, and receives a drive input for the specific terminal of the semiconductor device under test in an operating state. An input pattern generating circuit that outputs a pattern, an input pattern generating circuit, and an input for driving that are inserted and connected between a terminal on the LSI tester side that is directly connected to a specific terminal of the semiconductor device under test. A pattern is used to receive a current measuring circuit that measures the input current and the output current value generated at a specific terminal of the semiconductor device to be measured, and the input current and the output current value output from the current measuring circuit. Then, referring to the current value, PASS / FAIL in the input pattern is determined, and predetermined FAIL information is extracted and output. An information extraction circuit; and a FAIL information memory for receiving and storing the FAIL information output from the FAIL information extraction circuit. The FAIL information output from the FAIL information memory is used as the inspection test pattern. 2. The test pattern creating method according to claim 1, wherein the test pattern creating means outputs the test pattern to the input pattern creating means.