JPH0730552A - Atm switch overload test equipment - Google Patents

Abstract

PURPOSE:To make the size of the hardware scale small by copying a primitive load cell generated from a primitive load cell generating circuit by input port number of a tested ATM switch and giving routing information to the header so as to form a load cell. CONSTITUTION:A primitive load cell generating circuit 1 generates a primitive load cell 6 as a test cell and a copy circuit 2 copies the primitive load cell 6 corresponding to an input port of an ATM switch 5. Then a routing load circuit 3 designates the share destination to the ATM switch in the unit of input ports for the primitive load cell 6 to provide an output of a load cell 7 with header information given thereto to the ATM switch 5. Then an output timing of the load cell 7 outputted from the ATM excess load test control voltage 4 is set by a test cell generation control section 8 based on test pattern information 9. The control section 8 sets the frequency of occurrence of the primitive load cell 6 generated by the circuit 1, number of outputs from the copy circuit 3 and content of header information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in an ATM (asynchronous transfer mode) switch. In particular, the present invention relates to a load cell generation circuit that enables verification of operation at the time of overload input of an exchange in an exchange having a built-in ATM switch having a cell distribution function.

[0002]

2. Description of the Related Art A conventional example will be described with reference to FIG. Figure 2
FIG. 7 is a block diagram of a conventional device. In the conventional ATM switch overload test apparatus 4, in order to input load cells to all necessary input ports, it is necessary to connect independent load cell generation circuits 5 _{1 to} 5 _n as many as the number of input ports of the exchange. There is.

[0003]

SUMMARY OF THE INVENTION In such a system,
Since the load cell generation circuits for the input ports of the exchange are connected, a plurality of load cell generation circuits are required, the amount of hardware increases, and the device price increases.

The present invention has been made against such a background, and the AT of an exchange is configured by a small hardware configuration.
It is an object of the present invention to provide an ATM switch overload test device capable of verifying the operation when an M switch overload is input.

[0005]

SUMMARY OF THE INVENTION The present invention is an ATM switch overload test apparatus having means for providing test load cells to the input ports of an ATM switch having a plurality of input ports.

Here, the feature of the present invention lies in a primitive load cell generating means for generating at least one primitive load cell containing no header information in time series, and the primitive load cell generating means. Means for copying the original load cells to at least the number corresponding to the input port, and means for adding header information to the original load cells copied by the copying means to make the load cells. is there. The header information preferably includes routing information.

It is desirable to provide means for selectively controlling the frequency of occurrence of the primitive load cell generating means, the number of outputs of the copying means, and the contents of the header information according to a preset pattern.

[0008]

In the primitive load cell generating circuit, at least one primitive load cell is generated. The original load cells are copied in the copy circuit by the number of input ports of the ATM switch under test. Further, destination information for performing an overload test is added to the headers of the plurality of primitive load cells. An overload test of the ATM switch is performed using the test load cell thus generated.

As a result, with a small hardware configuration,
A TM switch overload test device can be realized.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

The present invention is an AT having a plurality of input ports.
The ATM switch overload test apparatus 4 is provided with means for providing test load cells 7 corresponding to the input ports of the M switch 5.

Here, the feature of the present invention lies in a primitive load cell generating circuit 1 for generating at least one primitive load cell 6 containing no header information in time series, and the primitive load cell generating circuit 1. As a means for copying the primitive load cells 6 generated by the above into at least a number corresponding to the input port, a copy circuit 2 is provided, and the primitive load cells 6 copied by the copy circuit 2 are provided with header information including routing information. The routing information adding circuit 3 is provided as a means for converting the load cell 7 into a load cell 7.

The primitive load cell 6 of the primitive load cell generating circuit 1
The test cell generation controller 8 is provided as a means for selectively controlling the frequency of occurrence of data, the number of outputs of the copy circuit 2, and the content of the header information according to a preset pattern. The test cell generation control unit 8 controls the primitive load cell generation circuit 1, the copy circuit 2, and the routing information addition circuit 3 by the test pattern information 9 provided from the outside.

Next, the operation of the apparatus of the present invention will be described. The primitive load cell generation circuit 1 generates a primitive load cell 6 as a test cell, and the copy circuit 2 copies the primitive load cell 6 corresponding to the input port of the ATM switch 5.

The primitive load cells 6 copied by the routing information adding circuit 3 are assigned to the ATM switch 5 in units of input ports, and the load cells 7 to which header information is added are output to the ATM switch 5.

The output timing of the load cell 7 output from the ATM switch overload test circuit 4 is set by the test cell generation controller 8 based on the test pattern information 9. The test cell generation control unit 8 sets the generation frequency of the primitive load cells 6 generated in the primitive load cell generation circuit 1, the number of outputs of the copy circuit 2, and the content of the header information by the test pattern information 9.

[0017]

As described above, according to the present invention, A
Compared with the conventional device that needs to prepare independent load cell generation circuits for the input ports of the TM switch, the device cost can be reduced because the device can be configured with a small amount of hardware by means of copying the primitive load cells. Wear scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional device.

[Explanation of symbols]

1 primitive load cell generating circuit 2 copies circuit 3 routing information addition circuit 4 ATM switch overload test device 5 ATM switches 5 ₁ to 5 _n load cell generating circuit 6 primitive load cell 7 Load cell 8 test cell generator controller 9 test patterns Information 11 signal line

 ─────────────────────────────────────────────────── ─── Continuation of front page (71) Applicant 000005223 Fujitsu Limited 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa (72) Inventor, Kyoo Hamakawa 5-7-1, Shiba, Minato-ku, Tokyo Within the NEC Corporation (72) Inventor Koji Suzuki, 5-7-1, Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor ▲ Takashi Yasushi 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation In-house (72) Inventor Hitoshi Ojima 4-6 Kanda Surugadai, Chiyoda-ku, Tokyo Inside Hitachi, Ltd. (72) Inventor Yasushi Okamoto 1-7-12 Toranomon, Minato-ku, Tokyo Inside Oki Electric Industry Co., Ltd. (72 ) Inventor Hitoshi Katakura 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (3)

[Claims] 1. An ATM switch overload test apparatus equipped with means for providing test load cells corresponding to input ports of an ATM switch having a plurality of input ports, wherein the primitive load cells not including header information are time-series. To generate at least one of the original load cells, a means for copying the primitive load cells generated by the primitive load cell generating means to at least a number corresponding to the input port, and a means for copying by the copying means. An ATM switch overload test device, comprising means for adding header information to each of the primitive load cells to make the load cells. 2. The ATM switch overload test apparatus according to claim 1, wherein the header information includes routing information. 3. The frequency of occurrence of the primitive load cell generating means,
2. An ATM switch overload test apparatus according to claim 1, further comprising means for selectively controlling the number of outputs of the copying means and the content of the header information according to a preset pattern.