KR100206191B1 - Router using cell delay priority - Google Patents

Abstract

The present invention relates to an asynchronous transfer mode (ATM) cell input to a plurality of input terminals, a CDP (Cell Delay Priority) scanner, Routing addressing means for generating a serial address for a corresponding ATM cell by means of a CDP signal (READ_PORT); And routing means for switching the crossbar by searching for an output terminal using the address generated by the routing address means. When various types of services are performed by the ATM method, the service quality of the network is controlled by controlling the network according to the delay characteristics of the service. There is an effect that can be guaranteed.

Description

Router using Cell Delay Priority

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a router using a cell delay priority (CDP), and more particularly, to an asynchronous transfer mode (ATM) cell input to a plurality of input terminals, The present invention relates to a router for crossbar switching a corresponding ATM cell to a plurality of output terminals using CDP detected by a scanner.

Since the ATM system must support various kinds of services such as low-speed voice and data, high-speed image, image, and image data, the parameters of the network must be controlled to match the characteristics of each service.

Voice data and video data having constant bit rate (CBT) characteristics are very sensitive to delay, while plain text or electronic mail data having a variable bit rate (VBR) The case is less sensitive to delay.

It is very important to set the appropriate parity for these services to ensure the quality of service of the network, and one of these parities is the cell delay priority.

An ATM cell with a CDP of 0 is a very severe voice or video data delay and this data should be considered to be preferentially routed when switching networks compared to text or e-mail data that is less sensitive to CDP 1 delay.

Therefore, according to the present invention, the value of the corresponding CDP bit is observed for ATM cells received from a plurality of input terminals, the feedback cell is determined according to the cell output request to the same output terminal in priority routing according to the CDP state, serial) data crossbar switch for the purpose of providing a router.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall configuration diagram of a router according to the present invention;

2 is a detailed block diagram of a unit address generator according to the present invention;

3 is a detailed block diagram of a unit router according to the present invention;

4 is a timing diagram showing a simulation result at the time of routing request from input 0 to output 0, input 1 to output 1, input 2 to output 3, and input 3 to output 3.

5 is a timing diagram showing a simulation result at the time of requesting routing from the input terminal 0 to the output terminal 1, the input terminal 1 to the output terminal 0, the input terminal 2 to the output terminal 3, and the input terminal 3 to the output terminal 2.

6 is a timing diagram showing a result of a simulation when input 0 is output 3, input 1 is output 0, input 2 is output 1, and input 3 is output 2.

FIG. 7 is a timing diagram showing a simulation result when a routing request is made from an input end 0 to an output end 1, an input end 1 to an output end 2, an input end 2 to an output end 3,

DESCRIPTION OF THE REFERENCE NUMERALS

I100: routing address means I200: routing means

I300: Routing control signal generating means I400: Multiplexing means

10, 12, 14, 16: unit address generators 11, 13, 15, 17:

20: counters 22 and 23: MUX,

24, 25, 30, 31, 32, 36: flip-flops 33, 34, 35: multiplexer

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings, in which four input terminals and four output terminals are provided.

Fig. 1 is an overall configuration diagram of a router according to the present invention, wherein I100 is a routing address means and I200 is a routing means. The routing address means I100 is composed of four unit address generators, and the routing means I200 is composed of four unit routers.

The unit address generators 10, 12, 14 and 16 generate a serial address for the corresponding ATM cell by means of a CDP signal (READ_PORT) outputted through the CDP scanner for the ATM cell received through each input terminal.

The unit routers 11, 13, 15, and 17 search for an output terminal using the address generated by the routing address means, and perform crossbar switching.

2 is a detailed block diagram of a unit address generator according to the present invention.

With reference to Figure 2, the unit address generator comprises a counter 20 for counting the number of inputs (2 ² ) during the actual routing decision period of the CDP scanner when n = 2 and outputting the signal, A first input terminal is connected to the second output terminal of the counter 20, a second input terminal is grounded, and a first MUX (first input terminal) and a second input terminal 22); The first input terminal is connected to its own output terminal. The second input terminal is connected to the output terminal of the first mux. The first input terminal is connected to the first flip- (24); A first input terminal is connected to a first output terminal of the counter, a second input terminal is connected to an output terminal of the first flip-flop, and a second mux (23); The second input terminal is connected to the output terminal of the second mux. The second input terminal is connected to the output terminal of the second mux. The second input terminal is connected to the output terminal of the second mux, Flop 25; And an AND gate 26 for generating a routing address signal ROUT_ADD by logically multiplying the output signal of the second flip-flop and the ROUT control signal.

And outputs the output 2 bits (QA, QB) first by turning the binary counter 20 as many as the number of terminals during REAL_FB, which is the actual routing decision period of the CDP scanner.

The output of the counter 20 is connected to the first flip-flop 24 and the second flip-flop 24 through the first and second muxes 22 and 23 while the ROUT signal is disabled when the READ_PORT signal is generated. (25) and generates PORT_ADD, which is the serial routing address of the output to the input while the ROUT signal is disabled.

The first and second flip-flops output a value input to the T1 terminal if the value input to the TE terminal is 1, and a value input to the D terminal when the value input to the TE terminal is 0.

The detection and judgment of the READ_PORT signal for the input terminal in the CDP scanner detects the PORT_READ signal for the output terminal with two conditions of the destination of the terminal and the cell delay priority (CDP), but is not shown in the present invention .

3 is a detailed block diagram of a unit router according to the present invention.

Referring to FIG. 3, the unit router latches the routing address signal ROUT_ADD output through the unit address generator by an ALIGN control signal input from the outside, and generates routing control signals ROUT_0 and ROUT_1 A routing control signal generation means for generating a routing control signal; Multiplexing means for selectively outputting an ATM cell of an input terminal corresponding to each output terminal by a routing control signal output by the routing control signal generating means; And a third flip-flop for latching a signal output through the multiplexing means.

The routing control signal generating means includes: a fourth flip-flop for latching the routing address signal ROUT_ADD; The first input terminal receives the routing address signal PORT_ADD, the second input terminal receives the routing address signal PORT_ADD, selects the signals of the two input terminals by the ALIGN control signal, and outputs the signals to the first routing control signal ROUT_1 A fifth flip flop; The second input terminal is connected to the output terminal of the fourth flip flop. The second input terminal is connected to the output terminal of the fourth flip flop. And a sixth flip-flop for outputting the second flip-flop.

The multiplexing means receives the first ATM cell through the first input terminal and the second ATM cell through the second input terminal among the four ATM cells input in parallel through the four input terminals, A third mux for selectively outputting signals at two input terminals by the routing control signal ROUT_0; A fourth mux receiving a third ATM cell through a first input, receiving a fourth ATM cell through a second input, and selectively outputting signals at two input terminals by the first routing control signal ROUT_1; And receives the output of the third multiplexer through the first input terminal, receives the output of the fourth multiplexer through the second input terminal, selectively outputs the signals of the two input terminals by the first routing control signal ROUT_1 And outputting the fifth mux.

And generates the routing control signals ROUT_0 and ROUT_1 by latching the serial address signal PORT_ADD of the output stage generated by the routing address means in Fig. 1 with an enable signal ALIGN for routing. By controlling the muxes 33, 34, and 35 using these two signals, IN3: 0, which is the serial data of the input terminal, is selected from the output terminal to output the serial data output PORT (0-3). When the input terminal A has the address of the output terminal B, when the data from the input terminal A is read from the output terminal B, the routing from A to B is performed.

4 is a timing diagram showing a simulation result when a routing request is made from an input terminal 0 to an output terminal 0, an input terminal 1 to an output terminal 1, an input terminal 2 to an output terminal 2, and an input terminal 3 to an output terminal 3.

At this time, the input data DI [3: 0] was set as DI [0] to 00000_1100_1100_1100, DI [1] to 10000_0110_0110_0110, DI [2] to 01000_0011_0011_0011 and DI [3] to 11000_1001_1001_1001.

5 is a timing diagram showing a simulation result when the input terminal 0 is at the output terminal 1, the input terminal 1 is at the output terminal 0, the input terminal 2 is at the output terminal 3, and the input terminal 3 is at the output terminal 2.

FIG. 6 is a timing diagram showing a simulation result when the input terminal 0 is the output terminal 3, the input terminal 1 is the output terminal 0, the input terminal 2 is the output terminal 1, and the input terminal 3 is the output terminal 2.

FIG. 7 is a timing diagram showing a simulation result when a routing request is made from an input end 0 to an output end 1, an input end 1 to an output end 2, an input end 2 to an output end 3, and an input end 3 to an output end 0. FIG.

According to the present invention, when various kinds of services are performed by the ATM scheme, the service quality of the network can be guaranteed by controlling the network according to the delay characteristics of the service. That is, according to the present invention, it is possible to ensure quality of service by routing voice or video data, which is very sensitive to signal delay, to text data or e-mail data, which is less sensitive to signal delay, when routing the network.

Claims (5)

( ²ⁿ ) output terminals using the CDP signal detected by a cell delay priority (CDP) scanner for a plurality of ( ²ⁿ ) input ATM cells as crossbars and a unit address generator for generating a serial address for the corresponding ATM cell by the CDP signal READ_PORT. The unit address generator includes a plurality of unit address generators 10, 12, 14 and 16, Routing unit for generating an address and n unit routers 11, 13, 15 and 17, and the unit router is a routing unit for searching for an output terminal using the address generated by the routing address unit, Wherein the router is a CDP router. 2. The apparatus of claim 1, wherein said unit address generator comprises: counter means for counting the number of input stages (2 ² ) during the actual routing decision period of the CDP scanner when n = 2 and outputting the signal; A first input terminal connected to the output terminal, a second input terminal grounded, and a first MUX for selectively outputting signals of two input terminals by an ROUT control signal input from the outside, a first input terminal connected to an output terminal of the first input terminal, A second input terminal connected to an output terminal of the first mux and selectively outputting signals of two input terminals according to the ROUT control signal or the READ_PORT signal, The second input terminal is connected to the output terminal of the first flip-flop, and the signal of the two input terminals is selectively outputted by the ROUT control signal. The second input terminal is connected to the output terminal of the second mux and selectively outputs signals of the two input terminals according to the ROUT control signal or the READ_PORT signal. A second flip-flop for outputting the second flip-flop; And an AND gate for generating a routing address signal ROUT_ADD by logically multiplying the output signal of the second flip-flop by the ROUT control signal. The unit router according to claim 1, wherein, when n = 2, the unit router latches the routing address signal ROUT_ADD output through the unit address generator by an ALIGN control signal input from the outside, Routing control signal generating means for generating routing control signals ROUT_0 and ROUT_1 and routing control signals outputted by the routing control signal generating means to selectively output the ATM cells of the input stage corresponding to the respective output stages And a third flip-flop for latching a signal output through the multiplexing means. 4. The circuit of claim 3, wherein the routing control signal generating means comprises: a fourth flip-flop for latching the routing address signal ROUT_ADD; a first input coupled to an output of the fourth flipflop; A fifth flip-flop for receiving signals of two input terminals according to the ALIGN control signal and outputting the signals to the first routing control signal ROUT_1, and a second input terminal connected to the output terminal of the fifth flip- And a sixth flip-flop connected to an output terminal of the fourth flip-flop, for selecting signals of two input terminals by the ALIGN control signal and outputting the signals to the second routing control signal ROUT_0. router. [4] The apparatus of claim 3, wherein the multiplexing unit receives the first ATM cell through the first input terminal and the second ATM cell through the second input terminal among the four ATM cells input in parallel through the four input terminals, The third and fourth ATM cells, which selectively output signals at two input ends by the second routing control signal ROUT_0, are received through a first input terminal, the fourth ATM cell is received through a second input terminal, And receives the outputs of the fourth mux and the third mux selectively outputting the signals of the two input ends by a first routing control signal ROUT_1 through the first input terminal and outputs the output of the fourth mux to the second input terminal, And a fifth mux for selectively receiving signals at two input ends by the first routing control signal ROUT_1.