KR100190853B1 - A switching apparatus of multicasting prerouter for atm - Google Patents

Abstract

The present invention relates to a switching device of an ATM pre-router network that matches the flow of a destination address of an ATM cell with a cell flow in a cell router network through which the cell is transmitted. The first to sixth input ports (L0, L1) The first and second lower address signals ILP2N and IPL2N + 1, the first and second higher address signals IUP2N, IUP2N + 1, and the first and second lower address signals IO, U1, S0, and S1, respectively. And routing signal generation circuit for generating first and second routing control signals G0, G1 in response to second valid address indication signals ISP2N, ISP2N + 1, where N is zero or a positive integer. And a signal selection circuit for selectively outputting the valid address display signals, the lower address signals, and the upper address signals by a logical combination of the lower address signals, the upper address signals, the effective address display signals, and the routing bit ( 200 and latch outputs of signal selection circuit 200 And output circuits 300 output through the first through sixth output ports OL0, OL1, OU0, OU1, OS0 and OS1, respectively.

Description

[Name of invention]

Switching device of multicast prerouter for asynchronous transmission

(A Switching Apparatus of Multicasting Prerouter for Asynchronous Transfer Mode)

[Brief Description of Drawings]

1A and 1B are diagrams showing modes of a 2x2 unit switching device for unicast communication in an asynchronous transmission cell router network.

2A to 2D are diagrams showing modes of a 2x2 unit switching device for multicast communication in an asynchronous transmission cell router network.

3 is a diagram illustrating a switching network of a prerouter for asynchronous transmission multicast communication to which the present invention is applied.

4 is a partially enlarged view of FIG.

5 is a preferred embodiment of a unit switching device for multicast communication of an asynchronous transmission praroter according to the present invention.

6 is a preferred embodiment of a routing signal generation circuit.

* Explanation of symbols for main parts of the drawings

100: routing signal generation circuit 110,130: routing signal generation unit

120,140: latch portion 200: signal selection circuit

300: output circuit

Detailed description of the invention

(Industrial use)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching network that supports Asynchronous Transfer Mode (ATM). In particular, the present invention relates to a flow of a destination address for allowing an ATM cell to reach a destination. The present invention relates to a switching device of a prerouter network for matching a cell flow in a cell router network.

(Explanation of the prior art)

In recent years, multimedia such as personal computers has advanced significantly. On the same screen, transmission media such as data, facsimile documents, video and audio can be displayed simultaneously. The communication provided by individual lines like the data transmission service and the video service so far cannot be supported by multimedia communication. In order to transmit various kinds of information from the same terminal, high-speed and broadband transmission such as 150Mbps or 600Mbps is required. As a result, technology development and construction of the broadband aspects of Integrated Service Digital Network (B-ISDN) are becoming more active. B-ISDN is based on a transmission technology called asynchronous transmission (ATM).

This ATM is a state-of-the-art communication system that can process all information such as voice, data and video in real time. In this system, fixed length (53 bytes) obtained by dividing digital information into 48 byte units (usually called 'payload') and adding 5 bytes of control information called a header to each of them. Transmit the cell of. The header contains a flow control signal, error correction code, priority and destination address.

The transmission of the header with information is similar to that of packet switching, but different from that of packet switching. In other words, the packet switched scheme differs from the packet switched scheme in accordance with various services. In other words, in a packet-switched system, the length of a packet is variable according to various services, but in ATM, the length of a cell is constant. As described above, in ATM, all information is sent in the form of a cell of fixed length, and thus the information is easily handled, and since the receiver side is known from the header portion of the cell, fast connection and transmission by hardware are possible. In addition, a valid cell may be transmitted only when information is to be sent, and nothing may be transmitted when it is unnecessary. In practice, however, it is filled with dummy cells on the transmission path. Since these empty cells are discarded in a network, this is a far cry from the circuit switching method, which requires the circuit to be retained even without information. This is why it is an asynchronous transmission method.

ATM supports point-to-multipoint, or rtcast, communication as well as point-to-point, or unicast, communication. In this case, multicast refers to replicating a cell according to the information of its header and transmitting it to various desired destinations. According to this multicast communication, not only stereoscopic video conference. Various multimedia services such as an image database (eg, an electronic art gallery, an electronic library, fashion information), a video on demand (VOD), etc. are enabled.

On the other hand, in ATM communication, it is an ATM leveling network that performs a function of allowing a cell to reach its destination using a destination address in a header of a cell, which is a cell router switching network and a free router switching network. Distinguished by a network.

1A and 1B show a mode of a 2 × 2 unit switching device of a cell router network (not shown) for unicast communication. 1A and 1B, the signal MS provided to the control terminal of the switching device is a mode selection signal for selecting the mode of the switching device. Since the transmission path of certain information is assigned by this signal MS, this signal MS is commonly called a 'routing bir signal' or 'routing control signal'. FIG. 1A shows ATM cells input to two input ports IN0 and IN1 when the routing bit MS is '0', for example, through two output ports OUT0 and OUT1 corresponding to the respective input ports. Pass mode for each output as it is, and FIG. 1B shows cells input to the first input port IN0 when the routing bit MS is '1', for example, through the second output port OUT1. Cells input to the second input port IN1 indicate a cross mode that is output through the first output port OUT0.

2A to 2D show modes of a 2 × 2 unit switching device of a cell router network capable of supporting multicast communication. 2A shows a first copy outputting a cell input to the first input port IN0 through two output ports OUT0 and OUT1 when the routing control signals G0 and G1 are, for example, (0,0). (copy) mode is displayed. FIG. 2D shows the cross mode, respectively, when the routing control signals G0, G1 are (0, 1), for example. 2B is a second copy mode in which a routing control signal outputs a cell input to the second input port IN1 through two output ports OUT0 and OUT1 when (G0, G1) is (1,1), for example. Is displayed.

[Purpose of invention]

It is an object of the present invention to provide a switching device of a prerouter for supporting multicast communication of ATM.

[Configuration of Invention]

The unit switching device of the ATM pre-router network which matches the flow of destination addresses of ATM cells with the cell flow in the cell router network in which the cells are transmitted is the cell router network to which two transmitted cells are copied and output. Lower address signals respectively indicating the ports of the lowest addresses among the output ports of and upper address signals indicating the ports of the highest addresses among the output ports to which the copied cells are respectively output, and indicating whether the lower and upper addresses are valid. First to sixth input ports to which valid address display signals are respectively input, first to sixth output ports for outputting the lower address signals, the upper address signals, and the valid address display signals, respectively; The lower address signals and the upper address signal Routing signal generating means for generating first and second routing control signals for controlling switching of the cell router network in response to the valid address indication signal from the sixth input port; and in response to the routing control signals; Signal selecting means for selectively outputting the valid address display signals, the lower address signals, and the upper address signals corresponding to the first to sixth output ports, and latching the outputs of the signal selecting means. And output means for outputting the latched signals through the first to sixth output ports as the lower address signals, the upper address signals, and the valid address display signals, respectively.

In the switching device, the routing signal generating means comprises: a first routing signal generation unit configured to logically combine the lower address signals and the valid address indication signal from the sixth input port to generate the first routing control signal; And a first latch unit for selectively latching an output of the first routing signal generator and its own output in response to a latch enable signal provided from the outside, and the upper address signals and the sixth input port from the first latch unit. A second routing signal generator configured to logically combine an effective address indication signal to generate the second routing control signal, and selectively latching an output of the second routing signal generator and its output in response to the latch enable signal It includes a second latch portion.

In another aspect, the switching device of the ATM router for a router according to the present invention; A plurality of unit switching devices forming a 2 ^{m by} 2 ^m inverse-venion network, where m is an integer greater than 3; First through sixth input ports to which lower address signals, upper address signals, and effective address display signals are respectively input; the valid address indication signal, lower address signals, and upper address signals from the sixth input port; Routing signal generating means for generating first and second routing control signals in response to the valid address by logically combining the lower address signals, the upper address signals, the valid address indication signals, and the routing control signals; Signal selecting means for selectively outputting display signals and the lower address signals and the upper address signals; and latching the outputs of the signal selecting means and latching the latched signals through the first to sixth output ports. And the upper address signals and the valid Including output means for each output as dress display signal; The routing control signals generated by each of the plurality of unit switching devices are provided to a unit switching device of the cell router network corresponding to each unit switching device.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(Example)

3 shows an example of a pre-router switching network for ATM multicast communication to which the present invention is applied, and has a 16 × 16 switching network having 16 input / output ports for each of three signals (ILP, IUP, and ISP). Is showing. 4 is an enlarged view of a portion of FIG. 3. Referring to FIG. 3, this switching network is a reverse Banyan network consisting of four stages (STGI to STG4). Each end of the network contains eight 2 x 2 unit switching devices 1 for multicast communication. In each stage, the input signals are switched bit by bit, respectively, by the unit switching devices 1. At this time, each unit switching device 1 performs the switching and generates routing control signals G0 and G1 for switching in the cell routing network (this cell routing network also has an inverse-Benian network structure). In each stage, the first routing control signal G0 and the second routing control signal G1 generated by each unit switching device 1 together with the corresponding routing control signals generated by the other switching devices in that stage. Two 8-bit routing signals (eg, G0STG1 and G1STG1 in the first stage) are formed, respectively. Routing signals G0STG1 and G1STG1, G0STG2 and G1STG2, and G0STG3 and G1STG3 and G0STG4 and G1STG4 respectively generated in the first to fourth stages of the prerouter switching network are corresponding to those of the cell router switching network. Each of the first to fourth stages (not shown) is provided. The first to fourth stages STG1 to STG4 latch signals provided to their input ports by latch enable signals RET1, RET2, RET3, and RET4 provided from the outside.

In order for a cell to be multicasted, it is necessary to identify that the cell is subject to multicasting. Information for identification thereof is given from a control block (not shown) of the ATM switching network. The control block decodes the destination address of the header to generate mode identification signals, and provides them to the prerouter switching network of FIG. In FIG. 3, the ILP15: 0, IPU15: 0, and ISP15: 0 signals coming into the input terminal are the mode identification signals described above. These signals contain information indicating the cell's destination port and whether it is multicasting. In FIGS. 3 and 4, n: 0 represents the number of bits (n + 1) of the signal transmission bus, and n represents the number of each transmission line or port of the bus. For example, ILP15: 0 denotes a 16-bit bus, G1STG17: 0 denotes an 8-bit bus, 0 denotes line 0 or port, and 15 denotes line 15 or port.

ILP15: 0 is a lower address, which designates the output port with the lowest number among the output ports to which a cell input to any input port of the cell router switching network is copied and transmitted. IUP15: 0 is an upper address, which designates the output port having the highest number among the output ports to which a cell input to any input port of the cell router switching network is copied. ISP15: 0 is provided to the port L1 having the higher number (ie, address) of the two input ports L0 and L1 to which the lower address is input in each of the 2 × 2 unit switching devices for the free router. A signal obtained by latching the most significant bit (MSB) of an address, and is a valid address display signal indicating whether or not an input address is a valid address.

Referring to FIG. 4, the 2 × 2 unit switching device 1 includes two input ports L0, L1, U0, U1, and S0 allocated to each of the ILP15: 0, IUP15: 0, and ISP15: 0 signals. , S1 and the output ports OL0, OL1, OU0, OU1, OS0, OS1, in addition, have two more output ports for the output of the routing control signals G0, G1. The routing control signals G0 and G1 are provided to a cell router network for routing ATM cells and used to control switching of cells.

The free router switching network shown in FIG. 3 is a 16 × 16 switching network consisting of 32 unit switching devices (in other words, since the number of assignable ports is 16 (= 2 ⁴ )), And each of the lower addresses has a size of 4 bits. Therefore, in this switching network, a 4-bit address is serially input to each of the input ports allocated 16 for each of the upper and lower addresses IUP and ILP. For example, a 4-bit lower address (ILP) input through line 1 of the ILP15: 0 bus is provided in serial order from the most significant bit (MSB) to input port 1.

ATM cells are unicast if ILPn and IUPn are the same, and cells are multicast and replicated by the difference if ILPn and IUPn are different (here, N = 0, 1, ..., 15) When the lower address of '0111' is sequentially input through ILP1 and the upper address of '1001' is sequentially input through IUP1, the ATM cell inputted to port 1 (not shown) of the cell router switching network is selected. To 7 (= 0111 ₂ ), 8 (= 000 ₂ ), and 9 (= 1001 ₂ ) output ports (not shown), respectively.

FIG. 5 shows a preferred embodiment of a 2 × 2 unit switching device 1 for multicast communication of an asynchronous transmission type free router according to the present invention. Referring to FIG. 5, the unit switching device 1 includes a routing signal generation circuit 100 which generates routing bits G0 and G1 in response to input signals ISP, ILP, and IUP, and the input signal. Signal selection circuit 200 for selectively outputting only a desired signal among the input signals ISP, ILP and IUP by logically combining the ISPs ISP, ILP and IUP and the routing bits G0 and G1. And an output circuit 300 for latching the output of the signal selection circuit 200 and outputting the output through the output ports OU0, OU1, OL0, OL1, OS0, and OS1.

Hereinafter, for convenience of description, in the unit switching device 1, L0 to which the first lower address signal ILP2N, where N is 0 or a positive integer; for example, ILP0, is inputted as 'first input port'. L1 to which the second lower address signal ILP2N + 1 (eg, ILP1) is input is referred to as a 'second input port', and OL0 to which the first lower address signal ILP0 is output is referred to as a 'first output port', OL1 from which the second lower address signal ILP1 is output is 'second output port', U0 from which the first upper address signal IUP2N (eg, IUP0) is input, 'third input port', and second upper address signal IUP2N. +1, for example, U1 to which IUP1 is input is 'fourth input port', OU0 to which the first upper address signal IUP0 is output is 'third output port', and the second upper address signal IUP1 is The output OU1 is referred to as the 'fourth output port' and the first valid address display signal (ISP2N, for example, ISP0) is inputted as 'S0'. A fifth input port ', S1 to which the second valid address display signal ISP2N + 1 (for example, ISP1) is input, is referred to as a' sixth input port ', and OS0 to which the first valid address display signal ISP0 is output is' 5th. Output port 'and OS1 to which the second valid address indication signal ISP1 is output are respectively referred to as a' sixth output port ', and G0 is referred to as a' first routing control signal 'and a port for outputting it 7 output port, G1 will be referred to as 'second routing control signal' and the port for outputting it will be referred to as 'eighth output port'.

FIG. 6 shows a preferred embodiment of the routing signal generation circuit 100 shown in FIG. The first and second routing control signals G0 and G1 are determined by the state of the second valid address indication signal ISP1 provided to the sixth input port S1, and the logic is as follows.

Referring to FIG. 6, the routing signal generation circuit 100 may include the lower address signals ILP0 and ILP1 and the sixth input port S1 input through the first and second input ports L0 and L1, respectively. In response to the latch enable signal RET and the first routing signal generation unit 110 for generating a first routing control signal G0 by logically combining the second valid address indication signal ISP1 inputted through. Through the first latch unit 120 for selectively latching the output G0 of the first routing signal generator 110 and its output Q, and through the third and fourth input ports U0 and U1. A second routing control signal G1 is generated by logically combining the upper address signals IUP0 and IUP1 and the second valid address indication signal ISP1 input through the sixth input port S1, respectively. The second routing signal generator 130 and the latch enable signal RET in response to the second la And an output (G1) and its output to the second latch 140 to selectively latch the (Q) of the boot signal generator 130.

The first routing signal generator 110 includes a first inverter 111 having an input terminal connected to a sixth input port S1, an output terminal of the inverter 111, and a first input port L0. A first and gate 112 to which input terminals are connected, a second inverter 113 to which an input terminal is connected to the second input port L1, an output terminal of the inverter 113, and the sixth input port, respectively. A first end gate 112 to which two input terminals are connected to S1, a second inverter 113 to which an input terminal is connected to a second input port L1, an output terminal of the inverter 113, and A second end gate 114 having two input terminals connected to the sixth input port S1, and two input terminals connected to output terminals of the first and second end gates 112 and 114, respectively. A first or gate 115 is provided.

The first latch unit 120 selectively latches one of its output Q and the output of the first or gate 115 in response to the latch enable signal RET to thereby generate the first routing control signal G0. And a first scanned D flip-flop 121 for outputting.

The second routing signal generator 130 may include a second or gate 131 having two input terminals connected to the third input port U0 and the sixth input port S1, and a fourth input port U1. And two input terminals at the output terminal of the third and gate 132 and the second or gate 131, and the output terminal of the third and gate 132, which are connected to the sixth and sixth input ports S1, respectively. And a third or gate 133 connected to each other.

The second latch unit 140 selectively latches one of its own output Q and the output of the third or gate 133 in response to the latch enable signal RET to generate a second routing control signal G1. And a second stand D flip-flop 141 which is output as.

The outputs G0 and G1 of the routing signal generation circuit 100 are provided to a 2 × 2 unit switching device (see FIGS. 2A to 2D) of the cell router network.

Referring to FIG. 5, the signal selection circuit 200 may select one of the first and second higher address signals IUP0 and IUP1 in response to the first and second routing control signals G0 and G1. A first selector 210 which selects and outputs the selected signal as a first upper address signal through a third output port OU0; and the first and second in response to the first and second routing control signals. A second selector 220 which selects one of the lower address signals ILP0 and ILP1 and outputs the selected signal as the first lower address signal through the first output port OL0, and responds to the routing control signals. The third selector 230 selects one of the first and second valid address display signals ISP0 and ISP1 and outputs the selected signal as the first valid address display signal through the fifth output port OS0. And in response to the first and second routing control signals; A fourth selector 240 which selects one of the second upper address signals and outputs the selected signal as the second upper address signal through the fourth output port OU1, and the first and second routing control signals A fifth selector 250 which selects any one of the first and second lower address signals in response to the second signal and outputs the selected signal as a second lower address signal through a second output cloth OL1; A sixth selector 260 which selects one of the first and second valid address indication signals in response to the signals and outputs the selected signal as a second valid address indication signal through the sixth output port OS1; Equipped.

The first selector 210 may include a fourth end gate 211 having one input terminal connected to the fourth input port U1 and the other input terminal receiving the second routing control signal G1. A first exclusive or gate 212 receiving first and second routing control signals G0 and G1 through two input terminals, and a third inverter for inverting the second routing control signal G1; 213 and a fifth end gate 214 having two input terminals connected to an output terminal and a third input port U0 of the inverter 213, and the fourth and fifth end gates 211, 214 and a fourth or gate 215 having three input terminals connected to output terminals of the exclusive or gate 212, respectively.

The second selector 220 includes a sixth end gate 221 having one input terminal receiving the second routing control signal G1 and the other input terminal connected to the second input port L1. And a fourth inverter 222 for inverting the second routing control signal G1, and a seventh end gate 223 having two input terminals connected to the output terminal and the first input port L0 of the inverter 222, respectively. And a fifth or gate 224 having two input terminals connected to output terminals of the sixth and seventh end gates 221 and 223, respectively.

The third selector 230 may include an eighth end gate 231 having one input terminal receiving the second routing control signal G1 and the other input terminal connected to the sixth input port S1. And a fifth inverter 232 for inverting the second routing control signal G1, and a ninth end gate 233 having two input terminals connected to an output terminal and a fifth input port S0 of the inverter 232, respectively. ), And a sixth or gate 234 connected to two output terminals of the eighth and ninth end gates 231 and 233, respectively.

The fourth selector 240 may include a tenth end gate 241 having one input terminal receiving the second routing control signal G1 and the other input terminal connected to the fourth input port U1. A sixth inverter 242 for inverting the first routing control signal G0, and an eleventh and gate 243 having two input terminals connected to an output terminal and a third input port U0 of the inverter 242, respectively. And a seventh or gate 244 having two input terminals connected to output terminals of the tenth and eleventh end gates 241 and 243, respectively.

The fifth selector 250 includes a seventh inverter 251 for inverting the first routing control signal G0, and two input terminals at the output terminal and the first input terminal L0 of the inverter 251, respectively. A thirteenth AND gate 253 having a twelfth AND gate 252 connected thereto, an input terminal receiving the first routing control signal G0, and another input terminal connected to the second input port L1; And an eighth or gate 254 having two input terminals connected to output terminals of the twelfth and thirteenth end gates 252 and 253, and an eighth for inverting the first routing control signal G0. A second exclusive or gate 256 having an inverter 255, one input terminal connected to the output terminal of the inverter 255, and the other input terminal receiving the second routing control signal G1; And two input stages at output terminals of the eighth or gate 254 and the second exclusive or gate 256. Are composed of the ninth OR gate 257 are connected, respectively.

The sixth selector 260 may include a fourteenth AND gate 261 having one input terminal receiving the first routing control signal G0 and the other input terminal connected to the sixth input port S1. And a ninth inverter 262 for inverting the first routing control signal G0, and a fifteenth end gate 263 having two input terminals connected to an output terminal and a fifth input port S0 of the inverter 262, respectively. And a tenth ore gate 264 in which two input terminals are respectively connected to output terminals of the fourteenth and sixteenth end gates 261 and 263.

The output circuit 300 includes first to sixth D flip-flops 310 to 360 having input terminals connected to output terminals of the first to sixth selectors 210 to 260, respectively. The output terminal of the first D flip-flop 310 is connected to the third output port OU0, and the output terminal of the second D flip-flop 320 is connected to the first output port OL0, and the third D flip-flop ( The output terminal of the 330 is connected to the fifth output port OS0, the output terminal of the fourth D flip-flop 340 is connected to the fourth output port OU1, and the output terminal of the fifth D flip-flop 350 is second To the output port OL0, the output terminal of the sixth D flip-flop 360 is connected to the fifth output port OS1, respectively.

Claims (19)

A unit switching apparatus of a pre-router network for ATM that matches a flow of destination addresses of ATM cells with a cell flow in a cell router network in which the cells are transmitted, the cell router to which two transmitted cells are copied and output respectively. Lower address signals ILP2N and IPL2N + 1 respectively indicating ports of the lowest addresses among the output ports of the network, and upper address signals IUP2N respectively indicating ports of the highest addresses among the output ports to which the copied cells are to be output. First to sixth input ports to which IUP2N + 1) and valid address indication signals ISP2N and ISP2N + 1 (where N is 0 or a positive integer), respectively, indicating whether the lower and upper addresses are valid; (L0, L1, U0, U1, S0, S1), First to sixth output ports (OL0, OL1, OU0, OU1, OS0, OS1) for outputting the lower address signals, the upper address signals, and the valid address indication signals, respectively; First and second devices for controlling switching of the cell router network in response to the lower address signals, the upper address signals, and the valid address indication signal ISP2N + 1 from the sixth input port S1; Routing signal generating means (100) for generating routing control signals (G0, G1), Signal selection means (200) for selectively outputting the valid address indication signals, the lower address signals, and the upper address signals corresponding to the first to sixth output ports in response to the routing control signals; , Output means for latching the outputs of the signal selecting means 200 and outputting the latched signals through the first to sixth output ports as the lower address signals, the upper address signals, and the valid address display signals, respectively; Switch comprising a 300). The method of claim 2, The routing signal generating means 100, A first routing signal generator 110 generating a first routing control signal G0 by logically combining the lower address signals and the effective address indication signal ISP2N + 1; A first latch unit 120 which selectively latches the output G0 of the first routing signal generator 110 and its own output Q in response to a latch enable signal RET provided from the outside; A second routing signal generator 130 for generating the second routing control signal G1 by logically combining the upper address signals and the valid address display signal ISP2N + 1; And a second latch unit 140 for selectively latching the output G1 of the second routing signal generator 130 and its own output Q in response to the latch enable signal RET. Switching device. The method of claim 2, The first routing signal generator 110, A first inverter 111 to which an input terminal is connected to the sixth input port S1; A first end gate 112 having two input terminals connected to an output terminal of the first inverter 111 and the first input port L0, respectively; A second inverter 113 having an input terminal connected to the second input port L1; A second end gate 114 having two input terminals connected to an output terminal of the inverter 113 and the sixth input port S1, respectively; And a first or gate (115) having two input terminals connected to output terminals of the first and second end gates (112, 114), respectively. The method of claim 2, The second routing signal generator 130, A second or gate 131 having two input terminals connected to the third and sixth input ports U0 and S1, respectively; A third end gate 132 having two input terminals connected to the fourth input port U1 and the sixth input port S1, respectively; And a third ore gate (133) having two input terminals respectively connected to an output terminal of the second or gate (131) and an output terminal of the third and gate (132). The method of claim 3, The first latch unit 120, A first scan for selectively latching one of an output Q and an output of the first or gate 115 in response to the latch enable signal RET, and outputting the first routing control signal G0 as a first routing control signal G0 And a D flip-flop (121). The method of claim 4, wherein The second latch unit 140, A second scan selectively latching one of its output Q and an output of the third or gate 133 in response to the latch enable signal RET and outputting the second routing control signal G1 as a second routing control signal G1; And a D flip-flop (141). The method according to any one of claims 1 to 6, The signal selection means 200, A first selector configured to select one of the upper address signals in response to the first and second routing control signals and output the selected signal as a first upper address signal through the third output port OU0; 210), A second selector which selects one of the lower address signals in response to the first and second routing control signals and outputs the selected signal as a first lower address signal through the first output port OU0; 220), A third selector 230 which selects any one of valid address display signals in response to the routing control signals and outputs the selected signal as a first valid address display signal through the fifth output port OS0; A fourth selector configured to select one of the upper address signals in response to the first and second routing control signals and output the selected signal as a second upper address signal through the fourth output port OU1 ( 240), A fifth selector which selects one of the lower address signals in response to the first and second routing control signals and outputs the selected signal as a second lower address signal through the second output port OL1; 250), and A sixth selector 260 which selects one of the valid address indication signals in response to the routing control signals and outputs the selected signal as a second valid address indication signal through the sixth output port OS1; Switching device comprising a. The method of claim 7, wherein The first selector 210, A fourth end gate 211 having one input terminal connected to the fourth input port U1 and the other input terminal receiving the second routing control signal G1; A first exclusive or gate 212 receiving the first and second routing control signals G0 and G1 through two input terminals, respectively; A third inverter 213 for inverting the second routing control signal G1; A fifth end gate 214 having two input terminals connected to an output terminal of the third inverter 213 and the third input port U0; And a fourth or gate 215 having input terminals connected to output terminals of the fourth and fifth end gates 211 and 214 and the exclusive or gate 212, respectively. Device. The method of claim 7, wherein The second selector 220, A sixth end gate 221 having one input terminal receiving the second routing control signal G1 and the other input terminal connected to the diffuser second input port L1; A fourth inverter 222 for inverting the second routing control signal G1; A seventh end gate 223 having two input terminals connected to an output terminal of the fourth inverter 222 and the first input port L0, and And a fifth or gate (224) having two input terminals connected to output terminals of the sixth and seventh gates (221, 223), respectively. The method of claim 7, wherein The third selector 230, An eighth end gate 231 having one input terminal receiving the second routing control signal G1 and the other input terminal connected to the sixth input port S1; A fifth inverter 232 for inverting the second routing control signal G1; A ninth end gate 233 having two input terminals connected to an output terminal of the fifth inverter 232 and the fifth input port S0, and And a sixth ore gate (234) having two input terminals connected to output terminals of the eighth and ninth end gates (231, 233), respectively. The method of claim 7, wherein The fourth selector 240, A tenth end gate 241 having one input terminal receiving the second routing control signal G1 and the other input terminal connected to the fourth input port U1; A sixth inverter 242 for inverting the first routing control signal G0; An eleventh end gate 243 having two input terminals connected to an output terminal of the sixth inverter 242 and the third input port U0, and And a seventh ore gate (244) having two input terminals connected to output terminals of the tenth and eleventh end gates (241, 243), respectively. The method of claim 7, wherein The fifth selector 250, A seventh inverter 251 for inverting the first routing control signal G0; A twelfth and gate 252 having two input terminals connected to an output terminal of the seventh inverter 251 and the first input terminal L0, respectively; A thirteenth end gate 253 having one input terminal receiving the first routing control signal G0 and the other input terminal connected to the second input port L1; An eighth gate 254 having two input terminals connected to output terminals of the twelfth and thirteenth gates 252 and 253, respectively; An eighth inverter 255 for inverting the first routing control signal G0; A second exclusive or gate 256 having one input terminal connected to the output terminal of the eighth inverter 255 and the other input terminal receiving the second routing control signal G1; And a ninth gate (257) having two input terminals connected to output terminals of the eighth gate (254) and the second exclusive or gate (256), respectively. The method of claim 7, wherein The sixth selector 260, A fourteenth gate 261 having one input terminal receiving the first routing control signal G0 and the other input terminal connected to the sixth input port S1; A ninth inverter 262 for inverting the first routing control signal G0; A fifteenth gate 263 having two input terminals connected to an output terminal of the ninth inverter 262 and the fifth input port S0, and And a tenth gate (264) connected to two input terminals of the output terminals of the fourteenth and sixteenth gates (261, 263), respectively. A switching apparatus of an ATM pre-router network for matching a flow of a destination address of an ATM cell with a cell flow in a cell router network through which the cell is transmitted; A plurality of unit switching devices forming a 2 ^{m by} 2 ^m inverse-venion network, where m is an integer greater than 3; Each of the plurality of unit switching devices, The lower address signals ILP2N and IPL2N + 1, the upper address signals IUP2N and IUP2N + 1, and the valid address indication signals ISP2N and ISP2N + 1, where N is 0 or a positive integer, respectively. First to sixth input ports (L0, L1, U0, U1, S0, S1), First to sixth output ports (OL0, OL1, OU0, OU1, OS0, and OS1) for outputting the lower address signals, the upper address signals, and the valid address display signals, respectively; In response to the lower address signals, the upper address signals, and the valid address indication signal ISP2N + 1 from the sixth input port S1, first and second routing control signals G0 and G1 are received. Routing signal generation means 100 to generate, Selectively combining the valid address indication signals, the lower address signals, and the upper address signals by logically combining the lower address signals, the upper address signals, the valid address indication signals, and the routing control signals. Signal selection means 200 for outputting corresponding to the sixth to sixth output ports, The outputs of the signal selecting means 200 are latched and the latched preference is applied to the lower address signals and the upper address signals through the first to sixth output ports OL0, OL1, OU0, OU1, OS0, and OS1. And output means (300) for outputting each of the valid address indication signals; And the routing control signals generated by each of the plurality of unit switching devices are provided to corresponding unit switching devices of the cell router network. The method of claim 14, The routing signal generating means 100, The first routing signal generator 110 generates a first routing control signal G0 by logically combining the lower address signals and the valid address indication signal ISP2N + 1 from the sixth input port S1. Wow, A first latch unit 120 for selectively latching the output G0 of the first routing signal generator 110 and its own output Q in response to a latch enable signal RET provided from the outside; A second routing signal generator 130 for generating the second routing control signal G1 by logically combining the upper address signals and the valid address indication signal ISP2N + 1 from the sixth input port; And a second latch unit 140 for selectively latching the output G1 of the second routing signal generator 130 and its own output Q in response to the latch enable signal RET. Switching device. The method of claim 15, The first routing signal generator 110, A first inverter 111 to which an input terminal is connected to the sixth input port S1; A first end gate 112 having two input terminals connected to an output terminal of the first inverter 111 and the first input port L0, respectively; A second inverter 113 having an input terminal connected to the second input port L1; A second end gate 114 having two input terminals connected to an output terminal of the second inverter 113 and the sixth input port S1, respectively; And a first or gate (115) having two input terminals connected to output terminals of the first and second end gates (112, 114), respectively. The method of claim 15, The second routing signal generator 130, A second or gate 131 having two input terminals connected to the third and sixth input ports U0 and S1, respectively; A third end gate 132 having two input terminals connected to the fourth input port U1 and the sixth input port S1, respectively; And a third ore gate (133) having two input terminals respectively connected to an output terminal of the second or gate (131) and an output terminal of the third and gate (132). The method of claim 16, The first latch unit 120, A first scan for selectively latching one of an output Q and an output of the first or gate 115 in response to the latch enable signal RET, and outputting the first routing control signal G0 as a first routing control signal G0 De D flip-flop 121; The second latch unit 140, A second scan selectively latching one of an output Q and an output of the third gate 133 in response to the latch enable signal RET and outputting the second routing control signal G1 as a second routing control signal G1; And a D flip-flop (141). The method according to any one of claims 14 to 18, The signal selection means 200, A first selector 210 which selects any one of the upper address signals and outputs the first upper address signal in response to the first and second routing control signals; A second selector 220 which selects one of the lower address signals and outputs the first lower address signal in response to the first and second routing control signals; A third selector 230 which selects one of the valid address display signals and outputs the first valid address display signal in response to the routing control signals; A fourth selector 240 which selects one of the upper address signals and outputs the second upper address signal in response to the first and second routing control signals; A fifth selector 250 which selects any one of the lower address signals and outputs the second lower address signal in response to the first and second routing control signals; And a sixth selector (260) for selecting any one of the valid address indication signals and outputting the second valid address indication signal in response to the routing control signals.