JPH07303048A - Decoding circuit in partial response transmission system - Google Patents

Abstract

PURPOSE: To provide a stable surviver metric at a high speed by allowing a differential surviver metric to be calculated to use the output of a determination part, when detecting a transmission signal having a highest probability of transmission out of a sequence of signal samples. CONSTITUTION: A 1st adder 250a adds the output of a multiplexer 230 and a sample value yn and applies the result to a determination part 210a which outputs a binary value. Outputs of 2nd flip-flops 220 and 225 are applied to the multiplexer 230 and become the output of a calculation part. A multiplier 260 provides a complementary form by multiplying '-1' to the output of the multiplexer 230. The output of the multiplexer 260 is inputted to a 1st register 240a, a sample value yn is inputted to a 2nd adder 270 and a subtracter 280, '1' is added and subtracted, and the outputs of 2nd adder 270 and subtracter 280 are inputted to 3rd and 4th registers 240b and 240c. The multiplexer 230 outputs differential surviver metric DJn-1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding circuit in a partial response transmission system, and particularly in the case of duobinary and dicode partial response system, outputs a stable survivor metric for every clock and outputs a Viterbi decoder. The present invention relates to a circuit for realizing.

[0002]

2. Description of the Related Art When a series of digital signals are transmitted through a communication channel having a baseband characteristic, the signal received at the receiving end has signal interference as well as additive noise. An equalization process that removes signal interference is used to detect the transmitted signal from the received signal. However, since the additive noise is amplified in this equalization process, it becomes difficult to detect the transmission signal.

However, PR (Partial Res)
In the (pse) system, the signal processing at the receiving end is extremely easy since the signal interference of a properly specified amount is allowed in consideration of a given channel state, and the channel bandwidth can be used more effectively. There is an advantage called. The PR system is used for baseband data transmission and FM and S
It can be applied to various modulation methods such as SB modulation.

The types of PR systems are (1 + D),
(1-D), (1-D ² ), etc., and duobinary and dicode (dic), respectively.
ode) and class-IV (class-4). Here, D indicates delay. Of these, Class-I
V is similar in properties to magnetic data storage channels, and Duobinary is similar in properties to magneto-optical channels.

Best Sequence Evaluation (Maximum-L
ikelihood Sequence Estima
(hereinafter, abbreviated as MLSE) method is an effective method for detecting a series of symbol sequences when interference is present in a received signal. In particular, the Viterbi Algorithm efficiently uses the MLSE method. It is a method to realize it.

Therefore, if the signal is processed in the PR form to allow a specified amount of interference in the received signal and then processed by the Viterbi algorithm, the size and complexity at the receiving end including the Viterbi algorithm are reduced. The signal to noise ratio (SNR).
The performance degradation of Noise Ratio) can be overcome.

FIG. 1 is a block diagram of a general partial response transmission system.

Referring to FIG. 1, binary symbols of "1" and "-1" are provided in a channel 11 at intervals of T (T; period).
Transmitted through. The received signal x (t) is a continuous signal to which white noise w (t) is added, and is expressed by the following first equation.

[0009]

[Equation 1]

After the received signal x (t) is processed by the receiver filter 13, the output y (t) is obtained and the output y (t) is obtained.
(T) is sampled at intervals of T by the switch 15 and converted into a discrete signal yn. The discrete signal yn is (1 + D), (1-D), (1
-D ² ), the following second to fourth equations are respectively given.
It is expressed like an expression.

Yn = an + an-1 + rn: PR (1 + D) (2)

Yn = an-an-1 + rn: PR (1-D) (3)

[0013] yn = an - an-2 + rn: PR (1-D 2) ··· (4)

Here, rn is a signal resulting from processing the white noise w (t) by the receiver filter 13. (1+
For example, in the case of D), the sequence having the highest probability of being transmitted is described.

[0015]

[Outer 1]

Minimizes the value of the following fifth equation.

[0017]

[Equation 2]

Since the square term in equation 5 is the same for all sequences, the sequence an which minimizes the value of equation 5 is the same as the one which maximizes the value of equation 6 below.

[0019]

[Equation 3]

Here, vk (ak, ak-1) is (1 + D), (1-D) or (1-) according to the PR characteristic used.
When expressed as D ² ), they are respectively expressed by the following formulas 7 to 9.

Vk (ak, ak-1) = yk (ak + ak-1) -ak.ak-1: PR (1 + D) (7)

Vk (ak, ak-1) = yk (ak-ak-1) + ak.ak-1: PR (1-D) (8)

Vk (ak, ak-2) = yk (ak-ak-2) + ak · ak-2: PR (1 + D ² ) (9)

A sequence that maximizes the value J calculated by the sixth equation is a survivor sequence (survivor sequence).
sequence) qn (an), and the value J at this time
n (an) is the survivor metric (survivor)
metric). Survivor sequence qn
A simple expression of (an) and the survivor metric Jn (an) is as shown in the following formulas 10 and 11.

[0025]

[Equation 4]

Jn (an) = max [Jn-1 (an-1) + vn (an, an-1)], an-1 = ± 1 (11)

Then, rearranging for an = ± 1 respectively, Jn (an) is expressed by the following equations 12 and 13.

Jn (+1) = max {Jn-1 (+1) + 2yn-1, Jn-1 (-1) +1} (12)

Jn (-1) = max {Jn-1 (+1) +1, Jn-1 (-1) -2yn-1} (13)

The survivor sequence conversions that can occur at this time are as shown in Table 1 below.

[0031]

[Table 1]

For such a binary sequence, the algorithm can be easily expressed as the following fourteenth expression by considering the difference in the survivor metric.

DJn = 1 / 2.multidot. [Jn (+1) -Jn (-1)] (14)

Now, in the case of the duobinary partial response system, the difference survivor metric can be simply expressed as the following fifteenth expression.

[0035]

[Equation 5]

On the other hand, in the case of the dicode partial response system, the difference survivor metric can be simply expressed as the following 16th equation.

[0037]

[Equation 6]

On the other hand, in the case of the class-IV partial response system, the difference survivor metric can be simply expressed as the following expression (17).

[0039]

[Equation 7]

The Viterbi decoder 17 is for performing MLSE with the difference survivor metric as described above, and stores the survivor metric calculator 18 for determining the survivor metric and the temporary binary output, and the survivor sequence. It is composed of a survivor sequence storage and update unit 19 that updates and outputs the final binary value.

FIG. 2 shows a survivor metric calculator 18 used in the conventional Viterbi decoder 17 shown in FIG. 1, which is disclosed in US Pat. No. 4,644,564.
Issue (filing date October 15, 1985), Francoi
s B. "DECODIN" by two people outside Dolivo
G THE OUTPUT SIGNAL OF AP
ARTIAL-RESPONSE CLASS-IV
COMMUNICATION OR RECODING
DEVICE CHANNEL ”.
The invention of Francois is Class-IV (class-
IV) Targeting PR (1-D ² ), class-I
Due to the characteristics of V (class-IV) PR, a received signal is divided into odd-numbered or even-numbered signals and two sequences are processed independently. When this technology is applied to duobinary (1 + D) and dicode (1-D),
It is disclosed that it can be applied by simply changing a part. However, when the method is applied to duobinary (1 + D) and dicode (1-D) without using the designated registers, the output becomes unstable and reliability is reduced. Occur.

[0042]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve duobinary,
A circuit for outputting a stable survivor metric for each clock to implement a Viterbi decoder in a dicode and class-IV partial response transmission system.

[0043]

In order to achieve the above object, the present invention comprises a receiver filter, a sample switch, a survivor metric calculation unit, a survivor sequence and update unit, and a duobinary,
In a circuit for maximally sequence-decoding a sequence of sample signals having dicode and class-IV partial response signal interference, the survivor metric calculator is configured to detect the sample signal and the survivor metric calculator according to the type of partial response. An adder / subtractor for adding / subtracting the output signal of, and a determination unit for outputting two binary values with the output signal of the adder / subtractor as an input,
And a multiplexer for calculating the survivor metric using the output signal of the determining unit as a selection control signal.

[0044]

In the decoding circuit, the differential survivor metric calculated when detecting the transmitted signal with the highest probability of being transmitted from the received sequence of signal samples is used to determine the output of the multiplexer using the output of the decision unit. The output of the determining unit is stored in each flip-flop and updated to determine the final output.

[0045]

The present invention will be described in detail below with reference to the accompanying drawings.

FIG. 3 is a block diagram of a first embodiment of a survivor metric calculation unit used in the decoding circuit of the present invention in a duobinary partial response transmission system, which is a decision unit 210a, first and second flip-flops. 220, 225, multiplexer 230, first to third registers 240a, 240b, 240c, first adder 250
a, a multiplier 260, a second adder 270, and a subtractor 28
It consists of zero.

FIG. 4 is a block diagram of a second embodiment of the survivor metric calculator used in the decoding circuit of the present invention in the duobinary partial response transmission system, which is a decision unit 210a, first and second flip-flops. 220, 225, a multiplexer 230, a fourth register 240d, a first adder 250a, a multiplier 260, a second adder 270, and a subtractor 280.

FIG. 5 is a block diagram of a first embodiment of a survivor metric calculation unit used in the decoding circuit of the present invention in a dicode partial response transmission system. The determination unit 210b, the first flip-flop 220,
225, multiplexer 230, first to third registers 24
0a, 240b, 240c, first subtractor 250b, second
It is composed of an adder 270 and a second subtractor 280.

FIG. 6 is a block diagram of a second embodiment of a survivor metric calculation unit used in the decoding circuit of the present invention in a dicode partial response transmission system, which is a decision unit 210b, first and second flip-flops. 22
0, 225, multiplexer 230, fourth register 24
0d, the first subtractor 250b, the second adder 270, and the second subtractor 280.

FIG. 7 is a block diagram of a first embodiment of a survivor metric calculator used in the decoding circuit of the present invention in a class-IV partial response transmission system, which is a decision unit 210b, first and second flip-flops. 2
20, 225, multiplexer 230, first to fourth registers 240a, 240b, 240c, 240d, first subtractor 250b, second adder 270, and second subtractor 280.
It is composed of

FIG. 8 is a block diagram of a second embodiment of the survivor metric calculation unit used in the decoding circuit of the present invention in the class-IV partial response transmission system. The determination unit 210b and the second flip-flop 22 are shown in FIG.
0, 225, multiplexer 230, fourth and fifth registers 240d and 240e, first subtractor 250a, second adder 270, and second subtractor 280.

FIG. 9 is a block diagram of a first embodiment of the decision unit shown in FIGS.
0, 330, 370a, first and second AND gates 320,
350, inverter 340a, and NAND gate 360
a.

FIG. 10 is a block diagram of a second embodiment of the determining unit shown in FIGS. 3 to 8, and includes first and second OR gates 310,
330, 1st, 2nd, 3rd AND gates 320, 350, 3
60b, an inverter 340a and a NOR gate 370b.

FIG. 11 is a block diagram of an embodiment of the survivor sequence storage and update unit used in the decoding circuit of the present invention shown in FIG. 1, and includes a plurality of flip-flops 410, 411, 420, 421 ,. ． Four
90, 491 and a plurality of multiplexers 412, 413,
422, 423 ,. ． It is composed of 492 and 493.

The operation of the present invention will now be described with reference to FIGS.
This will be described with reference to FIG.

[0056] First, the survivor metric calculation unit 18 inputs the sample values yn, binary bits b ⁺ n-1 and b ^-
Outputs n-1 and.

In FIG. 3, the first adder 250a has the output DJn-1 of the multiplexer 230 and the sample value yn.
Is added and the addition result is applied to the determination unit 210a. When there is no noise, the sample value yn is "-2", "0", "+".
The determination unit 210a outputs a temporary binary value according to the following eighteenth expression.

[0058]

[Equation 8]

[0059] Binary Output b ⁺ n and b is outputted from the determining unit 210a ^- n is temporarily respectively store the first flip-flop 220 to the second flip-flop 225, first
Flip-flop 220 and second flip-flop 225
Is output b ⁺ n-1 and b ^- n-1 is applied to the multiplexer 230. A first flip-flop 220 is the output of the second flip-flop 225 b ⁺ n-1 and b ^- n-1 is the output of the survivor metric calculation unit 18.

Multiplier 260 multiplies the output of multiplexer 230 by "-1" to form a two's complement form. The output −DJn−1 of the multiplier 260 is input to the first register 240a. On the other hand, the sample value yn is the second adder 270.
And “1” are added to and subtracted from each other, and the output signals yn + 1 and yn−1 of the second adder 270 and the subtractor 280 are respectively input to the second register 2
40b and the third register 240c. The first register 240a, the second register 240b and the third register 240c are -DJn-2, yn-1 + 1 and yn-1-, respectively.
1 is output and input to the multiplexer 230.

The multiplexer 230 includes the first register 2
40a, second register 240b and third register 240
-DJn-2, yn-1 + 1, yn- respectively output from c
1-1 is an input signal, and the outputs of the first flip-flop 220 and the second flip-flop 225 are b ⁺ n-1 and b ^- n.
-1 is used as a selection control signal, and a new difference survivor metric -DJn-1 is output as in the above-described Expression 15.

FIG. 4 shows a second embodiment of the survivor metric calculation unit 18 in the case of the duobinary partial response transmission system. Compared with FIG.
a, the second register 240b and the third register 240c are removed, and the fourth register 240d is added to the output end of the multiplexer 230, and the selection control signals that determine the output of the multiplexer 230 are b ⁺ n and b ^- n. Is different.

FIG. 5 shows the first embodiment of the survivor metric calculation unit 18 in the case of the dicode partial response transmission system. Compared with FIG. 3, the subtracter is used to determine the value obtained by subtracting yn from DJn-1. The difference is that 250b is used, and accordingly, the determining unit 210b having different determination content is used. At this time, the determining unit 210b is realized by a ROM, a PLA, or a logic as shown in FIG.

FIG. 6 shows a second embodiment of the survivor metric calculation unit 18 in the case of the dicode partial response transmission system. Compared with FIG. 5, the first register 240a, the second register 240b and the third register 240c are compared. And remove the fourth register 24 at the output of the multiplexer 230.
0d is added, and the selection control signals that determine the output of the multiplexer 230 at this time are b ⁺ n and b ⁻ n output from the determining unit 210.

FIG. 7 shows a first embodiment of the survivor metric calculation unit 18 in the case of the class-IV partial response transmission system. Compared with FIG. 3, the value obtained by subtracting yn-1 from DJn-1 is determined. The subtractor 250b is used for the decision, and the decision 210b having different decision contents is used. At this time, the determining unit 210b is realized by a ROM, a PLA, or a logic as shown in FIG. Further, the fourth resist 240d adds the output of the multiplexer 230, the selection control signal for determining the output of the time multiplexer 230 b ⁺ n-1 and b ^- becomes n-1.

FIG. 8 shows a second embodiment of the survivor metric calculation unit 18 in the case of the class-IV partial response transmission system. Compared with FIG. 7, the first register 240a,
The second register 240b and the third register 240c are removed, and the fourth register 2 is added to the output end of the multiplexer 230.
40d and the fifth register 240e are added, and the selection control signal that determines the output of the multiplexer 230 at this time is b ⁺ n.
And b ^- n.

On the other hand, in FIG. 3 and FIG.
0a is a ROM (Read Only Memory) or P
LA (Programmable Logic Arr
ay) or a discrete logic circuit.

[0068] determination unit 210a when input is P, the first 18 by performing expression b ⁺ n and b ^- to output a n. FIG. 9 shows an embodiment in which the decision unit 210a is realized by using a discrete logic circuit, and the input is 8 bits and the least significant bit LS of the input.
This is an example of the case where B is 2 ^-3 , and the input value uses 2's complement. P4 has a value of 2 ⁴ as the most significant bit,
P ^-3 has a value of 2 ^-3 as the least significant bit.

In FIG. 9, the outputs of the OR gate 310 and the inverter 340 are b ⁺ n through the NAND gate 360a.
Value of AND gate 320 output and OR gate 3
The output of 30 is input to the AND gate 350, and the output of the inverter 340 and the output of the AND gate 350 determine the value of b ^- n through the OR gate 370a. Here, b ⁺ n and b ^- n are input to the first flip-flop 220 and the second flip-flop 225 of FIGS.

On the other hand, FIG. 10 embodies the determining unit 210b, and the determining unit 210b is the determining unit 210a of FIG.
The NAND gate 360a is replaced with an AND gate 360b, and the OR gate 370a is replaced with a NOR gate 370b in order to obtain an inverted signal of the signal output from. At this time, the AND gate 360b and the NOR gate 370
respectively output from b b ⁺ n and b ^- n is 5-8
Is input to the first flip-flop 220 and the second flip-flop 225.

[0071] Then, the survivor sequence storage and updating unit 19, as shown in FIG. 11, the binary bit b ⁺ n and b is the output of the survivor metric calculation unit 18 ^- outputs the final decision value n as an input . This circuit basically takes the form of a shift register consisting of two flip-flop sequences. Each flip-flop is connected to a subsequent flip-flop by a multiplexer or a gating circuit, and one of the output bit of the previous flip-flop of the same shift register and the output bit of the previous flip-flop of another shift register is used. Can be selectively moved to the next flip-flop.

In the case of the class-IV partial response transmission system as shown in FIGS. 7 and 8, the output of the survivor metric calculation unit 18 is divided into an odd number and an even number, and the survivor sequence storage shown in FIG. 11 is stored for each. The final output is obtained by interleaving the outputs of these two sequences using the update unit 19 and the update unit 19. At this time, the operation speed of the two sequences should be 1/2 or more as compared with other circuits.

[0073]

As described above, in the partial response transmission system, in the decoding circuit according to the present invention, the difference calculated when the transmission signal having the highest transmission probability is detected from the received sequence of signal samples. The survivor metric can be obtained by determining the output of the multiplexer using the output of the determiner. The output of the determining unit is stored in each flip-flop and updated to determine the final output. Therefore, a stable survivor metric can be obtained at high speed per clock.

[Brief description of drawings]

FIG. 1 is a block diagram showing a general partial response transmission system.

FIG. 2 is a block diagram showing a survivor metric calculator used in the conventional decoding circuit of FIG.

FIG. 3 is a block diagram of a first embodiment of a survivor metric calculator used in the decoding circuit of the present invention in a duobinary partial response transmission system.

FIG. 4 is a block diagram of a first embodiment of a survivor metric calculation unit used in the decoding circuit of the present invention in a duobinary partial response transmission system.

FIG. 5 is a block diagram of a first embodiment of a survivor metric calculation unit used in the decoding circuit of the present invention in a dicode partial response transmission system.

FIG. 6 is a block diagram of a second embodiment of a survivor metric calculation unit used in the decoding circuit of the present invention in a dicode partial response transmission system.

FIG. 7 shows a class-IV partial response transmission system,
3 is a block diagram of a first embodiment of a survivor metric calculation unit used in the decoding circuit of the present invention. FIG.

FIG. 8 is a Class-IV partial response transmission system,
FIG. 6 is a block diagram of a survivor metric calculator used in a decoding circuit according to a second embodiment of the present invention.

9 is a block diagram of a first embodiment of the determination unit of FIGS. 3 to 8. FIG.

10 is a block diagram of a second embodiment of the determination unit in FIGS. 3 to 8. FIG.

11 is a block diagram of an embodiment of a survivor sequence storage and update unit used in the decoding circuit of the present invention in FIG.

[Explanation of symbols]

 11 channel 13 receiver filter 15 switch 17 Viterbi decoder 18 survivor metric calculation unit 19 survivor sequence storage and update unit 81 limiter determination unit 83 register 85 subtractor 87 register 89 register 91 adder 93 flip-flop 95 flip-flop 99 flip-flop 210a determination unit 210b Determining unit 220 First flip-flop 225 Second flip-flop 230 Multiplexer 240a First register 240b Second register 240c Third register 240d Fourth register 240e Fifth register 250a First adder 250b First subtracter 260 Multiplier 270th 2 adder 280 2nd subtractor 310 1st OR gate 320 1st AND gate 330 2nd OR gate 340 Inverter 350 second AND gate 360a NAND gate 360b third AND gate 370a third OR gate 370b NOR gates 410,420,490 flip flops 411,421,491 flip flops 412,422,492 multiplexers 413,423,493 multiplexer

Claims (2)

[Claims] 1. A receiver filter, a sample switch, a survivor metric calculation unit, a survivor sequence storage and update unit, and a sample signal having signal interference of duobinary, dicode and class-IV partial response. A decoding circuit in a partial response transmission system, which performs best-sequence decoding of a sequence, wherein the survivor metric calculation unit outputs the sample signal and an output signal of the survivor metric calculation unit according to the type of the partial response. A subtractor for adding and subtracting, a decision unit for outputting two binary values with the output signal of the adder / subtractor as an input, and a multiplexer for calculating the survivor metric with the output signal of the decision unit as a selection control signal Is characterized by having Decoding circuitry in the partial response transmission system. 2. The survivor metric calculation unit,
2. The partial response transmission system according to claim 1, wherein one of three values input to the multiplexer is used to determine the survivor metric by using a binary value output from the determination unit. Decoding circuit.