JPH07302222A - Processor provided with external program memory - Google Patents

Abstract

PURPOSE:To improve diversification at the time of using the plural kinds of programs by performing program control for specifying the optional address of a selected program memory within external or internal program memories. CONSTITUTION:A program memory control part 11 sends out PCS signals for selecting the internal program memory 2a or the external program memory 2b to the memory 2a or 2b corresponding to the kind of IN/EXT signals impressed from the outside of this processor during a reset period by RESET signals. Simultaneously, the program memory control part 11 specifies the instruction execution starting address of the selected program memory by EMSEL0 signals, EMSEL1 signals, PA signals, PRD signals and PWR signals impressed from the outside of the processor. As a result, instruction codes are successively sent out from the addresses of the internal and external program memories 2a and 2b through internal and external program buses to an instruction register 3 and instructions are executed in an arithmetic part 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention selects one of an internal program memory in a processor for performing arithmetic processing and an external program memory outside the processor, and selects a predetermined address of the selected program memory. It is possible to start the instruction execution of the program from, and select one of the internal program memory inside the processor or the external program memory outside the processor, and execute the program from any predetermined address of the selected program memory. The present invention relates to a processor having an external program memory capable of storing.

[0002]

2. Description of the Related Art A processor TMS320 series manufactured by TI (Texas Instruments) Co., Ltd. has a built-in program memory for storing programs such as arithmetic operations (hereinafter, simply referred to as programs) (hereinafter, this program The memory is referred to as an internal program memory.) In addition to the internal program memory, an external program memory is provided outside the processor to store a large-capacity program of the same type or a different type from the program stored in the internal program memory. In addition, a program memory control unit capable of issuing a program reading or writing command to an internal program memory or an external program memory is provided.

FIG. 4 is a schematic block diagram of the periphery of a processor provided with such an external program memory. Here, the description of the signals used below is summarized in Table 1.

[0004]

[Table 1]

In this configuration, the operation from the reading of the program from the internal program memory or the external program memory to the execution of the program by the arithmetic unit (not shown) will be described in section (A). It is assumed that programs are stored in advance in the internal program memory and the external program memory.

(A) First, in reading a program from the internal program memory, if the internal program memory is selected by an IN / EXT signal applied to the program memory control unit from outside the processor, the program memory control unit will select the internal program memory. The internal program memory is selected by sending a CS signal to. Normally, each program memory has an IR from the program memory control unit.
The D signal and the ERD signal are applied, and the program is sequentially read from the start address of the internal program memory by the IRD signal and the CS signal in the internal program memory, and this program is sent to the instruction decoder via the instruction register. Is
The calculation unit executes a calculation according to the content of such a program.

On the other hand, in reading the program from the external program memory, when the external program memory is selected by the IN / EXT signal applied to the program memory control unit from outside the processor, the program memory control unit causes the external program memory to send the CS signal. To select the external program memory. Here, similar to the above, the IRD signal and the ERD signal are applied to each program memory from the program memory control unit, and the program is sequentially read from the start address of the external program memory by the ERD signal and the CS signal in the external program memory. The program is issued and sent to the instruction decoder via the instruction register, and the arithmetic unit executes the arithmetic operation according to the content of the program.

Next, the operation of writing the program to the internal program memory or the external program memory is performed (B).
Explain in the column.

(B) In writing a program to the internal program memory, if the internal program memory is selected by an IN / EXT signal applied to the program memory control unit from outside the processor, the program memory control unit will be stored in the internal program memory. The CS signal is sent to select the internal program memory, whereby the program for writing is once read from the internal program memory. The content of the read program is an instruction to apply the IWR signal and the EWR signal to the internal program memory and the external program memory from the program memory control unit, and the program is sent to the instruction decoder via the instruction register. Sent out. After that, the command of the program is sent to the program memory control unit, and the program memory control unit sends the IWR signal and the EWR signal to the internal program memory and the external program memory in place of the IRD signal and the ERD signal. Apply.

Thus, in the internal program memory, I
The program is sequentially written from the head address of the internal program memory by the WR signal and the CS signal.

On the other hand, when writing a program to the external program memory, if the external program memory is selected by the IN / EXT signal applied to the program memory control unit from outside the processor, the program memory control unit causes the external program memory to CS A signal is sent to select the external program memory, and the program for writing is once read from the external program memory. The content of the read program is an instruction to apply the IWR signal and the EWR signal to the internal program memory and the external program memory from the program memory control unit, and the program is sent to the instruction decoder via the instruction register. Sent out. After that, the command of the program is sent to the program memory control unit, and the program memory control unit sends the IWR signal and the EWR signal to the internal program memory and the external program memory in place of the IRD signal and the ERD signal. Apply.

Thus, in the external program memory, I
The program is sequentially written from the head address of the external program memory by the WR signal and the CS signal.

As described above, since the conventional processor is used only for a limited purpose, the internal program memory or the external program memory itself is selected,
It was sufficient to read or write the program from the start address.

[0014]

However, although the use of the processor has been diversified today, for example, in an answering machine and a mobile phone, in the conventional processor, the read address of the internal program memory or the external program is read. There is a problem in that the program cannot be read or written by arbitrarily specifying.

[0015]

SUMMARY OF THE INVENTION Therefore, the present invention has been made in view of the above-mentioned problems, and is provided in an internal program memory for storing a program, which is provided in a processor for performing arithmetic processing, and provided outside the processor. And an external program memory for storing a program of the same type as or different from the program, and a program memory control unit for designating an arbitrary address of the internal program memory or the external program memory.

According to the present invention, there is provided an internal program memory which is provided in a processor for performing arithmetic processing and stores a program, and an external program memory which is provided outside the processor and stores a program of the same kind as or a different kind of the program. , A program memory switching signal (IN / EX) applied from the outside of the processor to select one of the internal program memory and the external program memory provided in the processor after a predetermined signal is generated.
T signal) and an execution start area designating signal (EMSEL0 signal, EMSEL1 signal) applied from outside the processor to designate a program reading area of the internal program memory or the external program memory. A program memory selection signal (PCS signal) for selecting a program memory to be read from the internal program memory or an external program memory, and an arbitrary program memory to be read from the program. A program memory control unit for applying an address designation signal (PA signal) for designating an address to the internal program memory or an external program memory.

Further, according to the present invention, an internal program memory, which is provided in a processor for performing arithmetic processing and is capable of storing a program, and an external program, provided outside the processor, store programs of the same kind or different kinds. And an external program memory capable of controlling the program memory switching signal (IN) applied from outside the processor to select one of the internal program memory and the external program memory provided in the processor.
/ EXT signal) and the internal program memory or the external program memory to specify a program writing area, the execution start area designating signals (EMSEL0 signal, EMSE) applied from outside the processor.
L1 signal), a program memory selection signal (PCS signal) for selecting a program memory to be programmed from the internal program memory or the external program memory, and the program writing It is characterized by comprising a program memory control unit for applying an address designation signal (PA signal) designating an arbitrary address of a target program memory to the internal program memory or an external program memory.

[0018]

According to the above means, the external program memory,
Alternatively, the program is read or written from an arbitrary address of the selected program memory among the internal program memories.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1 to 3, and the types of signals used in the embodiments of the present invention and a description of the signals are defined in Table 2 in advance. IN / E
Since the XT signal is the same as the conventional one, the explanation is omitted here. Further, the “program memory switching signal” described in the claims is an IN / EXT signal, and the “execution start area designation signal” is an EMSEL0 signal and EMSEL1.
Signal and "program memory selection signal" means PCS
Signals, and "addressing signals" refer to PA signals, respectively.

[0020]

[Table 2]

FIG. 1 is a schematic configuration diagram of a peripheral of a processor including a program memory control unit of the present invention.

In FIG. 1, 1 is a program counter in which the address of the program to be executed next is stored, 2
a is an internal program memory in which instruction codes of programs are stored, 2b is an external program memory in which instruction codes of programs of the same type or different types from the programs stored in the internal program memory 2a are stored, 3 Is an instruction register for temporarily reading and storing the instruction code stored in the internal program memory 2a or the external program memory 2b, 4 is an instruction decoder for decoding the instruction code stored in the instruction register 3,
Reference numeral 5 is an immediate data register in which immediate data is stored, 6 is a data memory in which operation data is stored, 7 is an address register for designating an address when reading / writing data in the data memory 6, and 8 is an instruction decoder. According to the instruction code decoded in 4, the arithmetic unit for executing the arithmetic processing by using the arithmetic data in the data memory 6, 9 is transmitted via the data bus in accordance with the instruction decoded by the instruction decoder 4. Data register for storing the calculation data, 10 is an accumulator for accumulating and storing the calculation result performed by the calculation unit 8, 11 is an IN / EXT signal, and an internal program memory by the PCS signal according to the EMSEL0 signal and the EMSEL1 signal. 2a,
Alternatively, the external program memory 2b is selected and the internal program memory 2a or the external program memory 2b is selected.
Is a program memory control unit for designating an address for reading or writing the program.

Here, the selection of the internal program memory 2a or the external program memory 2b by the IN / EXT signal and the read start address of the internal program memory 2a or the external program memory 2b by the combination of the EMSEL0 signal and the EMSEL1 signal, or Table 3 shows the write start addresses.

[0024]

[Table 3]

Here, according to the configuration of FIG. 1, a schematic operation from the reading of the program from the internal program memory 2a to the arithmetic processing in the arithmetic unit 8 will be described.

First, the address of the program counter 1 is synchronized with the rising edge of the clock, and the address of the internal program memory 2a in which the instruction to be executed next is stored is generated.

In accordance with the address of the program counter 1, the instruction code of the program is sent from the internal program memory 2a to the instruction register 3, the instruction register 3 loads the instruction code, and the instruction code is read by the instruction decoder 4 and It is sent to the immediate data register 5.

Next, the instruction decoder 4 increments the address to the address register 7,
Alternatively, a control command such as decrement is sent. According to this, the address data is sent from the address register 7 to the data memory 6, the data of the data memory 6 corresponding to this address data is read out, and then the data is sent to the data register 9 or the like via the data bus. To be done.

The arithmetic unit 8 performs arithmetic processing using the arithmetic data stored in the data register 9. The processing result is temporarily stored in the accumulator 10 and then sent / stored in the data memory 6 as appropriate. .

Further, when the arithmetic processing is continued, the arithmetic data stored in the data memory 6 is sent to the data register 9, and the arithmetic unit 8 uses this arithmetic data.
The arithmetic processing is continued and the final arithmetic result at this time is stored in the data memory 6 from the accumulator 10 to complete the series of arithmetic processing.

Next, the connection relationship of signals used when reading or writing a program stored in the internal program memory 2a or the external program memory 2b from an arbitrary preset address will be described in detail.

In FIG. 1, the program memory control unit 1
1 is the internal program memory 2a or the external program memory 2 depending on the type of IN / EXT signal applied from outside the processor during the reset period by the RESET signal.
A PCS (program chip select) signal for selecting b is sent to the internal program memory 2a or the external program memory 2b.

At the same time, the program memory controller 11
Is the EMSEL0 signal and EMSEL1 signal applied from outside the processor, and PA (program address)
The instruction execution start address of the program memory selected by the signal, the PRD (program read) signal, and the PWR (program write) signal can be designated.

In the following, 4 of the external program memory 2b will be used.
The operation at the time of reading the program from the address 000 will be described in the section (C) according to the timing chart of FIG. 2, and the operation at the time of writing the program at the address 4000 of the external program memory 2b will be described in accordance with the timing chart of FIG. ) Column. (C) Reading of Program from External Program Memory 2b First, IN / applied to the program memory control unit 11
When the EXT signal is set to "1", the EMSEL0 signal is set to "0", and the EMSEL1 signal is set to "0", respectively, in synchronization with the clock (hereinafter, referred to as CLK) a generated by the program counter 1, the external The selection command for the program memory 2b is applied to the program memory control unit 11. At the same time, the PA signal sent from the program counter 1 specifies the instruction execution start address 4000 of the external program memory 2b (see the PA signal d in FIG. 2). At this point, the instruction execution start address 400 of the external program memory 2b is simply changed by the PA signal.
Only address 0 is specified.

Next, in synchronization with CLKb generated by the program counter 1, the PCS signal and the PRD signal sent from the program memory control unit 11 are set to "0", so that the external program memory 2b is stored. To be selected.

As a result, the instruction code is sequentially sent from the instruction execution start address 4000 of the external program memory 2b to the instruction register 3 by the PD signal via the external program bus, and the instruction is executed by the arithmetic unit 8. (D) Writing of Program to External Program Memory 2b First, IN / applied to the program memory control unit 11
When the EXT signal is set to "1", the EMSEL0 signal is set to "0", and the EMSEL1 signal is set to "0", the selection command of the external program memory 2b is applied to the program memory control unit 11.

Next, in synchronization with CLKe generated by the program counter 1, the PA signal transmitted from the program counter 1 specifies the instruction execution start address 0001 of the external program memory 2b, and the instruction from the external program memory 2b is designated. The code is read. This instruction code is a program write instruction, and is sent to the instruction decoder 4 via the instruction register 3.

In synchronization with CLKf, the IN / EXT signal "1" causes the PCS signal sent from the program memory control unit 11 to once become active low, thereby selecting the external program memory 2b. At the same time, when the EMSEL0 signal is "0" and the EMSEL1 signal is "0", the PA signal sent from the program counter 1 specifies the instruction execution start address 4000 of the external program memory 2b. At the same time, the PWR signal becomes active low once in synchronization with CLKf, and the program can be written.

As a result, the instruction code is PD from the instruction execution start address 4000 in the external program memory 2b.
The signal is sent to the instruction register 3 via the external program bus, and the arithmetic unit 8 executes the instruction.

In the above embodiment, during the reset period, when the IN / EXT signal is "1", EMSEL0 is "0", and EMSEL1 is "0", the program is read from the 4000th address of the external program memory 2b. Although the write operation has been described, the present invention is not limited to this, and as shown in Table 2, IN / EXT signal, EMSEL, and
The program execution start address of the external program memory 2b can be set to "8000", "C000", and "0" by setting the 0 signal and the EMSEL1 signal.

[0041]

As is apparent from the above description, according to the present invention, in addition to the internal program memory provided in the processor, a program having an external program memory outside the processor can be used to store the program after generation of a predetermined signal. One of external program memory or internal program memory can be selected for execution,
When an external program memory is selected, execution of the program in the external program memory can be arbitrarily started from a preset address, and as a result, multiple types of programs exist in the internal program memory or the external program memory. You can improve the variety of using the program.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a peripheral of a processor including a program memory control unit of the present invention.

FIG. 2 is a timing chart regarding reading of a program from an external program memory 2b according to the present invention.

FIG. 3 is a timing chart regarding writing of a program in an external program memory 2b according to the present invention.

FIG. 4 is a schematic configuration diagram of a peripheral of a processor including an external program memory according to the related art.

[Explanation of symbols]

 1 Program Counter 2a Internal Program Memory 2b External Program Memory 3 Instruction Register 4 Instruction Decoder 5 Immediate Data Register 6 Data Memory 7 Address Register 8 Operation Unit 9 Data Register 10 Accumulator 11 Program Memory Control Unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Yoshida 2-5-5 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (4)

[Claims] 1. An internal program memory for storing a program, which is provided in a processor that performs arithmetic processing, an external program memory, which is provided outside the processor, for storing a program of the same type or a different type of the program, and the processor. A processor having an external program memory, comprising: a program memory control unit which is provided inside and which specifies an arbitrary address of the internal program memory or the external program memory. 2. An internal program memory for storing a program, which is provided in a processor that performs arithmetic processing, an external program memory, which is provided outside the processor, for storing a program of the same kind as or a different kind of the program, and the processor. Is provided inside, and after the predetermined signal is generated,
A program memory switching signal (IN / EXT signal) applied from outside the processor to select one of the internal program memory and the external program memory, and the program of the internal program memory or the external program memory. In response to both signals of the execution start area designating signal (EMSEL0 signal, EMSEL1 signal) applied from outside the processor to designate the reading area, the program reading from the internal program memory or the external program memory is performed. A program memory selection signal (PCS signal) for selecting a target program memory and an address designation signal (PA signal) for designating an arbitrary address of the program memory as a target for reading the program are used as the internal program memory, or Is external Processor with external program memory, characterized by comprising: a program memory controller applied to the program memory. 3. The processor having an external program memory according to claim 2, wherein the predetermined signal is a reset signal or a trigger signal. 4. An internal program memory provided in a processor for performing arithmetic processing and capable of storing a program, and an external program provided outside the processor and capable of storing a program of the same type or a different type from the program. External program memory and a program memory switching signal (IN / EXT signal) applied from outside the processor to select one of the internal program memory and the external program memory provided in the processor, and Execution start area designation signals (EMSEL0 signal, EMSEL1 signal) applied from outside the processor to designate a program writing area to the internal program memory or the external program memory.
In accordance with both signals, a program memory selection signal (PCS signal) for selecting a program memory to be written in the internal program memory or an external program memory, and an object to be written in the program. An external program memory, characterized by comprising: an address designating signal (PA signal) designating an arbitrary address of the program memory; Processor.