JPH07302221A - Digital circuit - Google Patents

Abstract

PURPOSE:To provide a digital circuit capable of more efficiently executing data transfer. CONSTITUTION:This circuit is provided with a central processing unit (CPU) 101, a ROM 105 connected to the CPU 101, an arithmetic means 102 for receiving data from the CPU 101 and executing a prescribed arithmetic operation by using the received data, a RAM 106, a selector for selectively connecting the CPU 101 and the RAM 106 or the arithmetic means 102 and the RAM 106 and connecting the arithmetic means 102 and the RAM 106 while prescribed signals are inputted and a control means for controlling the data transfer from the arithmetic means 102 to the RAM 106 while the prescribed signals are inputted. The CPU 101 outputs the prescribed signals to the selector and the control means at the time of accessing the ROM 105.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital circuit having a central processing unit (hereinafter referred to as CPU).

[0002]

2. Description of the Related Art Conventionally, the problems to be solved by the invention
As shown in FIG. 1, a central processing unit (hereinafter referred to as CP
U) 101, ROM 105, RAM 106
In a digital circuit including at least an arithmetic unit 102 that executes a predetermined arithmetic process according to an instruction from the CPU 101, the arithmetic result data is stored in the RAM 1 in order to store the result data of the arithmetic operation executed by the arithmetic unit 102.
When transferring to 06, the following processing was performed. As shown in the time chart of FIG. 2, the arithmetic unit 102 outputs an interrupt signal (hereinafter referred to as IRQ signal) to the CPU 101 when the arithmetic processing is completed. Upon receiving the IRQ signal, the CPU 101 specifies the address in which the jump address of the interrupt process is stored in the ROM 105 (indicated by "vector" in FIG. 2), and executes the interrupt processing routine from the jump address of the interrupt process. To do. Next, before the actual interrupt processing is executed, the CPU 10
1 designates the address in which the operation result is stored to the arithmetic unit 102 and reads the arithmetic result data from the arithmetic unit 102. Next, the CPU 101 writes an operation result data in the RAM 106 by designating an address for storing the read operation result data in the RAM 106. In the conventional data transfer method, since the operation of storing the operation result in the RAM 106 is performed after the call of the jump destination address of the interrupt processing, the CPU 101 causes the RAM 101 to operate.
The interrupt process must be executed after the data of the operation result is stored in. For this reason, it is not possible to execute interrupt processing promptly.

An object of the present invention is to provide a digital circuit which can transfer data more efficiently.

[0004]

According to a first aspect of the present invention, there is provided a digital circuit including a central processing unit (hereinafter referred to as CPU), a ROM connected to the CPU, data received from the CPU, and received data. An arithmetic means for executing a predetermined arithmetic operation, a RAM, a CPU and a RAM, or an arithmetic means and a RAM are selectively connected, and the arithmetic means and the RAM are connected while a predetermined signal is input. The CPU is provided with a selector and control means for controlling data transfer from the arithmetic means to the RAM while a predetermined signal is input, and the CPU sends a predetermined signal to the selector and the control means when accessing the ROM. It is characterized by outputting.

According to a second aspect of the present invention, in the digital circuit according to the first aspect, the arithmetic means outputs an interrupt signal to the CPU upon completion of the arithmetic operation, and the CPU receiving the interrupt signal It is characterized in that the ROM is accessed to execute the interrupt processing, and a predetermined signal is output to the selector and the control means.

According to a third aspect of the present invention, there is provided a digital circuit which is an interface for connecting a central processing unit (hereinafter referred to as CPU), a ROM connected to the CPU, and an external device. An interface that outputs an interrupt signal to the CPU in response to an access request, a RAM, a CPU and a RAM, or an interface and a RAM are selectively connected, and the interface and the RAM are connected while a predetermined signal is input. And a control means for controlling data transfer between an external device and a RAM connected via an interface while a predetermined signal is input, and the CPU receiving the interrupt signal executes the interrupt processing. In order to access the ROM, a predetermined signal is output to the selector and the control means. To.

[0007]

In the digital circuit of the present invention, the CPU is the ROM
A predetermined signal is output to the selector and the control means while accessing the. This allows the calculation means and the RAM
Is connected to the RAM from the arithmetic means by the control means
Data transfer to and from is controlled. By doing this, C
It is possible to effectively utilize the period during which the PU is not accessing the RAM to execute the data transfer from the calculation means to the RAM.

[0008] Preferably, the arithmetic means outputs an interrupt signal to the CPU upon completion of the arithmetic. This allows
The CPU accesses the ROM to execute the interrupt processing. Then, the ROM is accessed and a predetermined signal (for example, an interrupt vector fetch signal) is output to the selector and the control means. By doing so, the arithmetic means and the RAM can be connected by effectively utilizing the period during which the CPU is accessing the ROM for interrupt processing, that is, the period during which the RAM is not being accessed. Data transfer by means may be performed.

Further, the digital circuit of the present invention includes an interface for connecting an external device. The interface outputs an interrupt signal to the CPU in response to an access request from an external device. The CPU accesses the ROM in order to execute interrupt processing in response to an access request to the RAM from an external device and causes the control means to output a control signal. By doing so, the interface and the RAM can be connected by effectively utilizing the period during which the CPU is accessing the ROM for interrupt processing, that is, the period during which the RAM is not being accessed. The control means executes data transfer between the external device and the RAM connected via the interface.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The data transfer method of the present invention will be described below in the following order with reference to the accompanying drawings. (1) Digital circuit configuration (1-1) Data transfer from arithmetic unit to RAM (1-2) Data transfer from external device to RAM (1-3) Data transfer from RAM to external device

(1) Configuration of Digital Circuit FIG. 3 is a configuration diagram of a digital circuit of this embodiment. The arithmetic unit 2 outputs an interrupt signal (hereinafter referred to as an IRQ signal) to the CPU 1 and the DMA controller 3 when the arithmetic operation is completed. The I / O 7 sends an IRQ signal to the CPU 1 and the DMA in response to a write request from the external device 50.
The signal is output to the controller 3, and at the same time, a "read" switching signal is output to the DMA controller 3. The I / O 7 also sends an IRQ signal in response to a read request from the external device 50 to the CPU 1 and the DMA controller 3.
And a switching signal of “write” to the DMA controller 3. CPU1 is IRQ
An interrupt vector fetch signal is output to the selector 4 and the DMA controller 3 in response to signal input. CPU
1 is connected to the arithmetic unit 2, the selector 4, and the ROM 5 by the data bus B10. Further, the CPU 1 is connected to the selector 4 and the ROM 5 by the address bus B12.

The selector 4 normally connects the address bus B12 of the CPU 1 to the address bus B11 of the RAM 6 and the I / O.
7 is connected to the address bus B17, and the data bus B10 of the CPU1 is connected to the data buses B13 and I of the RAM6.
/ O7 data bus B18. But the CPU
While 1 is outputting the interrupt vector fetch signal to the selector 4 in response to the input of the IRQ signal from the arithmetic unit 2, the selector 4 sets the data bus B15 of the arithmetic unit 2 to R
The address bus B16 of the DMA controller 3 is connected to the data bus B13 of the AM6 and the address bus B11 of the RAM6. In addition, the CPU1 is the I / O7
While the interrupt vector fetch signal is being output to the selector 4 in response to the input of the IRQ signal from the selector 4, the selector 4 connects the data bus B18 of the I / O 7 to the data bus B13 of the RAM 6 and also the DMA controller. Three
Address bus B16 of RAM6 address bus B11
Connect to.

The ROM 5 receives the IRQ signal from the CPU 1 and the CP 5 during the fetching of the interrupt vector.
In response to the address signal sent from U1 via the address bus B12, the data of the jump destination address of the interrupt processing is sent back to the CPU 1 via the data bus B10.

The arithmetic unit 2 includes a data bus B1 from the CPU 1.
The calculation data is received via 0, and a predetermined calculation is executed based on this data. Then, when the predetermined arithmetic processing is completed, the IRQ signal is output to the CPU 1 and the DMA controller 3. From the DMA controller 3
The operation result is output to the data bus B15 after waiting for the "read" control signal to be sent.

The IRQ signal from the calculator 2 is input to the DMA controller 3. DMA controller 3
Waiting for the interrupt vector fetch signal output from the CPU 1, the control signal of “read” is output to the arithmetic unit 2, the control signal of “write” is output to the RAM 6, and the I / O 7 is output. Outputs a control signal of "access prohibited". Also, DMA
The controller 3 receives the IRQ signal from the I / O 7 and a switching signal for switching between read / write. "Read" together with IRQ signal from I / O7
When the switching signal of is input, the DMA controller 3
Outputs a "read" control signal to the I / O 7, a "write" control signal to the RAM 6, and an "access prohibited" control signal to the arithmetic unit 2. On the other hand, when the "write" switching signal is input from the I / O7 together with the IRQ signal, DM
The A controller 3 outputs a "write" control signal to the I / O 7, a "read" control signal to the RAM 6, and an "access prohibited" control signal to the arithmetic unit 2.

(1-1) Data Transfer from Arithmetic Unit to RAM FIG. 4 is a time chart for data transfer from the arithmetic unit 2 to the RAM 6. Hereinafter, the calculator 2 to the RAM 6
Data transfer to the server will be described. The CPU 1 sends the calculation data to the calculator 2 via the data bus B10. The arithmetic unit 2, which has received the arithmetic data, sends an I signal to the CPU 1 and the DMA controller 3 after a predetermined arithmetic operation is completed.
Output the RQ signal. Upon receiving the IRQ signal from the computing unit 2, the CPU 1 receives the DMA controller 3 and the selector 4
To the CPU interrupt vector fetch signal. The selector 4 keeps the data bus B1 of the arithmetic unit 2 during the period when the interrupt vector fetch signal is input from the CPU 1.
5 is connected to the data bus B13 of the RAM 6, and the address bus B16 of the DMA controller 3 is connected to the address bus B11 of the RAM 6. The CPU 1, which has been separated from the RAM 6 by the selector 4, transfers R via the address bus B12.
An address signal is output to OM5. ROM5 is CPU
In response to the address signal input from 1, the destination address of the interrupt process is sent back to the CPU 1 via the data bus B10. During this time, the DMA controller 3 keeps the arithmetic unit 2
The control signal of "read" is output to the RAM6 and the control signal of "write" is output to the RAM6. Then, the control signal "access prohibited" is output to the I / O7. The arithmetic unit 2 receiving the "read" control signal outputs the arithmetic result to the data bus B
15 to the RAM 6 via the data bus B13. D
The MA controller 3 outputs to the RAM 6 an address signal designating an address for storing the calculation result data from the calculator 2. The RAM 6 is the DMA controller 3
The data of the calculation result sent from the calculator 2 is stored in the address designated by. The actual interrupt handling is
It is started by the CPU 1 calling the jump destination address corresponding to the interrupt processing vector to the ROM 5.
In the above digital circuit, when the CPU 1 receives all the data of the jump destination address of the interrupt vector from the ROM 5 via the data bus B10, the RAM 6 stores all the calculation results of the calculator 2. Therefore, the CPU 1
The interrupt processing routine can be started at the same time as the fly address is called. Therefore, compared with the conventional data transfer method in which the calculation result of the arithmetic unit 2 is written in the RAM 6 after the call of the destination address and the interrupt processing is started after the writing.
It becomes possible to execute interrupt processing more quickly.

(1-2) Data Transfer from External Device to RAM Next, data transfer from the external device 50 to the RAM 6 will be described. The time chart when data is transferred from the external device 50 to the RAM 6 is the same as in FIG. When the external device 50 requests writing, the I / O 7 sends an I / O signal to the CPU 1 and the DMA controller 3.
The RQ signal is output and the "read" switching signal is output to the DMA controller 3. The CPU 1 receiving the IRQ signal from the I / O 7 outputs a CPU interrupt vector fetch signal to the DMA controller 3 and the selector 4. The selector 4 keeps the I / O during the period when the interrupt vector fetch signal is input from the CPU 1.
The data bus B18 of No. 7 is connected to the data bus B13 of the RAM6, and the address bus B16 of the DMA controller 3 is connected to the address bus B11 of the RAM6. Selector 4
Thus, the CPU 1 separated from the RAM 6 outputs an address signal to the ROM 5 via the address bus B12.
The ROM 5 stores the jump address of the interrupt process in response to the address signal input from the CPU 1 on the data bus B10.
It sends back to CPU1 via. DMA controller 3
During this period, it outputs a "read" control signal to the I / O7 and "write" to the RAM6.
The control signal of is output. Further, the control signal of "access prohibited" is output to the arithmetic unit 2. I / O that received a "read" control signal
The data 7 is sent from the external device 50 to the RAM 6 via the data bus B18 and the data bus B13. The DMA controller 3 has an I / O function for the RAM 6.
An address signal designating an address for storing the data output from 7 is output. The RAM 6 stores the data from the external device at the address designated by the DMA controller 3.

The interrupt processing is started by the CPU 1 calling the jump destination address corresponding to the interrupt processing vector to the ROM 5. In the above digital circuit, C
At the time when the PU1 receives all the data of the jump destination address of the interrupt vector from the ROM5 via the data bus B10, all the data from the external device 50 is stored in the RAM6. Therefore, the CPU 1 can start the interrupt processing routine at the same time as calling the destination address. Therefore, the external device 50 is called after the call to the destination address.
It is possible to perform interrupt processing more quickly than in the conventional method of writing the data of (1) into the RAM 6.

(1-3) Data Transfer from RAM to External Device FIG. 5 is a time chart in the case of transferring the data stored in the RAM 6 to the external device 50. Below, RAM6
The case of transferring the data stored in the external device 50 to the external device 50 will be described. In response to a data transfer request from the external device 50, the I / O 7 is connected to the CPU 1 and the DMA controller 3
The IRQ signal is output to. In this case, I / O7
It outputs a "write" switching signal to the DMA controller 3. CPU1 which received the IRQ signal from I / O7
The CPU interrupt vector fetch signal is output to the DMA controller 3 and the selector 4. Selector 4
While the interrupt vector fetch signal is being input from the CPU 1, the data bus B18 of the I / O 7 is connected to the data bus B13 of the RAM 6, and the address bus B16 of the DMA controller 3 is connected to the address bus B11 of the RAM 6. CPU 1 separated from RAM 6 by selector 4
Outputs an address signal to the ROM 5 via the address bus B12. The ROM 5 sends back the jump destination address of the interrupt process to the CPU 1 via the data bus B10 in response to the address signal input from the CPU 1. During this time, the DMA controller 3 "writes" to the I / O 7
The control signal of is output. Further, it outputs a "read" control signal to the RAM 6. further,
The control signal "access prohibited" is output to the arithmetic unit 2. The DMA controller 3 outputs an address signal designating a storage address of data to be sent to the I / O 7 to the RAM 6 via the address bus B16 and the address bus B11. Further, the DMA controller 3 outputs an address signal designating an address for storing the data read from the RAM 6 to the I / O 7 via the address bus B16 and the address bus B17. The I / O 7 which has received the "write" control signal from the DMA controller 3 writes the data stored in the address specified by the DMA controller 3 from the RAM 6 via the data bus B13 and the data bus B18. . The I / O 7 stores the data received from the RAM 6 in the external device 50.

The interrupt process is started when the CPU 1 calls the jump destination address corresponding to the interrupt process vector to the ROM 5. In the above digital circuit, C
The data transfer from the RAM 6 to the external device 50 is completed when the PU 1 receives all the data of the jump destination address of the interrupt processing vector from the ROM 5 via the data bus B10. Therefore, the CPU 1 can start the interrupt processing routine at the same time as calling the destination address. Therefore, it is possible to execute the interrupt process more quickly than the conventional method of writing the data in the RAM 6 to the external device 50 after the call to the destination address.

[0021]

In the digital circuit according to the first aspect of the present invention, the data transfer from the arithmetic means to the RAM can be executed while the CPU is not accessing the RAM. This enables more efficient data transfer.

Further, in the digital circuit according to the second aspect of the present invention, the arithmetic means outputs the CP interrupt signal when the arithmetic operation is completed.
By outputting to U, it becomes possible to perform more rapid data transfer.

According to the digital circuit of claim 3,
Utilizing the period when the CPU is not accessing the RAM,
It is possible to perform data transfer between the external device and the RAM via the interface. This enables more efficient data transfer.

[Brief description of drawings]

FIG. 1 is a configuration example of a conventional digital circuit.

FIG. 2 is a time chart during conventional data transfer.

FIG. 3 is a block diagram of a digital circuit of the present invention.

FIG. 4 is a time chart when data is transferred from a computing unit or an external device to RAM.

FIG. 5 is a time chart when transferring data from the RAM to an external device.

[Explanation of symbols]

 1 ... CPU 2 ... Arithmetic unit 3 ... DMA 4 ... Selector 5 ... ROM 6 ... RAM 7 ... I / O interface 50 ... External device

Claims (3)

[Claims] 1. A central processing unit (hereinafter referred to as a CPU), a ROM connected to the CPU, an arithmetic means for receiving data from the CPU and executing a predetermined arithmetic operation using the received data, and a RAM. The CPU and the RAM, or the arithmetic means and the RAM are selectively connected to each other, and the arithmetic means and the R are operated while a predetermined signal is input.
A selector for connecting the AM and a control means for controlling data transfer from the arithmetic means to the RAM while a predetermined signal is input are provided, and the CPU has the selector and the control means when accessing the ROM. A digital circuit, which outputs a predetermined signal to the digital circuit. 2. The digital circuit according to claim 1, wherein the arithmetic means outputs an interrupt signal to the CPU upon completion of the arithmetic operation, and the CPU which receives the interrupt signal executes a ROM for executing the interrupt processing. A digital circuit which outputs a predetermined signal to the selector and the control means while accessing the. 3. An interface for connecting a central processing unit (hereinafter referred to as a CPU), a ROM connected to the CPU, and an external device,
An interface that outputs an interrupt signal to a CPU in response to an access request from an external device, a RAM, a CPU and a RAM, or an interface and a RAM are selectively connected to each other, and an interface is provided while a predetermined signal is input. The CPU that receives the interrupt signal includes a selector that connects the RAM and a control unit that controls data transfer between the RAM and an external device that is connected through the interface while a predetermined signal is input. A digital circuit characterized in that it accesses a ROM to execute an interrupt process and outputs a predetermined signal to a selector and control means.