JPH0729753Y2 - Electric motor speed controller - Google Patents
Electric motor speed controllerInfo
- Publication number
- JPH0729753Y2 JPH0729753Y2 JP1986085250U JP8525086U JPH0729753Y2 JP H0729753 Y2 JPH0729753 Y2 JP H0729753Y2 JP 1986085250 U JP1986085250 U JP 1986085250U JP 8525086 U JP8525086 U JP 8525086U JP H0729753 Y2 JPH0729753 Y2 JP H0729753Y2
- Authority
- JP
- Japan
- Prior art keywords
- converter
- electric motor
- speed control
- analog signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Control Of Electric Motors In General (AREA)
- Control Of Ac Motors In General (AREA)
Description
【考案の詳細な説明】 A.産業上の利用分野 本考案は、F/V変換器（周波数−電圧変換器）を速度制
御系に持つ電動機の速度制御装置に関する。[Detailed Description of the Invention] A. Field of Industrial Application The present invention relates to a speed control device for an electric motor having an F / V converter (frequency-voltage converter) in a speed control system.
B.考案の概要 本考案は、デイジタル設定値とデイジタル検出値との偏
差をF/V変換器によつてアナログ信号に変換して電動機
駆動用インバータの周波数，電圧を制御する速度制御装
置において、 F/V変換信号を微分要素で一次進み補償しかつ一次遅れ
積分要素でリツプルを低減する補償回路を備えることに
より、 速度制御の応答性及び精度を向上できるようにしたもの
である。B. Outline of the Invention The present invention is a speed control device for controlling a frequency and a voltage of an inverter for driving a motor by converting a deviation between a digital set value and a digital detected value into an analog signal by an F / V converter. By providing a compensating circuit for compensating the F / V converted signal with the first-order lead by the differentiating element and reducing the ripple with the first-order lag integrating element, the response and accuracy of the speed control can be improved.
C.従来の技術 誘導電動機の速度制御装置は、インバータを駆動電源と
して速度フイードバツクによるインバータの出力周波
数，電圧を制御するものが多い。このフイードバツク方
式でしかもアナログ信号によるインバータ制御にした速
度制御装置において、速度設定をコンピユータにより設
定又はデイジタル信号による遠隔設定するために、第３
図に示す構成のものがある。デイジスイツチ等のデイジ
タル設定器１の設定値とパルスピツクアツプ等の電動機
２の速度検出器３の検出値とを比較器４によつて引算
し、この偏差をF/V変換器５によつて電圧信号に変換
し、さらにアンプ６を通してインバータ本体７の周波数
・電圧指令とする。C. Conventional technology In many cases, the speed control device of an induction motor controls the output frequency and voltage of the inverter by the speed feed back using the inverter as a driving power source. In the speed control device using the feedback method and the inverter control by the analog signal, in order to set the speed setting by the computer or remotely by the digital signal,
There is a configuration shown in the figure. The set value of the digital setter 1 such as a daisy switch and the detected value of the speed detector 3 of the electric motor 2 such as a pulse pick-up are subtracted by the comparator 4, and this deviation is converted by the F / V converter 5 into a voltage. It is converted into a signal, and is further used as a frequency / voltage command of the inverter main body 7 through the amplifier 6.
D.考案が解決しようとする問題点 F/V変換器を制御系に持つ速度制御装置において、F/V変
換器５はD/A変換器や積分回路が使用されるが、変換精
度を高くしようとするとその応答遅れが比較的大きくな
り、例えば50〜60msもの遅れになつてしまう。このた
め、従来の制御装置では電動機の速度一定制御が負荷の
変化等による外乱に対して変動し易くなり、可変速制御
を行うものでは応答遅れになる問題があつた。D. Problems to be solved by the invention In the speed control device having the F / V converter in the control system, the F / V converter 5 uses the D / A converter and the integrating circuit, but the conversion accuracy is high. If you try to do so, the response delay becomes relatively large, for example, a delay of 50-60 ms. Therefore, in the conventional control device, the constant speed control of the electric motor is apt to fluctuate with respect to the disturbance due to the change of the load, and the variable speed control causes a response delay.
E.問題点を解決するための手段と作用 本考案は、上記問題点に鑑みてなされたもので、デイジ
タル設定値とデイジタル検出値との偏差をF/V変換器に
よつてアナログ信号に変換し、このアナログ信号によつ
て電動機駆動用インバータの出力周波数，電圧を制御す
る速度制御装置において、前記F/V変換器の出力を入力
とし該F/V変換器の応答遅れを一次進み補償する微分要
素と該F/V変換器の出力に含まれるリツプル分を低減す
る一次遅れ積分要素とを有して前記アナログ信号を得る
補償回路を備え、F/V変換器の精度を下げて応答性を上
げ、補償回路によつて応答性をさらに高めかつリツプル
分の上昇を抑制する。E. Means and Actions for Solving Problems The present invention has been made in view of the above problems. The deviation between the digital set value and the digital detected value is converted into an analog signal by an F / V converter. Then, in the speed control device that controls the output frequency and voltage of the electric motor drive inverter by this analog signal, the output of the F / V converter is input and the response delay of the F / V converter is first-order advanced compensated. A compensating circuit that obtains the analog signal by having a differential element and a first-order lag integration element that reduces the ripple component included in the output of the F / V converter is provided, and the accuracy of the F / V converter is reduced to provide responsiveness. The compensation circuit further enhances the responsiveness and suppresses the rise of ripples.
F.実施例 第１図は本考案の一実施例を示す要部回路図である。F/
V変換器５の出力は補償回路6Aを通してインバータ本体
７の入力としている。この補償回路6Aは、従来のアンプ
６を兼ねるもので演算増幅器OPの入力回路に抵抗R1と、
この抵抗R1に並列に抵抗R2とコンデンサC1の直列回路を
具え、帰還回路に抵抗R3とコンデンサC2の並列回路を具
える。F. Embodiment FIG. 1 is a circuit diagram of essential parts showing an embodiment of the present invention. F /
The output of the V converter 5 is input to the inverter main body 7 through the compensation circuit 6A. This compensating circuit 6A doubles as the conventional amplifier 6 and has a resistor R 1 in the input circuit of the operational amplifier OP.
The resistor R 1 is provided in parallel with a series circuit of the resistor R 2 and the capacitor C 1 , and the feedback circuit is provided with a parallel circuit of the resistor R 3 and the capacitor C 2 .
このような補償回路6Aにおいて、抵抗R1とR3の比はアン
プ６のゲインに合わされるゲイン設定要素にされ、抵抗
R2とコンデンサC1はF/V変換器５の応答遅れを補償する
ための一次進み微分要素にされ、コンデンサC2はF/V変
換器５の出力に含まれるリツプリ分を低減するための一
次遅れ積分要素にされる。In such a compensating circuit 6A, the ratio of the resistors R 1 and R 3 is used as a gain setting element that is matched with the gain of the amplifier 6,
R 2 and the capacitor C 1 are used as first-order lead differential elements for compensating the response delay of the F / V converter 5, and the capacitor C 2 is for reducing the ripple component included in the output of the F / V converter 5. It is a first-order lag integration element.
上述の構成によれば、補償回路6Aによつて、F/V変換器
５の応答遅れ分が進み補償されて少ない遅れになるし、
この補償に加えて入力に含まれるリツプル分の低減にな
る。このことは、F/V変換器５の変換精度を多少犠牲に
した構成にしてその応答性を改善することができ、これ
に加えて微分要素による進み補償で増々応答性を改善す
ることができる。According to the above-described configuration, the compensation circuit 6A causes the response delay of the F / V converter 5 to be advanced and compensated for, resulting in a small delay,
In addition to this compensation, the ripple included in the input is reduced. This makes it possible to improve the responsiveness of the F / V converter 5 by sacrificing the conversion accuracy of the F / V converter 5, and in addition to this, the responsiveness can be improved more and more by the advance compensation by the differential element. .
本実施例による実験結果は、第２図に示すようになり、
F/V変換器５への時刻t0でのステツプ入力（同図ａ）に
対する補償回路6Aの出力は同図（ｂ）に実線で示すT0の
遅れになり、同図（ｂ）に破線で示す従来のF/V変換器
の遅れT1に較べて大幅に改善されたもので、T1＝50〜60
msに対してT0＝16msにすることができた。また、リツプ
ル分は同程度に抑えることができた。The experimental result according to this example is as shown in FIG.
The output of the compensation circuit 6A with respect to the step input to the F / V converter 5 at time t 0 (a in the figure) is delayed by T 0 shown by the solid line in the figure, and the broken line in the figure shows the figure. Compared with the delay T 1 of the conventional F / V converter shown in, T 1 = 50-60
It was possible to set T 0 = 16 ms to ms. Also, the ripple amount could be suppressed to the same level.
G.考案の効果 以上のとおり、本考案によれば、F/V変換器の出力に対
して一次進み微分要素と一次遅れ積分要素を有する補償
回路を備えてアナログ信号を得るようにしたため、周波
数−電圧変換に等価的に応答性高めかつリツプルの少な
い精度良い速度制御を得ることができる効果がある。ま
た、構成上はアンプ６に少しの素子を追加するのみで済
む。G. Effect of the Invention As described above, according to the present invention, since the analog signal is obtained by providing the compensating circuit having the first-order lead differential element and the first-order lag integration element with respect to the output of the F / V converter, the frequency can be obtained. There is an effect that the response can be equivalently improved to the voltage conversion, and accurate speed control with less ripple can be obtained. Further, in terms of configuration, only a few elements need be added to the amplifier 6.
第１図は本考案の一実施例を示す要部回路図、第２図は
第１図におけるF/V変換の入出力波形図、第３図は速度
制御装置の構成図である。 ５…F/V変換器、6A…補償回路、７…インバータ本体。FIG. 1 is a circuit diagram of an essential part showing an embodiment of the present invention, FIG. 2 is an input / output waveform diagram of F / V conversion in FIG. 1, and FIG. 3 is a configuration diagram of a speed control device. 5 ... F / V converter, 6A ... Compensation circuit, 7 ... Inverter body.
Claims (1)
偏差をF/V変換器によってアナログ信号に変換し、この
アナログ信号によって電動機駆動用インバータの出力周
波数，電圧を制御する速度制御装置において、前記F/V
変換器の出力を入力とし該F/V変換器の応答遅れを一次
進み補償する微分要素と該F/V変換器の出力に含まれる
リップル分を低減する一次遅れ積分要素とを有して前記
アナログ信号を得る補償回路を備えたことを特徴とする
電動機の速度制御装置。1. A speed control device for converting a deviation between a digital set value and a digital detected value into an analog signal by an F / V converter, and controlling the output frequency and voltage of an electric motor drive inverter by the analog signal. F / V
With an output of the converter as an input, a differential element for first-order compensation of the response delay of the F / V converter and a first-order lag integration element for reducing the ripple component contained in the output of the F / V converter, and A speed control device for an electric motor, comprising a compensation circuit for obtaining an analog signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986085250U JPH0729753Y2 (en) | 1986-06-04 | 1986-06-04 | Electric motor speed controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986085250U JPH0729753Y2 (en) | 1986-06-04 | 1986-06-04 | Electric motor speed controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62198896U JPS62198896U (en) | 1987-12-17 |
| JPH0729753Y2 true JPH0729753Y2 (en) | 1995-07-05 |
Family
ID=30940488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986085250U Expired - Lifetime JPH0729753Y2 (en) | 1986-06-04 | 1986-06-04 | Electric motor speed controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0729753Y2 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5612882A (en) * | 1979-07-11 | 1981-02-07 | Toyo Electric Mfg Co Ltd | Speed control device with drift compensator |
| JPS57132792A (en) * | 1981-12-25 | 1982-08-17 | Mitsubishi Electric Corp | Control system for induction motor |
| JPS58103896A (en) * | 1981-12-10 | 1983-06-21 | Fuji Electric Co Ltd | Control system for induction motor |
| JPS58218884A (en) * | 1982-06-11 | 1983-12-20 | Teac Co | Motor driving circuit |
| JPS5914383A (en) * | 1982-07-14 | 1984-01-25 | Matsushita Electric Ind Co Ltd | Switching governor unit for dc motor |
| JPS60229691A (en) * | 1984-04-27 | 1985-11-15 | Citizen Watch Co Ltd | Drive circuit for dc motor |
-
1986
- 1986-06-04 JP JP1986085250U patent/JPH0729753Y2/en not_active Expired - Lifetime
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5612882A (en) * | 1979-07-11 | 1981-02-07 | Toyo Electric Mfg Co Ltd | Speed control device with drift compensator |
| JPS58103896A (en) * | 1981-12-10 | 1983-06-21 | Fuji Electric Co Ltd | Control system for induction motor |
| JPS57132792A (en) * | 1981-12-25 | 1982-08-17 | Mitsubishi Electric Corp | Control system for induction motor |
| JPS58218884A (en) * | 1982-06-11 | 1983-12-20 | Teac Co | Motor driving circuit |
| JPS5914383A (en) * | 1982-07-14 | 1984-01-25 | Matsushita Electric Ind Co Ltd | Switching governor unit for dc motor |
| JPS60229691A (en) * | 1984-04-27 | 1985-11-15 | Citizen Watch Co Ltd | Drive circuit for dc motor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62198896U (en) | 1987-12-17 |
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