JPH07297348A - Semiconductor device and lead frame used in manufacture thereof and manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device excellent in multipin and fine pitch formation. CONSTITUTION:A lead frame 4, to which a rectangular-frame-shaped wiring board 4 is attached, is used to manufacture a semiconductor device 1. A tab 5, which supports a semiconductor chip 3, is made smaller than the semiconductor chip 3. A conductor wiring 8 is formed on the surface of the insulating resin in the wiring board 4. The electrode of the semiconductor chip 3 and a wiring pad 7 at the inner side of the conductor wiring 8 are connected with a wire 10. A wiring pad 11 at the outer side of the conductor wiring 8 is connected to the inner end of a lead 9 through a wire 12. The entire body other than the outer end part of the lead 9 is covered with a package 2 comprising resin. The wiring board 4 can form the conductor wiring 8 by etching. Therefore, the fine conductor wiring pattern can be formed, and the formations of the many pins and a fine pitch can be achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a lead frame used for manufacturing the same, and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art Electronic devices are required to have high-density mounting in terms of functions, and to be lightweight, compact, and thin in terms of mounting. Further, in order to reduce the manufacturing cost of electronic components, a resin package (plastic package) made of a resin (resin) that is inexpensive and has high productivity is often used as a package form. For small and thin packages, December 1989 issue of "Electronic Materials" published by the Industrial Research Group, the same year
Issued December 1, P37-P43. This document describes the trend of packages in terms of increasing the number of pins, increasing the size of chips, and reducing the size and thickness of wires, and touches on wire bonding as a technical issue. Is described. The following is an excerpt from the section for pad pitch reduction. "When the number of pins increases, the pads are placed around the chip, which may increase the size of the chip. As shown in Fig. 5, try to simplify and estimate. Expected to appear in the near future. There is 3
Taking the 00-pin class as an example, it is assumed that the chip is square and the pad arrangement dimension a is the pad pitch 16
In the case of 0 μm, it becomes 12 mm. If this becomes 120 μm, it becomes 9 mm, which is a great effect. For this purpose, it is necessary to miniaturize the bonding balls. Pad pitch is 120 μm
If so, the bonding position accuracy is approximately ± 15 to 20.
The diameter of the joining ball must be 80 to 90 μm or less. Is stated. " Note that FIG. 5 shows the relationship between the pad pitch, the lead pitch and the wire length. In addition, the following is an excerpt of the item corresponding to lead pitch reduction. "The lead pitch is
42N of t0.15mm whether pressing or etching
It seems that about 0.2 mm pitch is the limit for the iFe alloy. With this plate thickness, the lead width is about 0.1 mm, which is a half of this, and in order to bond into this, the lead bonding width must also be made stable and small. Is stated. "

On the other hand, it has become more difficult to manufacture a fine lead frame, and as one of the breakthrough means, for example, Japanese Unexamined Patent Publication No. 58-192334 or Shokai 64-64.
A composite lead frame as described in Japanese Patent No. 57641 is known. This composite lead frame has a structure in which an insulating substrate made of a polyimide resin film, an epoxy resin film, or the like is bonded onto a die pad. In this insulating substrate, the conductor layer formed by vapor deposition or foil sticking on the surface of the substrate is etched to form the wiring pattern, so the width and pitch of the inner leads can be made smaller and the lead pattern can be miniaturized. Becomes

On the other hand, in manufacturing a semiconductor device, there is a wire bonding step of connecting the electrodes of the semiconductor chip and the inner ends of the leads with a conductive wire. A wire bonding apparatus is used in this wire bonding process. Regarding the wire bonding equipment (wire bonder), "Electronic Materials" issued by the Industrial Research Committee, issued on November 22, 1991,
It is described in P132 to P135. This document touches on the recognition of semiconductor chips and leads. "In a wire bonder, a fully automatic system equipped with a pattern recognition device was installed several decades ago in order to correct the positions of bonding pads and external leads on the semiconductor chip. Wire bonders have begun to enter the market.When the fully automatic wire bonder was introduced, it took about 0.25s to recognize one point, but now it has achieved 0.05s / 1 point. In addition, in multi-pin products, it is necessary to have a function called a lead locator that corrects the position of each external lead before bonding.When this lead locator appeared, one external lead was recognized. It takes about 0.07 s to reduce the productivity in assembling a multi-pin semiconductor device significantly. De 1
The time required to recognize a book is increased to 0.023 s, which contributes to improved productivity. Is stated. "

Regarding the detection of the bonding pad, "Electronic Materials" published by the Industrial Research Institute, August 1984, 8
It is described on pages 114-115 issued on the 1st of each month. In this document, "Detection of displacement of mounting position of pellets is usually
The position of specific points (plurality) on the pellet is detected, and this is compared with the normal position. As this particular point, bonding pads at specific locations are often used. In this case, in particular, when the number of bonding pads is large, it is quite difficult to select a target pad from a large number of pads. With difficulty. Here are some ideas for this. In the method shown in FIG. 3, pads that form a characteristic triangle are selected from the pads as a reference array in advance. Then, the pellet is photoelectrically scanned to obtain a pad group, three pads are arbitrarily selected from the pad group, the triangle formed by this is compared with the triangle of the preselected reference array, and if correspondence is found,
It is determined that the pads A, B and C are target pads to be obtained. Is stated. "

[0006]

However, in the use of the insulating substrate, the manufacturing yield and reliability are lower than those in the case of the lead frame made of a normal metal, so that the applicant has a special structure. Already applied for a patent for the lead frame and semiconductor integrated circuit device using the same (Japanese Patent Application No. 4-208830, filed on August 5, 1992)
is doing. An example of the semiconductor device proposed by the present applicant will be briefly described. FIG. 14 is a plan view in which a part of the semiconductor device is cut away, and FIG. 15 is a schematic plan view showing electrodes (wiring pads) provided on the surface of the semiconductor chip and position recognition marks for the semiconductor chip. The semiconductor device 1 includes a package 2 made of a resin, a semiconductor chip 3 located at the center of the package 2, a rectangular frame-shaped wiring board 4 arranged so as to surround the semiconductor chip 3, and the semiconductor chip. A tab 5 that is smaller than a semiconductor chip (chip) 3 that supports 3 and a tab suspension lead 6 that is connected to the tab 5 and that supports the wiring board 4 in the middle thereof.
A plurality of leads 9 extending inside and outside the package 2, wires 10 electrically connecting the electrodes of the semiconductor chip 3 and the wiring pads 7 inside the wiring board 4, and the wiring board 4 of the wiring board 4. It is composed of a wiring pad 11 on the outside of the periphery and a wire 12 that electrically connects the inner end of the lead 9 extending near the periphery of the wiring substrate 4. Conductor wirings 8 are formed on the surface of the wiring board 4 from the inside to the outside of the frame. The inside and outside of the conductor wiring 8 become the inside wiring pad 7 and the outside wiring pad 11, respectively. The lead 9 is a gull wing type. In the electrode (wiring pad) 16 of the semiconductor chip 3,
As shown in FIG. 15, some electrodes 16 are used as position recognition marks 15 for chips. The position recognition mark 15 for the chip has a cross-shaped notation at the center. The position recognizing mark 15 for the chip is provided in the upper and lower substantially central portions of the semiconductor chip 3.

In manufacturing such a semiconductor device 1,
After fixing the semiconductor chip 3 to the tab 5, the electrodes of the semiconductor chip 3 and the wiring pads 7 on the inner side of the wiring board 4 are connected by the wires 10 made of gold wires, and the wiring pads 11 on the outer side of the wiring board 4 are connected. The inner end of the lead 9 is connected by a wire 12 made of a gold wire. The wiring board 4 serves as a relay wiring board, and by using it, there is no need to increase the wire length, and the wiring in the middle can be fine wiring.

As shown in FIG. 15, on the semiconductor chip 3, a chip position identification mark 15 is formed by utilizing a part of an electrode (wiring pad) 16 (this chip position identification mark). (15 is provided in each of the upper and lower substantially central portions of the semiconductor chip 3). Further, in the wiring board, a specific lead portion is recognized and the chip and the wiring board are connected by the wire 10. As a result, the reliability of the connection between the semiconductor chip 3 and the wiring pad 7 inside the conductor wiring 8 is high. However, no particular position recognition mark is provided on the wiring board 4. Therefore, it was found that automatic recognition errors frequently occur in the connection between the wiring pad 11 on the outer side of the wiring board 4 and the lead 9, and the connection failure occurs due to the displacement of the bonding position.

An object of the present invention is to accurately grasp the position and orientation of the wiring board when the semiconductor device is manufactured by using the lead frame in which the wiring board serving as the relay board is located at the center of the lead frame. Thus, wire bonding is performed with high yield, and an inexpensive semiconductor device is manufactured. The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[0010]

The outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, the semiconductor device of the present invention is manufactured using a lead frame with a wiring board described below. A plurality of position recognition marks for the wiring board are provided on the wiring board. The lead frame of the present invention includes a rectangular frame body, a tab smaller than a semiconductor chip on which a semiconductor chip located in the center of the frame body is mounted, and a plurality of tabs extending from the frame body and supporting the tab. A tab suspension lead and a plurality of position recognition marks for a wiring board are provided on the surface, the tab surrounds the tab separately, and is bonded to the tab suspension lead, and the frame inner diameter of the frame is larger than that of the semiconductor chip. And a plurality of leads extending from the inner peripheral edge of each side of the frame body to the vicinity of the periphery of the wiring board. Then, in the manufacture of the semiconductor device, after fixing the semiconductor chip on the tab, the position recognition mark for the wiring board provided on the surface of the wiring board is detected, and the detection information and the position recognition mark of the semiconductor chip are detected. Wire bonding is performed based on the detection information and the lead array detection information. That is, wire bonding is performed twice. The first time is a wire connection between the electrodes of the semiconductor chip and the wiring pads inside the wiring board.
The turn is a wire connection between the wiring pad outside the wiring board and the inner end of the lead. Therefore, the manufactured semiconductor device includes a package, a semiconductor chip located at the center of the package, a rectangular frame-shaped wiring board arranged so as to surround the semiconductor chip, and a tab for supporting the semiconductor chip. A tab suspension lead that is connected to the tab and supports the wiring board at an intermediate portion; and a plurality of leads that extend inside and outside the package,
A wire for electrically connecting the electrode of the semiconductor chip and a wiring pad of the wiring board, and a wire for electrically connecting the wiring pad around the wiring board and the inner end of the lead extending near the periphery of the wiring board And a structure in which a plurality of position recognition marks for the wiring board are provided on the surface of the wiring board.

A semiconductor device according to another embodiment of the present invention is
A package, a plurality of leads extending inside and outside of the package, a wiring board located in the package, several leads fixed to support the wiring board, and a wiring board on the wiring board. Wires that electrically connect the electrodes of at least one electronic component (that is, a semiconductor chip) to be fixed and the wiring pads of the wiring board, the wiring pads around the wiring board, and the leads extending near the periphery of the wiring board. A semiconductor device comprising a wire electrically connecting to an inner end, wherein a plurality of wiring board position recognition marks are provided on the surface of the wiring board. A lead frame for manufacturing such a semiconductor device has a plurality of leads extending inward from the inner peripheral edge of each side of a rectangular frame body and a desired size in the central portion of the frame. A plurality of leads, which are extended and connected to the wiring board to support the wiring board, and the inner ends of the remaining leads extend near the periphery of the wiring board. In the lead frame, a plurality of wiring board position recognition marks are provided on the wiring board.

[0012]

In the manufacture of the semiconductor device of the present invention, the lead frame to which the wiring board serving as the relay board is attached is used,
Moreover, since the semiconductor chip and the wiring board are provided with the position recognition mark and the position recognition mark for the wiring board, respectively, the electrodes of the semiconductor chip and the inner wiring pad in the conductor wiring of the wiring board are detected by the detection of these position recognition marks. The wire bonding can be performed with high accuracy on the outer wiring pad and the inner end of the lead in the conductor wiring of the wiring board.

One wiring board is positioned in the center of the lead frame, a semiconductor chip is mounted in the center of the wiring board, the electrodes of the semiconductor chip and the conductor wiring of the wiring board are wire-bonded, and the periphery of the wiring board is surrounded. Also in another embodiment in which the conductor wiring and the inner end of the lead are wire-bonded, by detecting the position recognition mark of the semiconductor chip and the position recognition mark for the wiring board, highly accurate wire bonding without deviation of the wire bonding position can be performed. You will be able to do it.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is a schematic plan view of a partially cut-out semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic explanatory view showing a position recognition mark for a wiring board, and FIG. 3 is A of FIG.
-A sectional view taken along the line A, Fig. 4 is a sectional view taken along the line B-B in Fig. 1, Fig. 5 is a schematic plan view of a lead frame according to an embodiment of the present invention, and Fig. 6 is an embodiment of the present invention. 7 is a plan view showing a lead frame body in a lead frame according to FIG. 7, FIG. 7 is a schematic plan view showing a wiring board in a lead frame according to an embodiment of the present invention, and FIG. 8 is an enlarged schematic plan view of electrodes (wiring pads) of a semiconductor chip. FIG. 9 and FIG. 9 are schematic plan views of a lead frame on which chip bonding and wire bonding are performed.

Resin package type semiconductor device 1 of the present invention
As shown in FIGS. 1, 3 and 4, the package includes a rectangular package 2 and a plurality of leads 9 extending inside and outside the package 2. In this example, the lead 9 protruding from the package 2 has a gull wing shape.

A tab (support) 5 is arranged inside the package 2. A semiconductor chip (chip) 3 constituting an LSI is fixed to the upper surface of the tab 5 via a bonding material 20 made of silver paste or the like. The tab 5 is smaller and rounder than the semiconductor chip 3,
The contact area with the semiconductor chip 3 is reduced. The tab 5 is supported by tab suspension leads 6 extending from the four corners of the rectangular package 2. Tab suspension lead 6
Is cut at the portion protruding from the package at the final stage of manufacturing the semiconductor device 1. In addition, in the semiconductor chip 3, as shown in FIG.
Electrodes (wiring pads) 16 are provided across the columns.
Two of the wiring pads 16 are the position recognition marks 15 for the chip. The position recognition mark 15 for the chip has a cross-shaped mark on its surface. The chip position recognition mark 15 is used as a mark for recognizing the position (orientation) of the semiconductor chip 3.

On the outside of the semiconductor chip 3, a frame-shaped wiring board 4 surrounding the semiconductor chip 3 is arranged. The wiring board 4 comprises an insulating substrate 21 and conductor wiring 8 provided on the surface of the insulating substrate 21. As shown in FIG. 7, the insulating substrate 21 is, for example, a frame body having a thickness of about 50 μm and outer dimensions of about 25 mm × 25 mm. The inner size of the semiconductor chip 3 is separated from the outer shape of the semiconductor chip 3 by several mm.
The insulating substrate 21 is formed of a plate material such as a polyimide resin film, an epoxy resin film, or ceramic. The conductor wiring 8 is formed by selectively etching a copper foil having a thickness of about 18 μm or a copper layer formed by vapor deposition. Each conductor wiring 8 extends from the inner side to the outer side of the frame body, and has a structure having an inner wiring pad 7 and an outer wiring pad 11 on the inner side and the outer side, respectively.

Further, this is one of the features of the present invention. On the surface of the wiring board 4, a plurality of position recognition marks 22 for the wiring board are provided. In this example, as shown in FIG. 7, the position recognition marks 22 for the wiring board are provided at two positions on the upper right and lower left edge portions. The position recognition mark 22 for the wiring board is formed by using the wiring pad 23 as shown in FIGS. 1 and 2, and for example, a ten-character notation is provided in the center.

On the other hand, as shown in FIG. 8, the electrodes (wiring pads) 16 of the semiconductor chip 3 and the wiring pads 7 inside the wiring board 4 are as shown in FIGS. 1, 3 and 4.
It is electrically connected by a wire 10 made of a gold wire. The inner ends of the leads 9 are located near the periphery of the wiring board 4, and the inner ends of the leads 9 and the wiring pads 11 on the outer side of the wiring board 4 are electrically connected by a wire 12 made of a gold wire. Has been done. The tab suspension lead 6 is shown in FIGS.
As shown in FIG. 5 and FIG.
The central part including the part that supports is lowered.
The wiring board 4 is adhered to the island 26 of the tab suspension lead 6 with an epoxy resin adhesive 25. In addition, FIG.
As shown in FIG. 3, the island 26 is formed by a circular projecting portion that projects laterally from a part of the tab suspension lead 6 because the thin tab suspension lead 6 cannot obtain desired adhesiveness. There is.

The position recognition mark 22 for the wiring board is
A recognition pattern (mark) for knowing the misalignment of the wiring board 4 to the lead group and the positional relationship with the semiconductor chip 3.
Becomes As a result, the pattern of the leads 9 input to the wire bonding apparatus, the conductor wiring pattern of the wiring board 4, the electrode pattern of the semiconductor chip 3, the position recognition mark 15 for the chip on the semiconductor chip, and the wiring board on the wiring board 4 are used. From the detection information of the position recognition mark 22,
Highly accurate wire bonding becomes possible. That is,
In the method of manufacturing a semiconductor device of the present invention, that is, the wire bonding method, there is no defective connection of the wire 10 connecting the electrode 16 of the semiconductor chip 3 and the inner wiring pad 7, and the outer wiring pad 11 and the lead 9 are also present. The poor connection of the wire 12 that connects the inner ends of the wires is unlikely to occur, and the reliability of the wire bonding property in the completed semiconductor device 1 of the present invention is high.

Next, the manufacture of such a semiconductor device 1 will be described. When manufacturing the semiconductor device 1 of the present invention, a lead frame 30 as shown in FIG. 5 is prepared. The lead frame 30 includes a lead frame main body 31 shown in FIG. 6 and a frame-shaped wiring board 4 attached to the surface of the lead frame main body 31 with an adhesive 25 (see FIG. 4).

The lead frame body 31 has a thickness of 0.15.
It is manufactured by patterning a Fe-Ni alloy plate or a Cu alloy plate of about mm by etching or pressing. As shown in FIG. 6, the lead frame body 31 includes a pair of outer frames 32 extending in parallel with each other, and a pair of inner frames 33 connecting the pair of outer frames 32 and extending in a direction orthogonal to the outer frame 32. It has a frame structure formed by and. A circular tab (support) 5 having a diameter smaller than that of the semiconductor chip 3 is arranged in the center of the frame, and the tab 5 is a tab suspension lead extending from the wide width portion 34 at the corner of the frame. Supported by 6. In addition, a circular island 26 that projects laterally is provided in the middle of the tab suspension lead 6. The island 26 is provided because when the wiring board 4 is bonded to the tab suspension leads 6 with the epoxy resin adhesive 25, desired adhesiveness cannot be obtained only with the thin tab suspension leads 6. Further, a plurality of leads 9 extend from the inner frame 33 and the outer frame 32 toward the wiring board 4. Also,
In the lead portions extending parallel to each other, each lead 9
Are connected by a dam 27. This dam 27
It is arranged in parallel with the inner frame 33 or the outer frame 32 and is connected to the thick width portion 34 at the corner of the frame. Although not shown, the outer frame 32 of the lead frame body 31 is not shown.
Holes and slots used for positioning and guiding are provided.

As shown in FIG. 7, the wiring board 4 has a rectangular frame-shaped insulating substrate 21 and conductor wirings 8 formed on the surface thereof.
It consists of The diameter of the inner frame of the insulating substrate 21 is larger than the diameter of the semiconductor chip 3 so that no trouble occurs when the semiconductor chip 3 is attached to the tab 5. The outer diameter of the insulating substrate 21 is determined by the lead pattern of the leads 9. The larger the size of the wiring substrate 4, the wider the pitch of the wiring pads 11 outside the conductor wiring 8 and the pitch of the inner ends of the leads 9. As a result, there is more room for wire bonding. The wiring board 4 is, for example, 18 μm.
It is formed of a polyimide resin film or an epoxy resin film having a certain thickness and further ceramics or the like. The conductor wiring 8 provided on the surface of the insulating substrate 21 is formed by selectively etching a copper foil having a thickness of several 10 μm or a copper layer formed by vapor deposition. Each conductor wiring 8 extends from the inner side to the outer side of the frame body, and has a structure having an inner wiring pad 7 and an outer wiring pad 11 on the inner side and the outer side, respectively. Then, a part of the wiring pads 23 is formed on the position recognition mark 22 for the wiring board as described above. In the figure, the position recognition marks 22 for the wiring board are provided on the upper right and lower left of the rectangular frame-shaped wiring board 4.

The wiring board 4 is mounted on the lead frame body 31.
The lead frame 30 as shown in FIG.

Next, chip bonding and wire bonding are performed on such lead frame 30. That is, the semiconductor chip 3 is fixed onto the tab 5 of the lead frame 30 via the bonding material 20 (see FIG. 3). Then, the position recognition mark 15 of the semiconductor chip 3 and the position recognition mark 22 of the wiring board 4 are detected by the wire bonding device. The pattern of the leads 9, the conductor wiring pattern of the wiring board 4, and the electrode pattern of the semiconductor chip 3 are input to the wire bonding device. Therefore, the wire bonding operates with high accuracy based on the input information and the detection information, and the semiconductor chip 3
The electrode 16 and the inner wiring pad 7 are connected by the wire 10, and the outer wiring pad 11 on the wiring substrate 4 is connected.
And the inner end of the lead 9 is connected by a wire 12. As a result,
Since the wire is accurately connected to each wiring pad, the reliability of the wire bondability in the semiconductor device 1 of the present invention is high.

Next, the lead frame 3 which has been assembled
In the case of 0, a predetermined portion is molded by a conventional transfer molding device to form the package 2 (see FIG. 9). After that, the lead frame 30 is removed from the transfer mold, the unnecessary lead frame portion is cut and removed, and lead molding is performed to manufacture the gull wing type semiconductor device 1 as shown in FIG.

[0027]

【The invention's effect】

(1) The semiconductor device of the present invention has a structure in which the wiring board is arranged around the semiconductor chip so as to be separated from each other, and in wire bonding in manufacturing the semiconductor device, the wiring pad inside the conductor wiring of the wiring board and the semiconductor chip Since the electrodes are connected by wires and the wiring pads on the outside of the conductor wiring and the inner ends of the leads are connected by wires, it is possible to form a fine pattern of the conductor wiring in the wiring board. Therefore, the number of leads (pins) can be reduced. The effect that the increase can be achieved is obtained.

(2) In the lead frame used for manufacturing the semiconductor device of the present invention, the lead frame main body is attached with the wiring board serving as a frame-shaped relay board. Since the position recognition mark for a certain wiring board is provided, it is possible to obtain the effect that the position and orientation of the wiring board can be accurately recognized even if the mounting position accuracy of the wiring board with respect to the lead frame body is poor.

(3) In the manufacturing of the semiconductor device of the present invention, as shown in (2) above, a lead frame in which a wiring board provided with a position recognition mark for the wiring board is attached to a lead frame body is used. Therefore, the electrodes of the semiconductor chip and the wiring pads of the wiring board can be accurately connected by the wires, and the wiring pads of the wiring board and the inner ends of the leads can be accurately connected by the wires. An effect that a high semiconductor device can be provided is obtained.

(4) According to the method (3) above, according to the method for manufacturing a semiconductor device of the present invention, since wire bonding can be accurately performed, the yield can be increased.

(5) Due to the above (1) to (4), according to the present invention, the number of pins is increased (highly integrated product having 200 or more input / output signal pins), fine pitch is excellent, and reliability of wire bonding is high. A synergistic effect that a highly reliable semiconductor device can be provided at low cost is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. 10 to 13 are views according to another embodiment of the present invention, and FIG. 10 is a schematic plan view showing a semiconductor device with a part cut away, FIG.
Is a sectional view taken along the line CC of FIG. 10, and FIG. 12 is D of FIG.
FIG. 13 is a schematic plan view showing a lead frame, which is a cross-sectional view taken along the line D. In this embodiment, the semiconductor chip 3 is fixed on a wiring board 4 as a relay board,
Of the wire 1 and the wiring pad 7 inside the conductor wiring 8
The wiring pads 11 on the outside of the conductor wiring 8 and the inner ends of the leads 9 are connected to each other by the wires 12 as well. In addition, the wiring board 4 is attached to the suspension lead 35 with the adhesive 2
It is connected via 5. In such an embodiment, the same effect as the above embodiment can be obtained. The lead may be directly connected to the wiring pad of the wiring board without connecting the lead and the wiring pad of the wiring board with a wire.

In the above description, the invention which was mainly made by the present inventor is the background field of application of LSI.
However, the present invention is not limited to this, and is also applied to, for example, a manufacturing technology of a hybrid integrated circuit device in which a plurality of semiconductor chips or passive components such as chip resistors are mounted on a wiring board. it can.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a partially cut-out semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic explanatory view showing a position recognition mark and the like for a wiring board in a lead frame according to an embodiment of the present invention.

3 is a cross-sectional view taken along the line AA of FIG.

4 is a cross-sectional view taken along the line BB of FIG.

FIG. 5 is a schematic plan view of a lead frame according to an exemplary embodiment of the present invention.

FIG. 6 is a plan view showing a lead frame body in a lead frame according to an exemplary embodiment of the present invention.

FIG. 7 is a schematic plan view showing a wiring board in a lead frame according to an embodiment of the present invention.

FIG. 8 is a schematic plan view showing electrodes (wiring pads) of a semiconductor chip according to an embodiment of the present invention.

FIG. 9 is a schematic plan view showing a diagram in which chip bonding and wire bonding are performed in the lead frame according to the embodiment of the present invention.

FIG. 10 is a schematic plan view showing a partially cut semiconductor device according to another embodiment of the present invention.

11 is a cross-sectional view taken along the line CC of FIG.

12 is a cross-sectional view taken along the line DD of FIG.

FIG. 13 is a schematic plan view showing a lead frame according to another embodiment of the present invention.

FIG. 14 is a schematic plan view showing a partially cut semiconductor device proposed by the present applicant.

FIG. 15 is a schematic plan view showing a position recognition mark provided on a semiconductor chip in a semiconductor device proposed by the present applicant.

[Explanation of symbols]

1 ... Semiconductor device, 2 ... Package, 3 ... Semiconductor chip,
4 ... Wiring board, 5 ... Tab, 6 ... Tab suspension lead, 7 ... Wiring pad, 8 ... Conductor wiring, 9 ... Lead, 10 ... Wire,
11 ... Wiring pad, 12 ... Wire, 15 ... Chip position recognition mark, 16 ... Electrode (wiring pad), 20 ... Bonding material, 21 ... Insulating substrate, 22 ... Wiring board position recognition mark, 23 ... Wiring pad , 25 ... Adhesive, 26 ... Island, 27 ... Dam, 30 ... Lead frame, 31 ... Lead frame main body, 32 ... Outer frame, 33 ... Inner frame, 34 ... Wide part, 35 ... Suspension lead.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Asao Matsuzawa 5-22-1, Kamisuihoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Ltd. (72) Inventor Hiroshi Watanabe 5-chome, Mizumizumoto-cho, Kodaira-shi, Tokyo No. 20-1 Semiconductor Company, Hitachi, Ltd. Semiconductor Division (72) Inventor Toshihiro Shiogetsu 5-20-1, Kamisuihonmachi, Kodaira-shi, Tokyo Within Hitachi Ltd., Semiconductor Division

Claims (6)

[Claims] 1. A package, a semiconductor chip located at the center of the package, a rectangular frame-shaped wiring substrate arranged so as to surround the semiconductor chip, a tab for supporting the semiconductor chip, and the tab. Tab suspension leads that are connected to the wiring board and that support the wiring board at an intermediate portion, a plurality of leads that extend inside and outside the package, and electrically connect the electrodes of the semiconductor chip and the wiring pads of the wiring board. A wire for electrically connecting a wiring pad around the wiring board and an inner end of a lead extending near the circumference of the wiring board, wherein a wiring is provided on the surface of the wiring board. A semiconductor device comprising a plurality of position recognition marks for a substrate. 2. A rectangular frame body, a tab for mounting a semiconductor chip located at the center of the frame body, a plurality of tab suspension leads extending from the frame body and supporting the tab, and a surface thereof. A rectangular frame-shaped wiring board that is provided with a plurality of position recognition marks for the wiring board and that surrounds the tab and is bonded to the tab suspension leads, and has a frame inner diameter larger than that of the semiconductor chip; A lead frame comprising a plurality of leads extending from the inner peripheral edge of each side to the vicinity of the periphery of the wiring board. 3. A rectangular frame body, a tab for mounting a semiconductor chip located at the center of the frame body, a plurality of tab suspension leads extending from the frame body and supporting the tab, and a surface thereof. A rectangular frame-shaped wiring board that is provided with a plurality of position recognition marks for the wiring board and that surrounds the tab and is bonded to the tab suspension leads, and has a frame inner diameter larger than that of the semiconductor chip; A step of preparing a lead frame including a plurality of leads extending from the inner peripheral edge of each side to the vicinity of the periphery of the wiring board; a step of fixing a semiconductor chip to the tab; an electrode of the semiconductor chip and a wiring board; Semiconductor having a step of electrically connecting wiring pads with wires, and a step of electrically connecting the inner ends of leads located near the periphery of the wiring board and the wiring pads of the wiring board with wires A method of manufacturing a device, wherein the wiring board position recognition mark provided on the wiring board is detected before wire connection, and wire bonding is performed based on the detected information. Method. 4. A package, a plurality of leads extending inside and outside of the package, a wiring board located in the package, and a plurality of leads fixed so as to support the wiring board. At least one electronic component fixed on the wiring board, a wire for electrically connecting an electrode of the electronic component and a wiring pad of the wiring board, a wiring pad around the wiring board, and a wire extending near the periphery of the wiring board. A semiconductor device comprising a wire electrically connecting an inner end of an existing lead, wherein a plurality of wiring board position recognition marks are provided on a surface of the wiring board. 5. The semiconductor device according to claim 5, wherein at least one of the electronic components is a semiconductor chip. 6. A lead comprising a plurality of leads extending inward from the inner peripheral edge of each side of a rectangular frame, and a wiring board extending in a desired size in the central portion of the frame. Some of the lead frames are long and connected to the wiring board to support the wiring board, and the inner ends of the remaining leads extend to the vicinity of the periphery of the wiring board. The lead frame is characterized in that a plurality of wiring board position recognition marks are provided on the wiring board.