JPH07297071A - Multilayered grain boundary insulated semiconductor ceramic capacitor - Google Patents

Multilayered grain boundary insulated semiconductor ceramic capacitor

Info

Publication number
JPH07297071A
JPH07297071A JP8675294A JP8675294A JPH07297071A JP H07297071 A JPH07297071 A JP H07297071A JP 8675294 A JP8675294 A JP 8675294A JP 8675294 A JP8675294 A JP 8675294A JP H07297071 A JPH07297071 A JP H07297071A
Authority
JP
Japan
Prior art keywords
layer
electrode layer
reinforcing
ceramic capacitor
electrode layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8675294A
Other languages
Japanese (ja)
Inventor
Iwao Ueno
巌 上野
Yoichi Ogose
洋一 生越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP8675294A priority Critical patent/JPH07297071A/en
Publication of JPH07297071A publication Critical patent/JPH07297071A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors

Abstract

PURPOSE:To restrain the defects inside a sintered body, by making at least the uppermost layer and the lowermost layer of inner electrode layers in a laminate be reinforcing electrode layers which are not electrically connected with outer electrodes. CONSTITUTION:An SrTiO3-Nb2O5-SiO2 based green sheet is cut so as to have a specified size. An inner electrode layer 2a and a reinforcing layer 2b composed of NiO and Li2O3 are screen-printed in a specified size on the green sheet 1. The green sheets 1 are arranged in the upper part and the lower part. Between them, a plurality of the green sheets 1 on which the inner electrode layers 2a are printed, and the green sheets 1 on which the reinforcing electrode layers 2b are printed are stacked, and pressed and fixed by pressure while heated. After the molded object is degreased and calcinated in the air, lower layer part outer electrode layers 3a of the same component as the inner electrodes 2a and the reinforcing electrode layer 2b are spread on both ends of the molded object, and baked in a reducing atmosphere. An upper layer part outer electrode layer 3b of Ag is spread on the lower layer part outer electrode 3a, and printed in the air to obtain a multilayered ceramic capacitor having varistor function.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、通常はコンデンサとし
て電圧の低いノイズや高周波のノイズを吸収する働きを
し、一方パルスや静電気などの高い電圧が侵入した時は
バリスタ機能を発揮することによって、電子機器で発生
するノイズ、パルス、静電気などの異常電圧から半導体
及び電子機器を保護する目的で使用される積層型粒界絶
縁型半導体セラミックコンデンサに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention normally serves as a capacitor for absorbing low-voltage noise and high-frequency noise, while exhibiting a varistor function when high voltage such as pulse or static electricity enters. The present invention relates to a laminated grain boundary insulation type semiconductor ceramic capacitor used for the purpose of protecting semiconductors and electronic devices from abnormal voltages such as noise, pulses and static electricity generated in electronic devices.

【0002】[0002]

【従来の技術】従来、例えばTi過剰のSrTiO3
半導体成分とMnO2−SiO2系の成分を混合したもの
でセラミックスグリーンシートを形成し、NiまたはN
i原子を含む化合物に低原子価のLi、Na、K原子の
うち少なくとも一種類以上を固溶させたものを内部電極
としていた。そしてセラミックスグリーンシートと内部
電極を、セラミックスグリーンシートの相対向する端面
に交互に内部電極が導出されるように積層した積層体
と、導出した内部電極を電気的に接続するように設けた
外部電極とで積層セラミックコンデンサを形成してい
た。
2. Description of the Related Art Conventionally, for example, a mixture of a semiconductor component and a MnO 2 --SiO 2 -based component in SrTiO 3 with excess Ti is used to form a ceramic green sheet, and Ni or N is used.
An internal electrode was formed by dissolving at least one kind of low-valence Li, Na and K atoms in a compound containing an i atom. Then, a laminated body in which the ceramic green sheets and the internal electrodes are laminated so that the internal electrodes are alternately led out to the opposite end surfaces of the ceramic green sheets, and an external electrode provided so as to electrically connect the led out internal electrodes To form a monolithic ceramic capacitor.

【0003】[0003]

【発明が解決しようとする課題】上記従来の構成では、
焼成時のセラミック材料と内部電極材料の体積変化の相
違から、焼結体内部において、デラミネーション、内部
電極切れ、焼結不良などが発生しやすいという問題点を
有していた。
SUMMARY OF THE INVENTION In the above conventional configuration,
Due to the difference in volume change between the ceramic material and the internal electrode material during firing, there is a problem that delamination, internal electrode breakage, sintering failure and the like are likely to occur inside the sintered body.

【0004】そこで本発明は、上記従来の問題を解決
し、焼結体内部の不良がほとんどない優れた積層型粒界
絶縁型半導体セラミックコンデンサを提供することを目
的とするものである。
Therefore, an object of the present invention is to solve the above-mentioned conventional problems and to provide an excellent laminated type grain boundary insulation type semiconductor ceramic capacitor having almost no defects inside the sintered body.

【0005】[0005]

【課題を解決するための手段】この目的を達成するため
に、本発明の積層型粒界絶縁型半導体セラミックコンデ
ンサは、積層体において内部電極層の少なくとも最上層
及び最下層を外部電極と電気的に接続しない補強電極層
とするものである。
In order to achieve this object, a laminated grain boundary insulation type semiconductor ceramic capacitor of the present invention has a laminated body in which at least the uppermost layer and the lowermost layer of internal electrode layers are electrically connected to external electrodes. The reinforcing electrode layer is not connected to.

【0006】[0006]

【作用】上記構成によると、補強電極層を設けることに
より、焼成時の体積変化の相違による残存応力が緩和さ
れ焼結体内部の不良の発生を抑えることができる。
According to the above structure, by providing the reinforcing electrode layer, the residual stress due to the difference in volume change during firing is relieved and the occurrence of defects inside the sintered body can be suppressed.

【0007】[0007]

【実施例】以下、本発明の一実施例について詳しく説明
する。
EXAMPLES An example of the present invention will be described in detail below.

【0008】図1は本発明の一実施例における積層型粒
界絶縁型半導体セラミックコンデンサ(以下、バリスタ
機能付き積層セラミックコンデンサとする。)の一部切
欠斜視図である。また図2は本発明の一実施例における
バリスタ機能付き積層セラミックコンデンサの積層体の
分解斜視図である。そして図3は本発明の一実施例にお
けるバリスタ機能付き積層セラミックコンデンサの製造
工程を示す図である。
FIG. 1 is a partially cutaway perspective view of a laminated grain boundary insulation type semiconductor ceramic capacitor (hereinafter referred to as a laminated ceramic capacitor having a varistor function) according to an embodiment of the present invention. FIG. 2 is an exploded perspective view of a laminated body of a laminated ceramic capacitor with a varistor function according to an embodiment of the present invention. FIG. 3 is a diagram showing a manufacturing process of a monolithic ceramic capacitor with a varistor function in one embodiment of the present invention.

【0009】まず、SrTiO3(Sr/Ti=0.9
7):97mol%、Nb25:1mol%、Mn
2:1mol%、SiO2:1mol%の組成で、ドク
ター・ブレード法などにより厚さ25μmの生シートを
作成し、この生シートを所定の大きさに切断した。
First, SrTiO 3 (Sr / Ti = 0.9
7): 97 mol%, Nb 2 O 5 : 1 mol%, Mn
A raw sheet having a composition of O 2 : 1 mol% and SiO 2 : 1 mol% and having a thickness of 25 μm was prepared by a doctor blade method or the like, and the raw sheet was cut into a predetermined size.

【0010】そして所定の大きさに切断された生シート
1の上に、NiO:99.9mol%、Li2CO3
0.1mol%の組成の内部電極層2a、補強電極層2
bを所定の大きさにスクリーン印刷した。
Then, on the green sheet 1 cut into a predetermined size, NiO: 99.9 mol%, Li 2 CO 3 :
Internal electrode layer 2a and reinforcing electrode layer 2 having a composition of 0.1 mol%
b was screen-printed to a predetermined size.

【0011】なお、図2から明らかなように、無効層と
なる最上層及び最下層の生シート1は内部電極層2a及
び補強電極層2bを印刷せず、通常それぞれ複数層積層
される。また、この時、内部電極層2aは、周知のよう
に交互に対向する(異なる)端縁に至るように印刷し、
かつ、補強電極層2bは、下層部外部電極3aに接続し
ないように印刷した。その後、上下に生シート1を配
し、その間に上記内部電極層2aの印刷された生シート
1を複数層そして、上記補強電極層2bの印刷された生
シート1を積層し、加熱しながら加圧、圧着して成形体
を得た。
As is apparent from FIG. 2, the uppermost and lowermost raw sheets 1 which are ineffective layers are not printed with the internal electrode layers 2a and the reinforcing electrode layers 2b, and are usually laminated in plural layers. Further, at this time, the internal electrode layers 2a are printed so as to reach the opposite (different) edges alternately, as is well known.
Moreover, the reinforcing electrode layer 2b was printed so as not to be connected to the lower layer external electrode 3a. After that, the green sheets 1 are arranged on the upper and lower sides, and a plurality of the green sheets 1 on which the internal electrode layers 2a are printed and the green sheets 1 on which the reinforcing electrode layers 2b are printed are laminated between them and heated while heating. A compact was obtained by pressure and pressure bonding.

【0012】次に、この成形体を空気中で1100℃、
2時間で脱脂、仮焼を行った。仮焼後、成形体の両端に
内部電極層2a及び補強電極層2bと同組成よりなる下
層部外部電極層3aを塗布した。塗布後、N2:H2=9
9:1の還元雰囲気中で1230℃で焼成した。焼成
後、下層部外部電極の上にAgよりなる上層部外部電極
層3bを塗布し、空気中で800℃、1時間で焼付ける
ことによりバリスタ機能付き積層セラミックコンデンサ
4を得た。
Next, the molded body was heated in air at 1100 ° C.
Degreasing and calcination were performed in 2 hours. After the calcination, a lower external electrode layer 3a having the same composition as the internal electrode layer 2a and the reinforcing electrode layer 2b was applied to both ends of the molded body. After application, N 2 : H 2 = 9
Baking was performed at 1230 ° C. in a 9: 1 reducing atmosphere. After firing, the upper layer external electrode layer 3b made of Ag was applied on the lower layer external electrode and baked in air at 800 ° C. for 1 hour to obtain a multilayer ceramic capacitor 4 with a varistor function.

【0013】なお、本実施例でのバリスタ機能付き積層
セラミックコンデンサの形状は図1における記号L×W
×Hが2.0×1.25×0.85mmの1.2タイプと
呼ばれるもので、内部電極層2aを3層、補強電極層2
bを上下それぞれ1層ずつ、及び2層ずつ積層したもの
である。また、補強電極層2bの面積は内部電極層2a
の面積の約1.3倍になるようにした。さらに、補強電
極層2bと内部電極層2aの間隔は内部電極層2a間の
間隔と同等にした。
The shape of the monolithic ceramic capacitor with a varistor function in this embodiment is L × W in FIG.
XH is called 2.0 type of 2.0x1.25x0.85mm, 3 internal electrode layers 2a, reinforcing electrode layer 2
b is laminated one layer each on the upper and lower sides and two layers each on the upper side. The area of the reinforcing electrode layer 2b is the same as the internal electrode layer 2a.
The area is about 1.3 times. Further, the distance between the reinforcing electrode layer 2b and the internal electrode layer 2a was made equal to the distance between the internal electrode layers 2a.

【0014】このようにして得られたバリスタ機能付き
積層セラミックコンデンサについて、その容量、tan
δ、バリスタ電圧、電圧非直線指数α、湿中高温課電負
荷寿命特性などの各種電気特性と焼結体内部のビッカー
ス押し込み硬度を、下記の(表1)に併せて記載する。
Regarding the monolithic ceramic capacitor with a varistor function thus obtained, its capacitance, tan
Various electrical characteristics such as δ, varistor voltage, voltage non-linearity index α, high temperature and humidity applied load life characteristics in humidity, and Vickers indentation hardness inside the sintered body are also described in the following (Table 1).

【0015】[0015]

【表1】 [Table 1]

【0016】なお、各種電気特性については以下の測定
値を記載した。 ◇容量Cは測定電圧1.0V、周波数1.0kHzでの
値。 ◇バリスタ電圧V0.1mAは測定電流0.1mAでの値。 ◇電圧非直線指数αは、測定電流0.1mAと1.0m
Aでの値から、 α=1/log(V1/V0.1) の式より算出した。 ◇湿中高温課電負荷寿命特性ΔV0.1mAは85℃、85
%の雰囲気中で5.4Vの直流電流を500時間負荷し
た後のバリスタ電圧V0.1mAの変化率の値。
Regarding the various electrical characteristics, the following measured values are shown. ◇ Capacitance C is a value at a measurement voltage of 1.0 V and a frequency of 1.0 kHz. ◇ The varistor voltage V 0.1mA is the value when the measurement current is 0.1mA. ◇ Voltage non-linearity index α is measured current 0.1mA and 1.0m
From the value at A, it was calculated from the formula α = 1 / log (V 1 / V 0.1 ). ◇ Humidity and high temperature applied load life characteristics ΔV 0.1mA is 85 ℃, 85
% Change rate of varistor voltage V 0.1 mA after a 5.4 V direct current was loaded for 500 hours in an atmosphere of 100%.

【0017】また、比較のため補強電極層が挿入されて
いない従来のバリスタ機能付き積層セラミックコンデン
サについても同様の測定を行った。
For comparison, the same measurement was performed on a conventional laminated ceramic capacitor with a varistor function in which no reinforcing electrode layer was inserted.

【0018】(表1)を見ると補強電極層2bが挿入さ
れている場合では、バリスタ機能とコンデンサ機能の両
機能が安定して発現していることがわかる。また、焼結
体内部観察からも硬度が約2倍に増加し機械強度も向上
していることがわかる。さらに内部電極切れやデラミネ
ーションがまったく観察されなかった。従って、本発明
品は電子機器で発生するノイズ、パルス、静電気などの
異常電圧から、半導体及び電子機器を保護するためバリ
スタ機能付きセラミックコンデンサとして適している。
それに比較し、従来の補強電極層が挿入されていない場
合では安定した電気特性が得られず、焼結体内部にデラ
ミネーションや内部電極切れが多発していた。
It can be seen from Table 1 that both the varistor function and the capacitor function are stably exhibited when the reinforcing electrode layer 2b is inserted. Further, from the observation of the inside of the sintered body, it can be seen that the hardness is about doubled and the mechanical strength is also improved. Furthermore, no breakage of internal electrodes or delamination was observed at all. Therefore, the product of the present invention is suitable as a ceramic capacitor with a varistor function for protecting semiconductors and electronic devices from abnormal voltages such as noise, pulses, and static electricity generated in electronic devices.
In comparison, when the conventional reinforcing electrode layer was not inserted, stable electrical characteristics were not obtained, and delamination and internal electrode breakage occurred frequently inside the sintered body.

【0019】さらに、本発明をする上で、行った実験で
得られた補強電極層の特徴について記述しておく。
Further, the features of the reinforcing electrode layer obtained in the experiment conducted in carrying out the present invention will be described.

【0020】(1)補強電極層2bは上下それぞれ1層
挿入するよりも複数層挿入した方が焼結体強度が向上し
た。
(1) The strength of the sintered body was improved by inserting a plurality of reinforcing electrode layers 2b, rather than inserting one layer above and below.

【0021】これは補強電極層2b数が増えることによ
り残存応力が緩和されやすくなったためであると考えら
れる。
It is considered that this is because the residual stress is easily relaxed by increasing the number of the reinforcing electrode layers 2b.

【0022】(2)補強電極層2bを外部電極に接続し
ないように設けた方が容量成分のバラツキが小さく安定
した値を示した。
(2) When the reinforcing electrode layer 2b was provided so as not to be connected to the external electrode, the variation in the capacitance component was small and a stable value was shown.

【0023】一般的に外部電極に接続させ、かつ容量成
分を発現させない方法としては補強電極層2bがその隣
の内部電極層2aと同電位の状態にすることが容易に想
像できる。しかし、この場合、浮遊容量が発現し設計値
よりも大きい容量を持つ。そして、その浮遊容量の値は
焼結体素子により大きくばらつき必ずしも一定値を示さ
ない。
In general, as a method of connecting to the external electrode and not expressing the capacitance component, it can be easily imagined that the reinforcing electrode layer 2b is set to the same potential as the adjacent internal electrode layer 2a. However, in this case, stray capacitance appears and has a capacitance larger than the design value. The value of the stray capacitance varies widely depending on the sintered body element and does not always show a constant value.

【0024】(3)補強電極層2bと内部電極層2aの
間隔を内部電極層2a間の間隔と同等もしくは広くした
方が焼結体内部組織が均一であった。
(3) The internal structure of the sintered body was more uniform when the distance between the reinforcing electrode layer 2b and the internal electrode layer 2a was equal to or wider than the distance between the internal electrode layers 2a.

【0025】これは間隔が狭い場合にはその部分の焼結
が進み焼結ムラなどの不均一な組織になり電気特性が発
現しにくいことやバラツキが頻繁に起こるためである。
This is because when the interval is narrow, the sintering of the portion progresses to form a non-uniform structure such as sintering unevenness, and it is difficult for the electrical characteristics to be expressed and variations occur frequently.

【0026】(4)補強電極用原料組成と内部電極用原
料組成は同一の方が望ましい。この理由は、異質の場合
では上記(3)と同様に焼結体内部に焼結ムラが発生し
易いためである。
(4) It is desirable that the raw material composition for the reinforcing electrode and the raw material composition for the internal electrode are the same. The reason for this is that in the case of heterogeneous materials, sintering unevenness is likely to occur inside the sintered body, as in (3) above.

【0027】以上のように補強電極層2bの特徴につい
て初期特性、焼結体組織の観点から記載したが、次に、
寿命特性の観点から記載する。
The characteristics of the reinforcing electrode layer 2b have been described above from the viewpoint of initial characteristics and sintered body structure.
It is described from the viewpoint of life characteristics.

【0028】一般的に半導体セラミック素子は比較的気
孔率が大きいために、湿気が容易に浸入し耐湿性寿命特
性が劣化しやすいといった問題点を有する場合がある。
本バリスタ機能付き積層セラミックコンデンサでも耐湿
性寿命特性が劣化し易いという問題点を有する。そこで
本発明に示した補強電極層2bを設けると湿気が補強電
極層2bまでは浸入するが有効層まで進入することな
く、補強電極層2bが湿気の遮断効果を示し、結果とし
て耐湿性寿命特性の劣化が抑制されることを見出した。
従って、新たな特徴として、 (5)補強電極層2bは湿気の遮断効果を示す。そし
て、この場合上下両側にそれぞれ1層設けるよりも複数
層設けた方がより効果が上がる。
In general, since the semiconductor ceramic element has a relatively large porosity, it may have a problem that moisture easily penetrates and the moisture resistance life characteristic is easily deteriorated.
Even this monolithic ceramic capacitor with a varistor function has a problem that the moisture resistance and life characteristics are easily deteriorated. Therefore, when the reinforcing electrode layer 2b shown in the present invention is provided, moisture penetrates up to the reinforcing electrode layer 2b but does not reach the effective layer, and the reinforcing electrode layer 2b exhibits a moisture blocking effect, and as a result, moisture resistance life characteristics. It was found that the deterioration of
Therefore, as a new feature, (5) the reinforcing electrode layer 2b exhibits a moisture blocking effect. In this case, a plurality of layers are more effective than one layer provided on each of the upper and lower sides.

【0029】(6)補強電極層2bの面積は内部電極層
2aの面積と同等もしくはそれ以上の方が耐湿性改善の
効果がより向上する。以上のことが分かった。
(6) When the area of the reinforcing electrode layer 2b is equal to or larger than the area of the internal electrode layer 2a, the effect of improving the moisture resistance is further improved. I found the above.

【0030】上記(1)〜(6)のことに気を付けて製
造したバリスタ機能付き積層セラミックコンデンサは大
容量で、かつ電圧非直線指数αが大きく、さらに耐湿性
寿命特性が優れているため、通常はコンデンサとして電
圧の低いノイズや高周波のノイズを吸収する働きをし、
一方パルスや静電気などの高い電圧が侵入した時はバリ
スタ機能を発揮し、ノイズ、パルス、静電気などの異常
電圧に対して優れた応答性を示し、従来のフィルムコン
デンサ、積層セラミックコンデンサ、半導体セラミック
コンデンサに変わるものとして期待されるものである。
The varistor function-equipped monolithic ceramic capacitor manufactured by paying attention to the above (1) to (6) has a large capacity, a large voltage non-linearity index α, and excellent moisture resistance and life characteristics. , Usually acts as a capacitor to absorb low-voltage noise and high-frequency noise,
On the other hand, when a high voltage such as pulse or static electricity invades, it exhibits a varistor function and exhibits excellent responsiveness to abnormal voltage such as noise, pulse, static electricity, etc., conventional film capacitors, multilayer ceramic capacitors, semiconductor ceramic capacitors. It is expected to change to.

【0031】さらに、本発明のバリスタ機能付き積層セ
ラミックコンデンサは、従来の単板型のバリスタ機能付
きセラミックコンデンサに比べて小型でありながら大容
量であり、かつ高性能であるために、実装部品としての
応用も大いに期待されるものである。
Further, the monolithic ceramic capacitor with a varistor function of the present invention is small in size and has a large capacity and high performance as compared with the conventional single plate type ceramic capacitor with a varistor function, so that it is used as a mounting component. The application of is also highly expected.

【0032】[0032]

【発明の効果】以上のように、本発明の積層型粒界絶縁
型半導体セラミックコンデンサは、積層体において内部
電極層の少なくとも最上層および最下層を補強電極層と
している。
As described above, in the laminated grain boundary insulating semiconductor ceramic capacitor of the present invention, at least the uppermost layer and the lowermost layer of the internal electrode layers in the laminated body are the reinforcing electrode layers.

【0033】その結果、焼成時におけるセラミック層と
内部電極層の体積変化の違いによる残存応力を緩和で
き、焼結体内部の不良の発生を防ぐことができる。
As a result, the residual stress due to the difference in volume change between the ceramic layer and the internal electrode layer at the time of firing can be relaxed, and the occurrence of defects inside the sintered body can be prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における積層型粒界絶縁型半
導体セラミックコンデンサの一部切欠斜視図
FIG. 1 is a partially cutaway perspective view of a laminated grain boundary insulation type semiconductor ceramic capacitor according to an embodiment of the present invention.

【図2】本発明の一実施例における積層体の分解斜視図FIG. 2 is an exploded perspective view of a laminated body according to an embodiment of the present invention.

【図3】本発明の一実施例における積層型粒界絶縁型半
導体セラミックコンデンサの製造工程図
FIG. 3 is a manufacturing process diagram of a laminated type grain boundary insulation type semiconductor ceramic capacitor according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 生シート 2a 内部電極層 2b 補強電極層 3a 下層部Ni外部電極 3b 上層部Ag外部電極 4 積層型粒界絶縁型半導体セラミックコンデンサ 1 Raw Sheet 2a Internal Electrode Layer 2b Reinforcing Electrode Layer 3a Lower Layer Ni External Electrode 3b Upper Layer Ag External Electrode 4 Multilayer Grain Boundary Insulation Semiconductor Ceramic Capacitor

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 セラミック層と内部電極層とを交互に積
み重ねた積層体と、前記積層体の内部電極層を電気的に
接続する外部電極とを備え、前記積層体の内部電極層の
少なくとも最上層と最下層を前記外部電極と接続しない
補強電極層とする積層型粒界絶縁型半導体セラミックコ
ンデンサ。
1. A laminated body, in which ceramic layers and internal electrode layers are alternately stacked, and an external electrode for electrically connecting the internal electrode layers of the laminated body, and at least the innermost electrode layer of the laminated body is provided. A laminated grain boundary insulation type semiconductor ceramic capacitor having upper and lowermost layers as reinforcing electrode layers which are not connected to the external electrodes.
【請求項2】 補強電極層と内部電極層の間隔が内部電
極層間の間隔と同等もしくは広いことを特徴とする請求
項1記載の積層型粒界絶縁型半導体セラミックコンデン
サ。
2. The laminated grain boundary insulation type semiconductor ceramic capacitor according to claim 1, wherein the distance between the reinforcing electrode layer and the internal electrode layer is equal to or wider than the distance between the internal electrode layers.
【請求項3】 補強電極層の面積が内部電極層の面積と
同等もしくは大きいことを特徴とする請求項1記載の積
層型粒界絶縁型半導体セラミックコンデンサ。
3. The laminated grain boundary insulation type semiconductor ceramic capacitor according to claim 1, wherein the area of the reinforcing electrode layer is equal to or larger than the area of the internal electrode layer.
JP8675294A 1994-04-25 1994-04-25 Multilayered grain boundary insulated semiconductor ceramic capacitor Pending JPH07297071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8675294A JPH07297071A (en) 1994-04-25 1994-04-25 Multilayered grain boundary insulated semiconductor ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8675294A JPH07297071A (en) 1994-04-25 1994-04-25 Multilayered grain boundary insulated semiconductor ceramic capacitor

Publications (1)

Publication Number Publication Date
JPH07297071A true JPH07297071A (en) 1995-11-10

Family

ID=13895503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8675294A Pending JPH07297071A (en) 1994-04-25 1994-04-25 Multilayered grain boundary insulated semiconductor ceramic capacitor

Country Status (1)

Country Link
JP (1) JPH07297071A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002015941A (en) * 2000-06-28 2002-01-18 Matsushita Electric Ind Co Ltd Chip-type electronic component
JP2002033236A (en) * 2000-07-13 2002-01-31 Matsushita Electric Ind Co Ltd Chip-type electronic component
KR100593889B1 (en) * 2003-12-24 2006-06-28 삼성전기주식회사 Multilayer Ceramic Capacitors with Reinforcement Patterns

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002015941A (en) * 2000-06-28 2002-01-18 Matsushita Electric Ind Co Ltd Chip-type electronic component
JP2002033236A (en) * 2000-07-13 2002-01-31 Matsushita Electric Ind Co Ltd Chip-type electronic component
JP4581194B2 (en) * 2000-07-13 2010-11-17 パナソニック株式会社 Chip-type electronic components
KR100593889B1 (en) * 2003-12-24 2006-06-28 삼성전기주식회사 Multilayer Ceramic Capacitors with Reinforcement Patterns

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