JPH0728625A - Binary multiplying circuit - Google Patents

Abstract

PURPOSE:To decrease the number of adding steps for multiplication by dividing a multiplier into multibit blocks, performing multiplying processes for multiplying a multiplicand by the respective blocks in parallel, and matching the digit places of the results and performing addition. CONSTITUTION:A block A consisting of the low-order three bits of the multiplicand X and a block B consisting of the low-order three bits of the multiplier Y are inputted to a partial multiplying circuit 1. At the same time, a block C consisting of the high-order three bits of the multiplicand X and the block B consisting of the low-order three bits of the multiplier Y are inputted to a partial multiplying circuit 2, the block A consisting of the low-order three bits of the multiplicand X and a block D consisting of the high-order three bits of the multiplier Y are inputted to a partial multiplying circuit 3, and the block C consisting of the high-order three bits of the multiplicand X and the block D consisting of the high-order three bits of the multiplier Y are inputted to a partial multiplying circuit 4 respectively. Then the respective multiplying circuits 1-4 perform multiplication (AXB, BXC, AXD, and CXD) and the multiplication results are added after the digit places are matched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication circuit for multiplying a multiplicand, which is a binary number, in a semiconductor device and the like, and outputting the result.

[0002]

2. Description of the Related Art Conventionally, for example, in a 6 × 6 bit multiplication circuit as shown in FIG. 3, the multiplication result is obtained by sequentially performing addition of 5 stages to the multiplicand. That is, in the binary n × n bit multiplication, the multiplication result is obtained by sequentially performing addition for the multiplicand by subtracting 1 from each bit number of the multiplier.

[0003]

However, as the number of digits of the multiplier and the multiplicand increases, the number of adding stages increases and the carry propagation delay increases, which tends to significantly increase the processing time.

The present invention has been made in view of the above problems of the prior art, and its main purpose is to multiply a multiplicand, which is a binary number, by a multiplier and output the result. To save time.

[0005]

According to the present invention, the above-mentioned problem is a binary multiplication circuit for multiplying a multiplicand consisting of a binary number and outputting the result, wherein the multiplier is higher than A plurality of partial multiplying circuits for multiplying the multiplicand simultaneously by blocks each having a plurality of bits from the lower order, and an adder circuit for adding the multiplication results of the partial multiplying circuits to each other with their digits aligned with each other are provided. This is accomplished by providing a featured binary multiplier circuit. In particular, it is preferable that the partial multiplication circuit multiplies blocks each having a plurality of bits from the upper or lower part of the multiplicand separately from each other and at the same time, a block having a plurality of bits of the multiplier.

[0006]

As described above, the multiplier is divided into, for example, upper and lower parts, the multiplication processes are performed in parallel, and the results are added together by adding the digits, thereby reducing the number of addition stages in the multiplication. Further, by dividing the multiplicand, the number of multiplication digits of each partial multiplication circuit is reduced, and the number of carry is reduced, so that carry propagation delay is reduced.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

The present embodiment is a 6 × 6 bit multiplication circuit. As shown in FIG. 1, this circuit has four partial multiplication circuits 1 to 4 and an adder circuit 5 for adding the output values from these partial multiplication circuits 1 to 4 with matching digits.
A bus BX for inputting a 6-bit multiplicand X and a bus BY for inputting a 6-bit multiplier Y are connected in parallel to each of the partial multiplication circuits 1 to 4. Here, the lower 3 bits of the multiplicand X and the lower 3 bits of the multiplier Y are input to the partial multiplication circuit 1,
The upper 3 bits of the multiplicand X and the lower 3 bits of the multiplier Y are input to the partial multiplication circuit 2, and the lower 3 bits of the multiplicand X and the upper 3 bits of the multiplier Y are input to the partial multiplication circuit 3. Is input, and the partial multiplication circuit 4 is connected to the buses BX and BY so that the upper 3 bits of the multiplicand X and the upper 3 bits of the multiplier Y are input.

The operating procedure of this embodiment will be described below.

First, when the multiplicand X is sent from the bus BX and the multiplier Y is sent from the bus BY, the block A consisting of the lower 3 bits of the multiplicand X and the block B consisting of the lower 3 bits of the multiplier Y are partial multiplication circuits. Input to 1. At the same time, the block C consisting of the upper 3 bits of the multiplicand X and the block B consisting of the lower 3 bits of the multiplier Y are simultaneously supplied to the partial multiplication circuit 2, and the block A consisting of the lower 3 bits of the multiplicand X and the multiplier Y Of the multiplicand X, the block D consisting of the upper 3 bits of the multiplicand X and the upper 3 of the multiplier Y of the multiplicand X.
The blocks D made up of bits are input to the partial multiplication circuits 4, respectively.

Next, in each of the partial multiplication circuits 1 to 4, FIG.
The multiplication shown in (a) is performed. That is, multiplication of block A × block B, block B × block C, block A × block D, block C × block D is performed. Then, the digits of the respective multiplication results are aligned and added (see FIG. 2).
(B)). At this time, if the multiplication result of block A × block B and the multiplication result of block C × block D are first added, no carry occurs, so that the number of addition stages can be substantially reduced. .

The above calculation means that the calculation of the portions AB, BC, AD and CD in FIG. 2C showing the conventional calculation formula is performed in parallel and the results are added.

Needless to say, the present invention is not limited to the above-mentioned embodiment and various applications are possible. For example, although the multiplicand is also divided in the above-mentioned embodiment, only the multiplier may be divided. In that case, for example, in the case of 6 × 6 bit multiplication, 6 ×
This multiplication circuit can be configured from two 3-bit partial multiplication circuits and one addition circuit, and although carry occurs to some extent, the number of addition stages can be significantly reduced.

[0014]

As described above, according to the present invention, the multiplier is divided into blocks each having a plurality of bits, the multiplication processes for multiplying the multiplicand by each block are performed in parallel, and the results are added with their digits aligned. As a result, the number of addition stages in multiplication can be reduced. Also, by dividing the multiplicand, the number of multiplication digits of each partial multiplication circuit is reduced, and the number of carry is reduced, so that it is possible to shorten the processing time for reducing the carry propagation delay.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a multiplication circuit that is an embodiment of the present invention.

2 (a), (b), and (c) are explanatory views showing multiplication processing by the circuit of FIG.

FIG. 3 is an explanatory diagram showing multiplication processing by a conventional circuit.

[Explanation of symbols]

 1 to 4 partial multiplication circuit 5 addition circuit BX bus for inputting multiplicand X BY bus for inputting multiplier Y

Claims (2)

[Claims] 1. A multiplicand consisting of a binary number is multiplied by a multiplier,
A binary multiplication circuit for outputting the result, wherein a plurality of partial multiplication circuits for multiplying the multiplicand by blocks each having a plurality of bits from the upper or lower bits of the multiplier and the multiplicand at the same time, A binary multiplication circuit, comprising: an addition circuit that adds the multiplication results of the partial multiplication circuits to each other with their digits aligned. 2. The partial multiplication circuit according to claim 1, wherein the blocks each having a plurality of bits from the higher or lower order of the multiplicand are separately and simultaneously multiplied by the blocks having a plurality of bits of the multiplier. Binary multiplication circuit.