JPH0612236A - Circuit and method for multiplication over integer - Google Patents

Abstract

PURPOSE:To provide the circuit and method for efficient multiplication considering carry by using a multiplier with the small number of digits in the case of dividing and calculating the large number of digits in the multiplication circuit. CONSTITUTION:In the circuit to multiply an integer A of (n) bits and an integer B of (hXm) bits while defining (h), (m) and (n) as positive integers, the (h) pieces of arithmetic elements composed of the multipliers of 1Xm bits, the full adders of (m) bits and the registers of (m+2) bits are provided corresponding to the (m) bits of the integer B, and the (m) bits of the integer B are multiplied to every one bits of the integer A and outputted to the (m) bit full adders. The full adders add the outputs of the respective multipliers, the high-order 3 bits of the (m) bit full adders at the low-order digit in the case of the last clock from the register at the low-order digit, and feedback value shifting the low-order m-1 bits of the added result at the full adders in the case of the last clock from the same register to the high-order digit by one digit and supplies the high-order 3 bits to the low-order 3 bits of the full adder at the high- order digit, and the content of the m+2 bit register (n) clock later is defined as a multiplied result A.B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integer multiplication circuit, and more particularly to a circuit and method for performing multiplication with a large number of digits by using a multiplier with a small number of digits. The present invention is an RSA cipher that requires multiplication of a large number of digits (Shinichi Ikeno, Kenji Koyama: "Modern Cryptography", IEICE, 1
It can be used for many integer operations, including encryption techniques such as 980, 6).

[0002]

2. Description of the Related Art In a gate array design or substrate design, a multiplier on an integer having a small number of digits can be easily constructed because a cell library, TTL, etc. are prepared. However, when trying to realize a multiplication circuit with a large number of digits, there is no cell library or the like, so it is necessary to design by yourself. However, in the case of designing a multiplier with a large number of digits by itself, if the circuit configuration of the multiplier with a small number of digits is expanded as it is, the circuit configuration becomes very complicated and difficult to realize.

Further, the input value is divided into predetermined bits and duplicated.
If you want to multiply by a few clocks, you can
Considering that, Galois body (Hiro Miyakawa, Yoshihiro Iwadari, Hideki Imai:
Carriage such as "Code theory", Shokodo, 1973, Chapter 4)
In an arithmetic system without burrs, multiply by a circuit as shown in Fig. 2.
Is known to take place. In Figure 2, * B_i Is B _i 
M bits * m bits with (i = 0, ..., N-1) as a multiplier
The multiplier on the Galois field of G, EX is the EXOR of m bits,
r is an m-bit register.

However, in the multiplication on an integer, carrying out a division operation as shown in FIG. 2 causes a carry for each digit of the division operation, so that it is difficult to realize an efficient multiplier.

[0005]

SUMMARY OF THE INVENTION The present invention eliminates the above-mentioned drawbacks, and when a multiplication circuit divides an input value having a large number of digits for arithmetic operation, a carry with a carry having a small number of digits is used. It is an object of the present invention to provide an efficient integer multiplication circuit and multiplication method in consideration.

[0006]

In order to solve this problem, the multiplication circuit on integers according to the present invention uses n bit integers A and (h × n) when h, m, and n are positive integers. m) A multiplication circuit on an integer which multiplies the bit B by an integer B, wherein the integer A is divided into n clocks for each 1 bit and inputted from the upper digit, and the integer B is assigned to each 1 bit of the integer A. 1-bit × m-bit multiplier connected in parallel to the integer A for multiplying the m-bits, the output of the multiplier, and the m-bit full adder with 2-bit carry of one lower digit at the previous clock. The top 3 bits of m, m + 1 and m + 2 of
The m bit full adder with 2 bit carry and the m bit full adder with 2 bit c A m + 2 bit register connected between the two m-bit full adders with two bit carriers for simultaneously inputting / outputting the m + 2 bit output of the full adder, and multiplying the contents of the m + 2 bit register after n clocks by the result A・ Set to B.

When h, m, and n are positive integers,
A multiplication circuit on an integer for multiplying an n-bit integer A and a (h × m) -bit integer B, which is a 1-bit × m-bit multiplier, a 2-bit m-bit full adder with m + 2 bits, and a register of m + 2 bits. There are h operation elements consisting of and corresponding to predetermined m bits of the integer B. The integer A is divided into n clocks every 1 bit and inputted in parallel from the upper digit to the multiplier. Each one bit is multiplied by a predetermined m bit of an integer B and output to the m-bit full adder. In the m-bit full adder, the output of each multiplier and the previous clock from the register of the lower digit are output. Of the upper 3 bits of m, m + 1 and m + 2 of the m-bit full adder of the lower digit of the hour and the addition result of the m-bit full adder at the previous clock from the register in the same arithmetic element The lower m-1 bit is added to the feedback value obtained by shifting the lower one by one digit, and the register is
The outputs of the m + 2 bits of the m-bit full adder are simultaneously held, the lower m-1 bits are fed back to the m-bit full adder in the same arithmetic element, and the upper 3 bits are the lower 3 bits of the m-bit full adder of the upper digit. It is provided to the bit and the contents of the register of the m + 2 bit after n clocks are taken as the multiplication result A · B.

Here, the m-bit full adder with 2-bit carrier is realized by a plurality of 2-input full adders or half adders.

The multiplication method on integers according to the present invention is based on h,
If m and n are positive integers, n bit integer A and
(H × m) Multiplication on an integer that performs multiplication with the bit integer B
The method consists of a 1-bit by m-bit multiplier and a 2-bit multiplier.
Tobitary m-bit full adder and the full adder
The address is arranged corresponding to the digit of the integer B that stores the output
A memory of at least m + 2 bits having a plurality of regions
And (A) an integer A bit divided into n (A_i )When
An m-bit (B divided by h of integer B)_j ) And 1 bit
(B) Multiply result with the process of multiplying by the multiplier of x m bits
And a predetermined area (R_j-1 ) Top 3 Bits and Places
Constant area (R_j ) Lower m-1 bits and the full adder
And the result of (C) addition in the specified area of the memory.
Area (R_j ) Is stored in the step (A).
(C) for each A_iFor (i = n-1, n-2, ..., 0 order)
B _j Of j from n-1 to 0 is repeated,
The contents of the memory after the entire process is set as the multiplication result A / B.
It

[0010]

In this embodiment, a multiplier of an n-bit integer A and an h · m-bit integer B is assumed, but for simplicity, h =
It will be described as n. This limitation does not lose generality. That is, let us assume that an integer A of n bits and an integer B of n · m bits are used to execute the operation of A · B = C. Here, the multiplication a · b of two integers a and b of m bits
The multiplier for executing = c can be easily realized by a known structure such as a cell library or TTL.

If the integer A is divided by n and the integer B is divided by n, the integer B can be expressed as follows.

A = A _n-1 · 2 ^n-1 + A _n-2 · 2 ^n-2 + ...
+ A ₁・ 2 + A ₀ B = B _n-1・ X ^n-1 + B _n-2・ X ^n-2 + ... + B ₁・ X +
B ₀ Here, X = 2 ^m−1, and n is from the upper digit for A and B.
Each of the divided bit sequences is A _i , B _i (i = n-1,
..., 0). In this case, since the integers A and B can be regarded as polynomials, A · B can be expressed as follows.

[0013]

[Formula 1] A · B = A _n-1 · B · 2 ^n-1 + A _n-2 · B · 2 ^n-2 + ... + A ₁ · B · 2 + A ₀ · B Here, generality is lost Therefore, consider the case of n = 4.

A · B = A ₃ · (B ₃ · X ³ + B ₂ · X ² + B ₁ · X + B ₀ ) · 2 ³ + A ₂ · (B ₃ · X ³ + B ₂ · X ² + B ₁ · X + B ₀ )・ 2 ² + A ₁・ (B ₃・ X ³ + B ₂・ X ² + B ₁・ X + B ₀ ) ・ 2 + A ₀・ (B ₃・ X ³ + B ₂・ X ² + B ₁・ X + B ₀ ) This is shown in FIG. It is composed of a multiplier of a circuit such as. In FIG. 1, A _i (i = n−1, ..., 0) is 1 bit unit and B _i is m.
This is a multiplication circuit in bit units. Figure 1 1 × multiplier 4 m bits and _{(× B 0 ~ × B 3} ) is provided with with 2 Bitsutokiyari m-bit full adder 4 _{(+ 0 ~ + 3),} m +
It is composed of _four 2-bit registers (R _{0 to} R ₄ ). In FIG. 1, the initial state of each register is all “0”.
And

When A ₃ is input at the first clock,
The coefficient A ₃ · B _i (i = 3, ..., 0) of each term in the equation is output from each multiplier and stored in each register through each full adder.

When A ₂ is input at the next clock,
The coefficients A ₂ · B _i (i = 3, ..., 0) of each term in the equation are output from each multiplier. Since the expression is one digit larger than the expression by one digit, the value stored in the register is shifted one bit higher and added with the output from each multiplier representing the coefficient of the expression. Therefore, the lower m-1 bit of each register is shifted to the upper one bit and input to the adder in the feedback back, and the m-th bit of each register is input to the lowest bit of the adder on the right side. Therefore, in the adder, addition of m bits is performed, and if there is a carry, m + 1 bits are output and stored again in the register.

When A ₁ is input at the next clock,
The same operation as when A ₂ is input is performed, but the carry bit of the m + 1th bit of each register is input to the second digit of the adder on the right as a carrier. That is, since the (m + 1) th bit of each register represents the same digit as the least significant bit of the register on the right side, the adder must treat it as the second most significant bit rather than the least significant bit. Therefore, m + 2 bits are output from the adder and stored again in the register. By this,
It means that the addition of the coefficient of each term up to the above formula was performed.

When the last input A ₀ is input at the next clock, the coefficients of the respective terms of the expressions are added by the same calculation, and it means that the multiplication of A and B has been performed. After that, you can continue to input the clock and output the multiplication result A / B from the upper digit of the upper bit of the register of the most significant digit, or you can read the contents of each register to obtain the final multiplication result A / B.
May be created. Thus, when the value of A is divided and input, the calculation of A and B is efficiently performed.

In this example, the integer A is divided by 1 bit,
Although described as n = 4, without loss of generality, the integer A is set to the number of n · m bits divided into m bits, and n and h are extended to arbitrary integer multiplications. In this case, an m-bit by m-bit multiplier is used.

It is also apparent that the carrier full adder in FIG. 1 can be realized by a combination of a plurality of two-input full adders and half adders. Further, it is apparent that the same multiplier can be configured by omitting the register at the right end in FIG. 1 or adding a full adder and a register.

Further, the configuration in which the same arithmetic element (element) consisting of the multiplier (× B _j ) and the full adder (+ _j ) and the register (R _j ) as shown in FIG.
There is also an advantage that it is easy to configure a large-scale circuit such as SI.
Further, it is apparent that the same calculation result can be obtained by using the memory having the plurality of regions R _j and performing the calculation corresponding to the above-mentioned calculation elements by software in order or in parallel. The present invention may be applied to a system including a plurality of devices or an apparatus including a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

According to the present invention, when an input value having a large number of digits is divided and operated in a multiplying circuit, a multiplier having a small number of digits is used, and an efficient integer multiplication circuit considering a carry is provided. A multiplication method can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing an integer multiplication circuit according to the present embodiment.

FIG. 2 is a diagram illustrating a known polynomial multiplication circuit on a Galois field.

[Explanation of symbols]

R ... m + 2 bit register, + ... 2m bit full adder with 2 bit carriers, xB _i ... B _i (i = 0, ..., n)
-1) Multiplier on 1-bit x m-bit integer with multiplier, * B _i ... B _i (i = 0, ..., n-1) with 1-bit * m-bit on Galois field Multiplier, EX ... m bit EXOR, r ... m bit register

Claims (4)

[Claims] 1. When h, m, and n are positive integers, n
A multiplication circuit on an integer which multiplies a bit integer A and a (h × m) bit integer B, wherein the integer A is divided into n clocks for each bit and inputted from the upper digit, and the integer A A 1-bit × m-bit multiplier connected in parallel to the integer A for multiplying each 1-bit by a predetermined m-bit of an integer B, the output of the multiplier, and one lower digit of the last clock. Of 2
The upper 3 bits of m, m + 1 and m + 2 of the m bit full adder with bit carry and the lower m- of the m bit full adder with 2 bit carry of the same digit at the previous clock
M bit full adder with 2 bit carriers and m bit +2 of m bit full adder with 2 bit carriers, which adds 1 bit up to the feedback value
M + 2 connected between the two m-bit full adders with the two bit carriers that simultaneously input and output the bit output
An integer multiplication circuit, comprising: a bit register, wherein the contents of the m + 2 bit register after n clocks are used as the multiplication result A · B. 2. When h, m, and n are positive integers, n
A multiplication circuit on an integer that multiplies a bit integer A and a (h × m) bit integer B by a 1-bit × m-bit multiplier and a 2-bit m
An arithmetic element consisting of a bit full adder and a register of m + 2 bits is set to h corresponding to a predetermined m bit of the integer B.
In the multiplier, the integer A is divided into n clocks every 1 bit and inputted in parallel from the upper digit, and each 1 bit of the integer A is multiplied by a predetermined m bit of the integer B to obtain the m Output to the bit-full adder, and in the m-bit full-adder, the output of each of the multipliers,
The upper 3 bits of m, m + 1, and m + 2 of the m bitful adder of the lower digit from the register of the lower digit at the previous clock, and the m bitfull of the last clock from the register in the same arithmetic element. The lower m-1 bit of the addition result in the adder is added with the feedback back value shifted up by one digit, and the register holds the output of the m + 2 bit of the m-bit full adder at the same time, and stores the lower m-1 bit. Feed back to the m-bit full adder in the same arithmetic element, provide the high-order 3 bits to the low-order 3 bits of the high-order m-bit full adder, and multiply the contents of the m + 2 bit register after n clocks by the multiplication result A. A multiplication circuit on an integer, characterized by B. 3. The m-bit full adder with two bit carriers is realized by a plurality of two-input full adders or half adders.
A multiplication circuit on the described integer. 4. When h, m, and n are positive integers, n
Multiply the bit integer A by (h × m) bit integer B
Multiplying method on integers, with 1-bit × m-bit multiplier and 2-bit carry
memorize m bit full adder and output of the full adder
Has multiple areas where addresses are arranged corresponding to the digits of integer B
Memory having at least m + 2 bits, and (A) an integer A divided into 1 bit (A_i ) And the integer B
h divided m bits (B_j ) And 1 bit x m bits
Step of multiplying by the multiplier of the bridge, (B) multiplication result and a predetermined area (R_j-1 ) Top
3 bits and predetermined area (R_j ) Lower m-1 bits before
The process of adding with the full adder, and (C) the addition result is stored in a predetermined area (R_j )
And the above steps (A) to (C)_i(i = n-1, n-2, ...,
0 order), B _j Of j is changed from n-1 to 0
Repeatedly, multiply the contents of the memory after the whole process
A multiplication method on an integer, wherein the result is A · B.