JPH07282585A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the fetching of erroneous data to a register type input buffer etc., performing an input operation according to a clock signal CLK by suppressing the power source noise of clock signal input buffer IBK receiving the clock signal CLK and stabilizing its level deciding operation. CONSTITUTION:A power source supplying path supplying a power source voltage VCC1 and a grounding potential VSS1 to the clock signal input buffer IBK is provided independently of a power source supplying path supplying a power source voltage VCC2 and a grounding potential VSS2 to other internal circuits. Thus, the power source noise due to charging currents and pass-through currents accompanied by operations of internal circuits is suppressed from being transferred to the power source supplying path of the clock signal input buffer IBK.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique which is particularly effective when used for a synchronous SRAM (static random access memory).

[0002]

2. Description of the Related Art A so-called synchronous SRA whose operation is synchronized according to a clock signal supplied from the outside.
There is M (clocked RAM). Synchronous SRAM
Includes a clock signal input buffer that receives a clock signal, and a so-called register-type input buffer that includes an edge trigger type flip-flop and receives a start control signal such as a chip selection signal and an address signal according to the clock signal.

Regarding a synchronous SRAM including a register type input buffer (input register), for example,
"HM6" issued by Hitachi, Ltd. in October 1993.
7A4101 Series Data Book ”and the like.

[0004]

In the conventional synchronous SRAM described above, even though the clock signal is a basic signal for determining its operation mode and timing, power supply to the clock signal input buffer is provided. The path is substantially shared with the power supply path for other input buffers and memory arrays and their peripheral portions. As is well known, the synchronous SRAM includes a word line, a bit line, a common data line, etc., to which a relatively large load capacitance is coupled, and at the time of selection thereof, a relatively large charge current flows through these signal lines. . Also,
The peripheral part of the synchronous SRAM has P channel and N channel.
A plurality of CMOS (complementary MOS) circuits each including a channel MOSFET (metal oxide semiconductor type field effect transistor; generically referred to as an insulated gate type field effect transistor in this specification) are included, and at the time of operation transition thereof. A relatively large through current is applied. These charge current and shoot-through current induce relatively large power supply noise in the power supply path, and make the level determination operation of the clock signal input buffer unstable when the clock signal is at the intermediate level during the state transition period. To do. As a result, erroneous data is taken into the register type input buffer that receives the start control signal and the address signal, and the synchronous SR
There is a problem that the AM malfunctions and its reliability is reduced.

It is an object of the present invention to suppress power supply noise of an input buffer which receives a basic clock signal, stabilize its level determination operation, and input erroneous data to a register type input buffer or the like which performs an input operation according to a clock signal. Is to prevent the uptake of. Another object of the present invention is to provide a synchronous SRA that operates synchronously according to a clock signal.
The purpose is to prevent malfunction of M and the like and improve its reliability.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a clock signal input buffer that receives an externally supplied clock signal, a register-type input buffer that takes in a start control signal, an address signal, and the like according to the clock signal, and internal circuits such as a memory array and peripheral portions that operate in synchronization with the clock signal In the synchronous SRAM or the like including the above, the power supply path for the clock signal input buffer is provided substantially independently of the power supply paths for the register-type input buffer and other internal circuits.

[0008]

According to the above-mentioned means, the power supply noise due to the charge current and the through current due to the operation of the internal circuits such as the memory array and the peripheral portion is suppressed, and the level judgment operation for the clock signal of the clock signal input buffer is stabilized. be able to. As a result, erroneous data is prevented from being taken into the register type input buffer, and the synchronous SRAM
It is possible to prevent erroneous operations such as the above and improve the reliability.

[0009]

1 is a block diagram showing an embodiment of a synchronous SRAM to which the present invention is applied. An outline of the configuration and operation of the synchronous SRAM of this embodiment will be described first with reference to FIG. The circuit elements forming each block in FIG. 1 are not particularly limited,
By the well-known bipolar CMOS integrated circuit manufacturing technology,
It is formed on one semiconductor substrate such as single crystal silicon.

In FIG. 1, the basic structure of the synchronous SRAM of this embodiment is a memory array MARY which occupies most of the surface of a semiconductor substrate. This memory array MARY is arranged in a grid pattern at a plurality of word lines arranged in the horizontal direction in the drawing, a plurality of sets of complementary bit lines arranged in the vertical direction, and intersections of these word lines and complementary bit lines. And a large number of static memory cells.

The word lines forming the memory array MARY are coupled to the X address decoder XD on the left side thereof and are alternatively set to the selected state. X address decoder X
In D, the complementary internal address signals X0 * to Xi * of i + 1 bits from the X address buffer XB (here, for example, the non-inverted internal address signal X0T and the inverted internal address signal X0B are collectively referred to as the complementary internal address signal X0 *. Is added with *, and for non-inverted signals, etc., which are selectively brought to high level when it is enabled, T is added to the end of the name, and so on. ,
The internal control signal DE is supplied from the timing generation circuit TG. Further, the X address buffer XB is supplied with the X address signals AX0 to AXi (second input signal) through the address input terminals AX0 to AXi (second input terminal), and the timing generation circuit TG receives the input clock signal. BC
K is supplied. The internal control signal DE is selectively set to a high level at a predetermined timing when the synchronous SRAM is selected in the write mode or the read mode. The input clock signal BCK is based on the clock signal CLK (first input signal) input from the clock signal input terminal CLK (first input terminal), and is used as a data input buffer I of the timing generation circuit TG described later.
B (first input buffer), which is an in-phase signal slightly delayed in phase from the clock signal CLK.

The X address buffer XB fetches and holds the X address signals AX0 to AXi externally supplied via the address input terminals AX0 to AXi in accordance with the input clock signal BCK, and complements them based on these X address signals. The internal address signals X0 * to Xi * are formed and supplied to the X address decoder XD. Further, the X address decoder XD receives the high level of the internal control signal DE and is selectively operated, decodes the complementary internal address signals X0 * to Xi *, and outputs the memory array MARY.
The corresponding word line is selectively set to the selected state. In addition,
The X address buffer XB has address input terminals AX0 to AX0.
It includes register-type X address signal input buffers UXB0 to UXBi (second input buffers) provided corresponding to AXi, and the specific configuration thereof will be described in detail later.

Next, the complementary bit lines constituting the memory array MARY are coupled to a Y switch YS below the complementary bit lines, and four sets of them are selectively written via the Y switches YS to write complementary common data lines or read complementary common data lines. Connected to common data line.

The Y switch YS is a memory array MARY.
Of N-channel type and P-channel type switch MOSFET pairs provided corresponding to the respective complementary bit lines.
One of these switch MOSFET pairs is coupled to a corresponding complementary bit line of memory array MARY, respectively. The other of the N-channel type switch MOSFET pairs is coupled to a complementary complementary common data line for writing (not shown) every four pairs, and a P-channel type switch MOSF.
The other of the ET pairs is coupled to the read complementary common data line (not shown) every four pairs. The Y address decoder Y is provided at the gate of the N-channel type switch MOSFET pair.
The corresponding write bit line selection signal is supplied from D, and the corresponding write bit line selection signal is supplied to the gates of the N-channel type switch MOSFET pairs.

As a result, N constituting the Y switch YS is formed.
The channel-type switch MOSFET pairs are selectively turned on by four groups when the corresponding write bit line selection signal is set to the high level, and the memory array MAR
The four complementary bit lines corresponding to Y and the complementary common data line for writing are selectively connected. On the other hand, a P channel type switch MOS which constitutes the Y switch YS
The FET pairs are selectively turned on by four sets when the corresponding read bit line selection signals are set to the low level, and the four pairs of the complementary bit lines and the read complementary common data lines corresponding to the memory array MARY are selectively turned on. The spaces are selectively connected.

The Y address decoder YD is supplied with the j + 1-bit complementary internal address signals Y0 * to Yj * from the Y address buffer YB and the internal control signal DE from the timing generation circuit TG. Further, the Y address buffer YB has Y address signals AY0 to AYj via address input terminals AY0 to AYj (second input terminals).
(Second input signal) is supplied to the timing generation circuit T
The input clock signal BCK is supplied from G.

The Y address buffer YB fetches and holds the Y address signals AY0 to AYj supplied through the address input terminals AY0 to AYj in accordance with the input clock signal BCK and complements them based on these Y address signals. The internal address signals Y0 * to Yj * are formed and supplied to the Y address decoder YD. Further, the Y address decoder YD is selectively operated in response to the high level of the internal control signal DE, decodes the complementary internal address signals Y0 * to Yj *, and selects the corresponding write bit line selection signal. One is set to the high level, or the corresponding read bit line selection signal is selectively set to the low level. The Y address buffer YB is a register-type Y address signal input buffer UYB0 to UYBj provided corresponding to the address input terminals AY0 to AYj.
Although the (second input buffer) is provided, its specific configuration should be inferred from the following description regarding the X address signal input buffers UXB0 to UXBi of the X address buffer XB.

The write complementary common data lines to which the designated four sets of complementary bit lines of the memory array MARY are selectively connected are coupled to the output terminals of the corresponding unit circuits of the write amplifier WA, and read complementary common data lines. The data line is coupled to the input terminal of the corresponding unit circuit of the sense amplifier SA. The input terminal of each unit circuit of the write amplifier WA is coupled to the output terminal of the corresponding unit circuit of the data input buffer IB via the corresponding write data bus WB0 * to WB3 *, and the input terminal of each unit circuit of the sense amplifier SA is connected. The output terminals are corresponding read data buses RB0 * to RB3.
It is coupled via * to the input terminal of the corresponding unit circuit of the data output buffer OB. The input terminal of each unit circuit of the data input buffer IB has a corresponding data input terminal DI0.
To DI3 respectively, data output buffer OB
The output terminal of each unit circuit of is the corresponding data output terminal D
They are respectively coupled to O0 to DO3.

An internal control signal WP is commonly supplied from the timing generation circuit TG to each unit circuit of the write amplifier WA, and an internal control signal SP is commonly supplied to each unit circuit of the sense amplifier SA. The input clock signal BCK is commonly supplied from the timing generation circuit TG to each unit circuit of the data input buffer IB, and the internal control signal DOC is commonly supplied to each unit circuit of the data output buffer OB. Here, the internal control signal WP is selectively set to a high level at a predetermined timing when the synchronous SRAM is selected in the write mode.
Further, the internal control signals SP and DOC are synchronous S
When the RAM is selected in the read mode, it is selectively set to the high level at a predetermined timing.

Each unit circuit of the data input buffer IB is
When the synchronous SRAM is selected in the write mode, the write data supplied via the data input terminals DI0 to DI3 is fetched and held in accordance with the input clock signal BCK, and the write data bus WB is used.
It is transmitted to the corresponding unit circuit of the write amplifier WA via 0 * to WB3 *. At this time, each unit circuit of the write amplifier WA is selectively activated by receiving the high level of the internal control signal WP, and the write data transmitted from the corresponding unit circuit of the data input buffer IB is written in a predetermined complementary manner. After being converted into a signal, the selected 4 of the memory array MARY is transmitted via the corresponding complementary common data line for writing.
Write to each memory cell. The data input buffer IB includes four register-type unit data input buffers UI provided corresponding to the data input terminals DI0 to DI3.
B0 to UIB3 (second input buffer) are provided, and the specific configuration thereof is the X of the X address buffer XB.
Please infer from the following description regarding the address signal input buffers UXB0 to UXBi.

On the other hand, each unit circuit of the sense amplifier SA is
When the synchronous SRAM is brought into the selected state in the read mode, it is selectively brought into the operating state in response to the high level of the internal control signal SP, and the corresponding read complementary from the four memory cells selected in the memory array MARY. After amplifying the minute read signal output via the common data line, it is transmitted to the corresponding unit circuit of the data output buffer OB via the read data buses RB0 * to RB3 *. At this time, each unit circuit of the data output buffer OB receives the high level of the internal control signal DOC and is selectively brought into an operating state, and the read data transmitted from the corresponding unit circuit of the sense amplifier SA is transferred to the data output terminal DO0. ~
Output to the outside of the synchronous SRAM through DO3. The data output buffer OB of this embodiment includes a data latch that holds the read data read in each cycle for one cycle period of the clock signal CLK. As a result, the read data output operation by the data output buffer OB is performed in a form delayed by one cycle period of the clock signal CLK, whereby the relative cycle time of the synchronous SRAM is accelerated.

The timing generation circuit TG has a clock signal CLK supplied via a clock signal input terminal CLK.
And a chip selection signal CSB and a write enable signal WEB (second input signal) supplied as a start control signal through the chip selection signal input terminal CSB and the write enable signal input terminal WEB (second input terminal). In addition, the input clock signal BCK and various internal control signals are selectively formed and supplied to each part of the synchronous SRAM. The timing generation circuit TG includes a clock signal input buffer IBK for receiving the clock signal CLK, a register-type chip selection signal input buffer IBC for receiving the chip selection signal CSB and a write enable signal WEB according to the input clock signal BCK, and a write enable signal input. A buffer IBW (second input buffer) is provided, and the specific configuration of these input buffers will be described in detail later.

Incidentally, the synchronous SR of this embodiment
AM has a power supply voltage supply terminal VCCO and a ground potential supply terminal VSSO for supplying an operation power supply, that is, a power supply voltage VCC (first power supply voltage) and a ground potential VSS (second power supply voltage) to the data output buffer OB. , A power supply voltage supply terminal VCC (first power supply terminal) and a ground potential supply terminal VSS (second power supply terminal) for supplying the power supply voltage VCC and the ground potential VSS to the internal circuits except the data output buffer OB, respectively. And a power supply voltage V
A constant voltage generation circuit VCSG for supplying a predetermined constant voltage VCS based on CC and the ground potential VSS is provided. Although the power supply voltage VCC is not particularly limited, it is + 5V.
It is a positive potential such as (volt). In addition, the power supply voltage supply terminals VCCO and VCC and the ground potential supply terminal V
It goes without saying that SSO and VSS are commonly connected outside the synchronous SRAM.

In this embodiment, the power supply voltage supply terminal V
The power supply voltage VCC and the ground potential VSS supplied via the CCO and the ground potential supply terminal VSSO are supplied to the data output buffer OB as the power supply voltage VCC3 and the ground potential VSS3, respectively. On the other hand, the power supply voltage supply terminal VC
The power supply voltage VCC and the ground potential VSS supplied via C and the ground potential supply terminal VSS are respectively the power supply voltage V
The CC1 and the ground potential VSS1 are supplied to the clock signal input buffer IBK and the constant voltage generation circuit VCSG that form the timing generation circuit TG, and the clock signal input buffer IBK and the constant voltage generation circuit VCSG are supplied as the power supply voltage VCC2 and the ground potential VSS2, respectively. Are supplied to the other internal circuits IL except for. As will be described later, the power supply voltage VCC1 and the ground potential VS for the clock signal input buffer IBK and the constant voltage generation circuit VCSG.
The supply path of S1 is provided substantially independently of the supply paths of the power supply voltage VCC2 and the ground potential VSS2 to the other internal circuits IL. As a result, the power supply noise due to the charge current and the through current accompanying the operation of the internal circuit IL is suppressed, and the clock signal input buffer IBK
Also, the operation of the constant voltage generation circuit VCSG is stabilized. The power supply system of the relevant portion of such a synchronous SRAM will be described in detail later.

FIG. 2 is a partial signal system diagram of an embodiment of the input section of the synchronous SRAM of FIG. 3 and 4 are partial circuit diagrams of an embodiment of the timing generation circuit TG and the X address buffer XB included in the synchronous SRAM of FIG. 1, respectively, and FIG. 3 is a signal waveform diagram of an example of the synchronous SRAM of FIG. Based on these figures, the specific configuration and characteristics of the signal system, the timing generation circuit TG and the X address buffer XB in the input section of the synchronous SRAM of this embodiment will be described. In the circuit diagram below, the MOSFET with an arrow on its channel (back gate) is P
It is a channel type and is shown in distinction from an N-channel MOSFET without an arrow. Further, the illustrated bipolar transistors (hereinafter simply referred to as transistors) are all NPN type. Further, in FIG. 2, the clock signal input buffer IBK uses the power supply voltage VCC1 and the ground potential VSS1 as its operating power supply as described above, and the other circuits surrounded by the dotted line supply the power supply voltage VCC2 and the ground potential VSS2. Use as operating power supply.

In FIG. 2, the timing generation circuit TG
Is a clock signal input buffer IBK whose input terminal is coupled to a clock signal input terminal CLK, and a chip selection signal input buffer IBC whose input terminals are respectively coupled to a chip selection signal input terminal and a write enable signal input terminal WEB. And a write enable signal input buffer IBW. Of these, the clock signal input buffer IBK uses the power supply voltage VCC1 and the ground potential VSS1 as its operating power supply, as described above. The non-inverted output signal ICK of the clock signal input buffer IBK becomes the input clock signal BCK after passing through the inverters V1 and V2, and the inverted output signal ICKB is the inverted input clock signal BCK.
It is supplied to a subsequent circuit (not shown) as CKB.

Here, the clock signal CLK is not particularly limited, but is formed based on a system clock signal of a computer system or the like including a synchronous SRAM, and as shown in FIG. 5, it is alternately high during the same period. Level or low level, so-called duty 50%
Pulse signal. The chip selection signal CSB and the write enable signal WEB are the clock signal CLK.
Of the X address signals AX0 to AXi and the Y address signals AY0 to AYj are selected to a low level for a predetermined period to include the rising edge of the clock signal CLK. Is effectively set to a valid value. In the embodiment of FIG. 5, at the first rising edge A of the clock signal CLK, the X address signals AX0 to AXi and the Y address signals AY0 to AYj are supplied in a combination designating the row address ra1 and the column address ca1, respectively, and the rising edge. For C and E, the row address ra2
And ra3 and column addresses ca2 and ca3 are sequentially supplied in a specified combination.

The clock signal input buffer IBK which constitutes the timing generation circuit TG, as shown in FIG.
It includes an input inverter composed of P-channel MOSFETs P1 and P2 and an N-channel MOSFET N1 that are connected in series between the power supply voltage VCC1 and the ground potential VSS1 and have their gates coupled to the clock signal input terminal CLK. Of these, the drain of the MOSFET P1, that is, the source of the MOSFET P2 is coupled to the power supply voltage VCC1 through the transistor T1 which is substantially diode-shaped by having its base commonly coupled to the collector. The drains of the MOSFETs P2 and N1 that are commonly coupled are coupled to the input terminal of the inverter V3 as an output terminal of the input inverter, and the two P-channel MOSFETs P3 and P4 are connected in series.
To the power supply voltage VCC1. MOSFET
The gate of P3 is coupled to the ground potential VSS1 and
The gate of ETP4 is coupled to the output terminal of inverter V3.

The output terminal of the inverter V3 is further coupled to the input terminal of the inverter V4, and the P-channel MOSFETs P5 and P7, N-channel MOSF are connected.
It is coupled to the first input terminal of a so-called BiNMOS type two-input NOR gate composed of ETN4 to N7 and transistor T2, that is, the gates of MOSFETs P7, N4 and N5. The second input terminal of the NOR gate, that is, the gates of the MOSFETs P5, N6 and N7,
The output signal of the NAND gate NA1 is supplied, and the output signal, that is, the potential at the emitter of the transistor T1 becomes the inverted output signal ICKB of the clock signal input buffer IBK.

On the other hand, the output terminal of the inverter V4 is the first input terminal of the CMOS type two-input NOR gate composed of the P-channel MOSFETs P5 and P6 and the N-channel MOSFETs N2 and N3, that is, the MOSFET P6.
And the gates of N2. Further, the output signal of the NAND gate NA1 is supplied to the second input terminal thereof, that is, the gates of the MOSFETs P5 and N3, and the output signal thereof, that is, the potential at the commonly coupled drains of the MOSFETs P6, N2 and N3 is the clock signal input buffer. It becomes the non-inverted output signal ICK of IBK.

The first and second input terminals of NAND gate NA1 are commonly coupled to power supply voltage VCC1. As a result, the output signal of the NAND gate NA1 is constantly set to the low level like the ground potential VSS1. In addition, BiN
Both the MOS-type and CMOS-type NOR gates are constantly in the transmission state, and invert the potential at the first input terminal to transmit. Further, between the drain of the MOSFET P5 and the inverting output terminal of the clock signal input buffer IBK, that is, the emitter of the transistor T1, its gate is coupled to the non-inverting output terminal of the clock signal input buffer IBK, that is, the drains of the MOSFETs P6, N2 and N3. A P-channel MOSFET P8 is provided.
This MOSFET P8 is a clock signal input buffer I
In order to raise the high level of the inverted output signal ICKB to the power supply voltage VCC1 when the non-inverted output signal ICK of the BK is set to the low level, in other words, when the inverted output signal ICKB is set to the high level. Of the so-called pull-up MOSFET.

When the level of the clock signal CLK at the clock signal input terminal CLK is set to a predetermined low level suitable for a so-called TTL (transistor / transistor logic) interface, the MOSFET P1,
The output signal of the input inverter composed of P2 and N1 is set to a high level like the power supply voltage VCC1, and
The output signal of 3 is at a low level like the ground potential VSS1. Therefore, the clock signal input buffer IBK
The non-inverted output signal ICK is set to a low level like the ground potential VSS1, and the inverted output signal ICKB is set to a predetermined high level which is lower than the power supply voltage VCC1 by the base-emitter voltage of the transistor T1. The high level of the inverted output signal ICKB indicates that the non-inverted output signal ICK
Is set to a low level and the pull-up MOSFET P8 is sufficiently turned on, so that the power supply voltage VCC1
Be raised to.

On the other hand, the level of the clock signal CLK is TT.
When it is set to a predetermined high level suitable for the L interface, the output signal of the input inverter composed of MOSFETs P1, P2 and N1 changes to a low level such as the ground potential VSS1, and the output signal of the inverter V3 changes to the power supply voltage VC.
It changes to a high level like C1. Therefore, the non-inverted output signal ICK of the clock signal input buffer IBK is set to the high level like the power supply voltage VCC1, and the inverted output signal ICKB is set to the low level like the ground potential VSS1. The non-inverted output signal ICK of the clock signal input buffer IBK is generated by the two inverters V as described above.
It becomes the input clock signal BCK through 1 and V2. Therefore, the input clock signal BCK becomes a pulse signal having the same phase as the clock signal CLK, as shown in FIG.
The actual phase thereof is delayed from the clock signal CLK by the signal transmission delay time of the clock signal input buffer IBK and the inverters V1 and V2.

Next, the chip selection signal input buffer IBC
Is supplied to the data input terminal D of the edge trigger type flip-flop FFC, and the output signal IWB of the write enable signal input buffer IBW is supplied to the data input terminal D of the edge trigger type flip-flop FFW. It The input clock signal BCK is commonly supplied to the clock input terminals C of these flip-flops. On the other hand, the non-inverted output signal Q of the flip-flop FFC is supplied as an internal signal FCB to the mode control circuit MODC and other subsequent circuits not shown, and the inverted output signal QB is supplied as an internal signal FC to the subsequent circuit. . Similarly, flip-flop FF
The non-inverted output signal Q of W is supplied as an internal signal FWB to the mode control circuit MODC and a subsequent circuit (not shown), and its inverted output signal QB is supplied as an internal signal FW to the subsequent circuit.

The chip selection signal input buffer IBC takes in the chip selection signal CSB input through the chip selection signal input terminal CSB, forms an in-phase internal signal ICB, and supplies it to the mode control circuit MODC and other subsequent circuits. Supply. The write enable signal input buffer IBW fetches the write enable signal WEB input via the write enable signal input terminal WEB,
The in-phase internal signal IWB is formed and the mode control circuit MO is formed.
Supply to DC as well as other subsequent circuits.

On the other hand, the flip-flop FFC is a flip-flop FFX0 of the X address buffer XB which will be described later.
~ Like FFXi, includes master and slave latches. Among these, the master latch is brought into a transmission state by taking in the internal signal ICB supplied to the data input terminal D when the clock signal CLK, that is, the input clock signal BCK is at a low level, and the rising edge of the input clock signal BCK. Internal signal ICB at
The latch form holds the logic level immediately before. The slave latch is connected to the input clock signal BCK.
Is set to a high level, the output signal of the master latch is taken into the transfer state and the input clock signal BC
At the falling edge of K, a latch form is formed by holding the logic level immediately before the output signal of the master latch. As a result, the low level of the chip selection signal CSB is, for example, as shown in FIG.
At the rising edges A and C of CK, it is taken into the flip-flop FFC, so that its non-inverted output signal, that is, the internal signal FCB becomes selectively low level for the corresponding cycle period of the input clock signal BCK.

Similarly, the flip-flop FFW includes a master latch and a slave latch. Of these, the master latch is a write enable signal input buffer IBW when the input clock signal BCK is at a low level.
The internal signal IWB supplied to the data input terminal D from the input signal DWB is brought into the transmission state, and at the rising edge of the input clock signal BCK, the logic level immediately before the internal signal IWB is held and the latch form is set. When the input clock signal BCK is at a high level, the slave latch is brought into a transmission state by taking in the output signal of the master latch, and at the falling edge of the input clock signal BCK, the signal immediately before the output signal of the master latch is output. The latch form holds the logic level. As a result, the low level of the write enable signal WEB is as shown in FIG.
, The non-inverted output signal thereof, that is, the internal signal FWB, is selectively set to the low level only during the corresponding cycle period of the input clock signal BCK, for example, at the rising edge C of the input clock signal BCK. Become.

As described above, the chip select signal input buffer IBC, the flip-flop FFC, and the write enable signal input buffer I of the timing generation circuit TG.
The BW and the flip-flop FFW receive the corresponding chip selection signal CSB and write enable signal WEB from the input clock signal BCK, that is, the substantial clock signal CLK.
The input signal of the so-called register type which takes in according to
The logic levels of B, FC, FWB and FW are transited in synchronization with the rising edge of the input clock signal BCK. The flip-flops FFC and FFW are the flip-flops FFX of the X address buffer XB described later.
Since it has the same configuration as 0, its specific configuration and operation should be inferred from the following description regarding the flip-flop FFX0.

The mode control circuit MODC constituting the timing generation circuit TG receives the chip selection signal CSB, that is, the internal signal FCB and the write enable signal WEB, that is, the internal signal FWB, and determines the operation mode of the synchronous SRAM, and Output signal, ie internal control signal DE,
WP, SP and DOC are selectively set to high level or low level at predetermined timings. As described above, the internal signals FCB and FWB are equal to the input clock signal B.
CK, that is, a transition is made in synchronization with the rising edge of the clock signal CLK, and in response to this, the internal control signals DE, W
P, SP and DOC are selectively formed. Therefore, as shown in FIG. 5, each circuit of the synchronous SRAM executes the read operation in the period from the rising edge A to the next rising edge C of the clock signal CLK, and the rising edge C to the next rising edge C, for example. The write operation is executed in the period up to E.

Next, the X address buffer XB is i + 1 provided corresponding to the address input terminals AX0 to AXi.
X address signal input buffers UXB0 to UXBi
And flip-flops FFX0 to FFXi.
Of these, the X address signal input buffers UXB0 to UX
The output signal of Bi is supplied to the data input terminals D of the corresponding flip-flops FFX0 to FFXi as the internal signals IX0 to IXi. Flip-flop FFX0 to FF
The input clock signal BCK is commonly supplied to the clock input terminal C of Xi. Further, the non-inverted output signals Q are respectively non-inverted internal address signals X0T to XiT.
And inverted output signals QB thereof are inverted internal address signals X0B to XiB, respectively.

Here, the X address signal input buffers UXB0 to UXBi forming the X address buffer XB are
As represented by the X address signal input buffer UXB0 in FIG. 4, the power supply voltage VCC2 and the ground potential VSS are represented.
A P-channel MOSF provided in series between the two and having its gate coupled to the corresponding address input terminal AX0 or the like.
ETP9 and PA and N-channel MOSFET N
Includes 8 input inverters. Hereinafter, a specific description of the X address signal input buffers UXB0 to UXBi will be given by taking the X address signal input buffer UXB0 as an example.

The drain of the MOSFET P9 forming the input inverter of the X address signal input buffer UXB0, that is, the source of the MOSFET PA, is coupled to the power supply voltage VCC2 through the transistor T3 which is in the form of a diode because its base is commonly coupled to the collector. To be done.
Also, the output signal of the input inverter, that is, MOSFETP
The potential at the co-coupled drains of A and N8 is
The corresponding flip-flop FFX as the internal signal IX0
0 is supplied to the data input terminal D.

As a result, the output signal of the X address signal input buffer UXB0, that is, the internal signal IX0 becomes like the power supply voltage VCC2 when the level of the address signal AX0 at the address input terminal AX0 is set to a predetermined low level suitable for the TTL interface. When the high level is set to a predetermined high level suitable for the TTL interface, the low level such as the ground potential VSS2 is set.

On the other hand, the flip-flops FFX0 to FFXi forming the X address buffer XB are not particularly limited, but as shown by the flip-flop FFX0 in FIG. Consisting of 2
A master latch ML including a clocked inverter and a NAND gate NA2 is provided. Hereinafter, taking the flip-flop FFX0 as an example, the flip-flops FFX0 to FFX
A concrete explanation of i will be given.

The data input terminal of the left clocked inverter forming the master latch ML, that is, MOSFET
The commonly coupled gates of PD and NA are coupled to the output terminal of the X address signal input buffer UXB0 and also to the power supply voltage VCC2 through P channel MOSFETs PB and PC. The NAND gate NA is connected to the data input terminal of the clocked inverter on the right side, that is, the commonly connected gates of the MOSFETs PF and NC.
2 output signals are provided. Further, the output signal of the NAND gate NA4 is commonly supplied to the non-inverting control terminal of the left clocked inverter, that is, the gate of the MOSFET N9 and the inverting control terminal of the right clocked inverter, that is, the gate of the MOSFET PF. The inverted signal from the inverter V7 is commonly supplied to the inversion control terminal, that is, the gate of the MOSFETPE and the non-inversion control terminal of the clocked inverter on the right side, that is, the gate of the MOSFETNB.

MOSFE constituting the master latch ML
The gate of TPB is fixedly coupled to the ground potential VSS2. Also, the output terminal of the master latch ML, that is, MO
The commonly coupled drains of SFETPE, PG, N9 and NB are coupled to the gate of the MOSFET PC and to one input terminal of the NAND gate NA2, and further to the clocked inverter on the left side constituting the slave latch SL of the subsequent stage. Data input terminal, that is, P-channel MOSFET PJ and N-channel MOSFET N
E is coupled to the commonly coupled gates. The other input terminal of the NAND gate NA2 has a power supply voltage V
It is coupled to the output terminal of inverter V5 which is coupled to CC2. Further, the input clock signal BCK is supplied to one input terminal of the NAND gate NA4 via the two inverters V8 and V9, and the other input terminal thereof is provided with the inverters VA and VB of the output signal of the inverter V9 and the capacitor. A delay signal from the delay circuit composed of C1 is supplied. As a result, the output signal of the NAND gate NA4 becomes low level when a predetermined delay time by the delay circuit elapses after the input clock signal BCK becomes high level, and it becomes high level in response to the low level of the input clock signal BCK. Will be returned.

When the input clock signal BCK is set to low level and the output signal of the NAND gate NA4 is set to high level, in the master latch ML, the clocked inverter on the left side is set to the transmission state, and the logic of the X address signal AX0, that is, the internal signal IX0. The level is inverted and transmitted to the output terminal of the master latch ML. At this time, the clocked inverter on the right side is in the non-transmission state and has no effect.

On the other hand, a predetermined delay time elapses after the input clock signal BCK is set to the high level, and the NAND gate N
When the output signal of A4 is at a low level, in the master latch ML, the left clocked inverter is in a non-transmission state, and the right clocked inverter is in a transmission state instead. As a result, the clocked inverter on the right side constitutes a latch circuit together with the NAND gate NA2,
The logic level immediately before the X address signal AX0, that is, the internal signal IX0 is held.

The flip-flop FFX0 further includes a slave latch SL including two clocked inverters composed of P-channel MOSFETs PH to PL and N-channel MOSFETs ND to NG and an inverter VE. Of these, the data input terminal of the left clocked inverter, that is, the commonly connected gates of the MOSFET PH and NE are connected to the output terminal of the master latch ML. The output signal of the inverter VE is supplied to the data input terminal of the clocked inverter on the right side, that is, the commonly connected gates of the MOSFETs PI and NG. The output signal of the inverter V9 in phase with the input clock signal BCK is commonly supplied to the non-inverting control terminal of the clocked inverter on the left side, that is, the gate of the MOSFET ND and the inverting control terminal of the clocked inverter on the right side, that is, the gate of the MOSFET PL. The inverting control terminal of the clocked inverter on the left side, that is, the gate of the MOSFET PJ and the non-inverting control terminal of the clocked inverter on the right side, that is, the gate of the MOSFET NF, are connected via the inverters VC and VD to the inverter V8 having a phase opposite to that of the input clock signal BCK. Output signals are commonly supplied.

Output terminal of slave latch SL, that is, MO
The commonly coupled drains of SFETs PJ, PL, ND and NF are connected to the input terminal of the inverter VE and the P channel M.
It is coupled to the input terminal of the inverter composed of the OSFETPN and the N-channel MOSFET NJ, is coupled to the power supply voltage VCC2 via the P-channel pull-up MOSFET PM, and is coupled to the ground potential VSS2 via the N-channel pull-down MOSFET NI. . The source of the MOSFET NJ forming the above-mentioned inverter is coupled to the drains of the MOSFETs NE and NG, and then coupled to the ground potential VS2 via the N-channel drive MOSFET NH. Also, its output terminal is
It is coupled to the input terminal of the inverter VF and also coupled to the power supply voltage VCC2 via the P-channel pull-up MOSFET PN. The output signal of the inverter VE is the non-inverting output signal Q of the flip-flop FFX0, that is, the non-inverting internal address signal X0T, and the inverter V
The output signal of F is its inverted output signal QB, that is, the inverted internal address signal X0B.

An inverted signal of the output signal of the NAND gate NA3 by the inverter V6 is commonly supplied to the gates of the pull-up MOSFETs PM and PO and the drive MOSFET NH. The output signal of the inverter V5 is supplied to the gate of the pull-down MOSFET NI. A pair of input terminals of the NAND gate NA3 is coupled to the power supply voltage VCC2. As a result, the NAND gate NA
The output signal of the inverter 3 is constantly at the low level, and the output signal of the inverter V6 is constantly at the high level. Further, as described above, the input terminal of the inverter V5 is coupled to the power supply voltage VCC2, and the output signal thereof is constantly at the low level. Therefore, the drive MOSFET NH is constantly turned on, and the pull-up MOSFETs PM and PN and the pull-down MOSFET NI are constantly turned off.

When the input clock signal BCK, that is, the output signal of the inverter V9 is at the high level and the output signal of the inverter VD is at the low level, the slave latch SL.
Then, the clocked inverter on the left side is set to the transmission state, and the output signal of the corresponding master latch ML is inverted and transmitted to the output terminal of the slave latch SL. At this time, the clocked inverter on the right side is in the non-transmission state and has no effect.

On the other hand, the input clock signal BCK, that is, the output signal of the inverter V9 is set to the low level, and the inverter V9 is turned on.
When the output signal of D is set to the high level, the clocked inverter on the left side is set to the non-transmission state in the slave latch SL, and the clocked inverter on the right side is set to the transmission state instead. Therefore, the clocked inverter on the right side forms a latch circuit together with the inverter VE and holds the logic level immediately before the output signal of the master latch ML. As a result, the X address signals AX0 to AXi are fetched by the master latch ML of the corresponding flip-flops FFX0 to FFXi at the rising edge of the clock signal CLK and then transmitted to the corresponding slave latch SL, as shown in FIG. And complementary internal address signal X0 *
~ Xi *. The logical levels of these complementary internal address signals are held by each slave latch SL even after the input clock signal BCK is set to the low level, and transit at the next rising edge of the input clock signal BCK.

The synchronous SRAM of this embodiment is
As described above, the data output buffer OB is provided with the data latch for holding the read data, and the output operation of the read data is delayed by one cycle of the clock signal CLK. Done. Therefore, the address (ra1, ca1) performed in the period from the rising edge A to C of the clock signal CLK
The result of the read operation for is output from the data output terminals DO0 to DO3 in the subsequent cycle of the clock signal CLK, that is, in the period from the rising edge C to E.

FIG. 6 shows a board layout diagram of an embodiment of the synchronous SRAM of FIG. 1, and FIG. 7 shows a partial power supply system diagram of the embodiment. Based on these drawings, the substrate arrangement of the synchronous SRAM of this embodiment, a specific power supply system, and its features will be described. Note that FIG. 6 illustrates only the pads necessary for explaining the power supply system according to the present invention. Further, in the following description, the vertical and horizontal directions on the surface of the semiconductor substrate are represented by the positional relationship of FIGS. 6 and 7.

In FIG. 6, the X address decoder XD constituting the synchronous SRAM of this embodiment is actually divided into four X address decoders XD0 to XD3 and arranged on the surface of the semiconductor substrate SUB. Memory array M divided into four pairs so as to sandwich the X address decoder
ARY0L and MARY0R to MARY3L and M
ARY3R is arranged respectively. Also, inside each memory array, Y address decoders YD0L and YD0R to YD3R and YD3R which are similarly divided into four pairs are provided.
Are arranged corresponding to each other, and four sets of memory mats MAT0 to MAT3 are constituted by the X address decoder and the corresponding memory array and Y address decoder. The Y address decoders YD0L and Y
Each of D0R to YD3L and YD3R includes a Y switch YS, a write amplifier WA, and a sense amplifier SA, which are correspondingly divided into four pairs.

The X address buffer X is provided in the vertical central portion of the semiconductor substrate SUB, that is, between the memory mats MAT0 and MAT1 and between the memory mats MAT2 and MAT3.
B, constant voltage generation circuit VCSG, Y address buffer YB
And a timing generation circuit TG, and data input buffers IB01 and IB23 and OB01 divided into two.
And peripheral circuit PEV including OB23 are arranged. In addition, a central portion on the side of the semiconductor substrate SUB, that is, between the memory mats MAT0 and MAT2, and the memory mat MAT.
Between 1 and MAT3, other peripheral circuits PEHL and PEHR including a redundant circuit and the like not shown in FIG. 1 are arranged, respectively. Below the constant voltage generation circuit VCSG, the clock signal input buffer IB of the timing generation circuit TG is provided.
Only K is arranged separately from the timing generation circuit body. Further, the synchronous SRAM of this embodiment adopts a so-called LOC (read-on-chip) form, and has a constant voltage generation circuit VCSG and a clock signal input buffer IB.
On the left and right of K, power supply voltage supply pads PVC corresponding to the power supply voltage supply terminal VCCO and the ground potential supply terminal VSSO
CO and a ground potential supply pad PVSSO are respectively arranged, and a power supply voltage supply pad PVCC (first power supply pad) corresponding to the power supply voltage supply terminal VCC and a ground potential supply terminal VSS and a ground are provided on the left and right of the timing generation circuit TG. Potential supply pads PVSS (second power supply pads) are arranged.

In this embodiment, X address buffer XB, data input buffers IB01 and IB23, Y address buffer YB and clock signal input buffer IBK.
The power supply voltage VCC, that is, VCC1 is supplied from the power supply voltage supply pad PVCC via the power supply voltage supply wiring SVCC1 to the timing generation circuits TG except for, and the ground potential VSS, that is, the ground potential VSS, from the ground potential supply pad PVSS via the ground potential supply wiring SVSS1. VSS1 is supplied. Also,
The clock signal input buffer IBK of the constant voltage generation circuit VCSG and the timing generation circuit TG has a power supply voltage supply line SVCC independent of the power supply voltage supply pad PVCC.
The power supply voltage VCC, that is, VCC2 is supplied via 2
The ground potential VSS, that is, VS, via the ground potential supply wiring SVSS2 independent from the ground potential supply pad PVSS.
S2 is supplied. Further, the data output buffers OB, that is, OB01 and OB02, are supplied with the power supply voltage VCC, that is, VCC3 from the independent power supply voltage supply pad PVCCO through the power supply voltage supply wiring SVCC3, and the ground potential supply wiring is supplied from the independent ground potential supply pad PVSSO. The ground potential VSS, that is, VSS3 is supplied via SVSS3.

That is, the synchronous SRA of this embodiment
In M, the power supply path to the data output buffer OB, that is, OB01 and OB23, which can be a source of relatively large power supply noise, is independent including the power supply voltage supply terminal and the ground potential supply terminal, the power supply voltage supply pad and the ground potential supply pad. And a constant voltage generation circuit VCSG and a timing generation circuit T for determining the operation characteristics, operation mode and timing of the synchronous SRAM.
A power supply path for the G clock signal input buffer IBK is independently provided with the power supply voltage supply pad PVCC and the ground potential supply pad PVSS as a starting point, so that the power supply noise accompanying the operation of the data output buffer OB may be different. It is possible to suppress the transmission to the power supply path of the internal circuit, and the power supply noise due to the charge current and the through current accompanying the operation of the data output buffer OB and other internal circuits is generated by the constant voltage generating circuit VC.
It is possible to suppress transmission to the power supply paths of the SG and the clock signal input buffer IBK. As a result,
In particular, the clock signal C of the clock signal input buffer IBK
It is possible to stabilize the level determination operation for LK,
This prevents malfunction of the synchronous SRAM,
The reliability can be improved.

The operational effects obtained from the above embodiments are as follows. That is, (1) a clock signal input buffer which receives an externally supplied clock signal, a register type input buffer which takes in a start control signal, an address signal and the like according to the clock signal, a memory array and peripheral parts which are operated in synchronization with the clock signal SRA with internal circuit of
In M, etc., the power supply path for the clock signal input buffer is provided substantially independently of the power supply paths for the register-type input buffer and other internal circuits, thereby operating the internal circuits such as the memory array and peripheral parts. It is possible to obtain an effect that power supply noise due to the charge current and the shoot-through current accompanying the above can be suppressed. (2) According to the above item (1), it is possible to stabilize the level determination operation for the clock signal of the clock signal input buffer. (3) According to the above items (1) and (2), it is possible to prevent the erroneous data from being taken into the register-type input buffer. (4) According to the above items (1) to (3), it is possible to prevent the malfunction of the synchronous SRAM or the like and increase the reliability thereof.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
In FIG. 1, the synchronous SRAM is × 1 or × 8.
Any bit configuration such as bits can be adopted. In addition, the synchronous SRAM does not necessarily include the constant voltage generation circuit VCSG, and the block configuration, the combination and name of the activation control signal and the address signal, the polarity and the absolute value of the power supply voltage, and the like are various. Embodiments can be adopted.

2 to 4, the clock signal C
Separation of the power supply path to the input circuit of LK may be performed by including the inverters V1 and V2 in the subsequent stage, or may be performed by including the input circuits related to other input signals such as the chip selection signal CSB and the write enable signal WEB. it can. Flip-flops FFC, FFW, FFX0 to FFXi and F included in the register type input buffer
FY0 to FFYj are not required to be edge-triggered flip-flops. Further, various embodiments can be adopted for the specific configurations of the timing generation circuit TG and the X address buffer XB, the conductivity types of the MOSFET and the transistor, and the like.

In FIG. 5, the synchronous SRAM is
The operation may be performed starting from the falling edge of the clock signal CLK, and the logic levels of each activation control signal and internal signal are not restricted by this embodiment. In FIG. 6, each part of the synchronous SRAM can be divided and arranged in an arbitrary number. Further, the synchronous SRAM does not require the LOC form as an indispensable condition, and the specific substrate layout can adopt various embodiments. In FIG. 7, the power supply path for the constant voltage generation circuit VCSG and the clock signal input buffer IBK may be provided independently including the power supply voltage supply terminal and the ground potential supply terminal, or a part of the power supply path may be provided for the X address buffer X.
It may be partially shared with the power supply path for B and the like.

In the above description, the case where the invention made by the present inventor is mainly applied to the synchronous SRAM which is the background field of application has been described. However, the invention is not limited thereto, and for example, the synchronous D
It is also applicable to various memory integrated circuits such as RAM (dynamic RAM) and logic integrated circuit devices such as microcomputers. INDUSTRIAL APPLICABILITY The present invention can be widely applied to semiconductor devices whose operations are synchronized by a basic input signal such as a clock signal.

[0065]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a clock signal input buffer that receives an externally supplied clock signal, a register-type input buffer that takes in a start control signal, an address signal, and the like according to the clock signal, and internal circuits such as a memory array and peripheral portions that operate in synchronization with the clock signal In a synchronous SRAM or the like including a memory array and peripheral parts, the power supply path for the clock signal input buffer is provided substantially independently of the power supply paths for the register type input buffer and other internal circuits. The power supply noise due to the charge current and the through current due to the operation of the internal circuit can be suppressed, and the level determination operation for the clock signal of the clock signal input buffer can be stabilized. As a result, it is possible to prevent erroneous data from being taken into the register-type input buffer, prevent erroneous operation of the synchronous SRAM, etc., and improve its reliability.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous SRAM to which the invention is applied.

FIG. 2 is a partial signal system diagram showing an embodiment of the synchronous SRAM of FIG.

3 is a partial circuit diagram showing an embodiment of a timing generation circuit included in the synchronous SRAM of FIG.

4 is a partial circuit diagram showing an embodiment of an X address buffer included in the synchronous SRAM of FIG.

5 is a signal waveform diagram showing an embodiment of the synchronous SRAM of FIG.

6 is a board layout diagram showing an embodiment of the synchronous SRAM of FIG. 1. FIG.

FIG. 7 is a partial power system diagram showing one embodiment of the synchronous SRAM of FIG.

[Explanation of symbols]

MARY ... Memory array, XD ... X address decoder, XB ... X address buffer, YS ... Y
Switch, YD ... Y address decoder, YB ...
Y address buffer, WA ... write amplifier, SA
..Sense amplifier, IB ... Data input buffer, O
B ... Data output buffer, TG ... Timing generation circuit, VCSG ... Constant voltage generation circuit. CLK ...
Clock signal input terminal, CSB ... Chip selection signal input terminal, WEB ... Write enable signal input terminal,
AX0 to AXi, AY0 to AYj ... Address signal input terminals, DI0 to DI3 ... Data input terminals, DO0
~ DO3 ... Data output terminal, VCC, VCCO ...
Power supply voltage supply terminal, VSS, VSSO ... Ground potential supply terminal, WB0 * to WB3 * ... Write data bus, RB0 * to RB3 * ... Read data bus. IBK ... Clock signal input buffer, IBC
..Chip selection signal input buffer, IBW ... Write enable signal input buffer, UXB0 to UXBi ...
・ X address signal input buffer, UYB0 to UYBj
..Y address signal input buffer, FFC, FFW, F
FX0 to FFXi, FFY0 to FFYj ... Edge trigger type flip-flop, MODC ... Mode control circuit. ML ... Master latch, SL ... Slave latch. P1-PO ... P-channel MOSFET, N
1-NJ ... N-channel MOSFET, T1-T3
... NPN bipolar transistors, V1 to VF
..Inverters, NA1 to NA4 ... NAND (NAN
D) Gate, C1 ... Capacitor. ra1-ra3
..Row addresses, ca1 to ca3 ... Column addresses. S
UB ... Semiconductor substrate, MAT0 to MAT3 ... Memory mat, MARY0L to MARY3L, MARY0R
~ MARY3R ... Memory array, XD0-XD3
..X address decoders, YD0L to YD3L, YD0
R to YD3R ... Y address decoder, PEV, PE
HL, PEHR ... Peripheral circuits, PVCC, PVCCO
... Power supply voltage supply pads, PVSS, PVSSO ...
Ground potential supply pad, IB01, IB23 ... Data input buffer, OB01, OB23 ... Data output buffer. SVCC1 to SVCC3 ... Power supply voltage supply wiring, SVSS1 to SVSS3 ... Ground potential supply wiring.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/10 381

Claims (4)

[Claims] 1. A first input terminal to which a first input signal is input, a first input buffer which receives the first input signal, and a first input which is input via the first input buffer.
And an internal circuit that is operated substantially in synchronization with the input signal of 1., wherein the power supply path for the first input buffer is provided substantially independently of the power supply path for the internal circuit. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the first power supply terminal and the first power supply pad are supplied with a first power supply voltage, and the second power supply terminal is supplied with a second power supply voltage. A power supply pad;
2. The semiconductor device according to claim 1, wherein the power supply path for the input buffer is independently provided with the first and second power supply pads as a starting point. 3. The semiconductor device according to claim 1, wherein the second input signal is input via a second input terminal to which a second input signal is input, and the first input signal input via the first input buffer. And a constant voltage generating circuit that forms a predetermined constant voltage based on the first and second power supply voltages, and a power supply path for the internal circuit is , Substantially shared as a power supply path to the second input buffer, and the power supply path to the first input buffer is substantially shared as a power supply path to the constant voltage generation circuit. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 4. The semiconductor device comprises an output buffer, and a power supply path for the output buffer includes a power supply terminal for supplying the first and second power supply voltages, 4. The semiconductor device according to claim 1, wherein the internal circuit and the power supply paths for the first and second input buffers are provided substantially independently of each other.