JPH0727452B2 - Priority Encoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to a priority encoder (Priority E) that searches for information consisting of a plurality of binarized bits at high speed.
ncoder) regarding.

(Prior Art) A priority encoder (hereinafter referred to as “P encoder”) uses binary (“0”, “1”) logical data having a plurality of bit lengths (hereinafter referred to as “search information”). Search (scan) from the lower bit (LSB) direction or the most significant bit (MSB) direction to detect the bit position where the bit is "1" or "0" first, and this bit position is the binary code (BCD) It is represented by.

That is, the P encoder gives an n-bit output as a binary code to search information having a bit length of 2 (n = 1, 2 ...). For example, if the search information is n = 5
The encoder output at the first bit position of "1" in (32 bits) is shown in FIGS. 11 (A) and 11 (B). FIG. 11 (A) shows the bit position which is first "1" when the search information is searched from the least significant bit direction (hereinafter referred to as "right direction") and the corresponding binary code output. In FIG. 11 (B), when searching from the most significant bit direction (hereinafter referred to as “left direction”), “1” is first displayed.
Indicates the bit position and the corresponding binary code output. In addition, in FIG. 11 (A) and FIG. 11 (B), and in the following figures, the X mark is “0”.
Or it indicates that it may be "1"(don't care).

FIG. 12 is a block diagram of a P encoder that searches, for example, 8-bit search information when the bit length of the search information is small. The P encoder shown in the same figure searches the search information 7i to 0i by combining various logic gates from the left as shown in FIG. 4d, 2b, 1b) is output as a binary code, and the lower bit search depends on the upper bit search result.

In FIG. 12, when Ei = “0”, the outputs (4b, 2b, 1b) obtained from the search information 7i to 0i are output as they are. On the other hand, when Ei = "1", all outputs (4b, 2b, 1b) are forced to "0", When is input, the output Eo of the NAND gate is forcibly set to "1". This Eo becomes "0" only when Ei = "0" to 7i to 0i are all "0", and becomes "1" in other cases. That is, when the bit length of the search information is increased by using a plurality of 8-bit P encoders shown in FIG. 12, Ei and Eo determine whether the search information on the upper bit side is all “0” or lower bit. It will be shown to the side.

FIG. 14 is a block diagram of the P encoder shown in FIG. 12, in which the 8-bit P encoder is cascade-connected, 32-bit search information is searched from the left and the search result is given as a binary code output (PE4 to PE0). Is.

The P encoder shown in the same figure outputs the respective outputs corresponding to the respective 8-bit P encoders (P4, P3, P2, P1) to N.
It is input to the OR gates (NO1, NO2, NO3), and the inverted output of each NOR gate is used as the output (PE2, PE1, PE0) of the lower 3 bits in the binary code. Furthermore, in the cascade-connected P encoders (P4 to P1), the Eo of the P encoder on the higher-order bit side is given as the Ei of the P encoder on the lower-order bit side, and the Eo of the higher-order bit side is "1". At times, the Ei of all P encoders on the lower bit side become "1" and all outputs also become "0". That is, when the search information is searched from the left and the first bit position of "1" is detected, all lower P encoders that do not include this bit are irrespective of the input search information. The output becomes "0".

On the other hand, the higher-order 2-bit output (PE4, PE3) is a P-encoder P5 that inputs Eo ₄ , Eo ₃ , Eo ₂ , Eo ₁ of each P-encoder (P4, P3, P2, PE1) as a 4-bit input. Lower side of the output of 2
It is given as a bit.

Further, in the P encoder by this cascade connection, the speed is slow because the propagation of Eo to the lower bit side is serial. Therefore, as shown in FIG. 15, Ei is obtained by calculating the logical sum of Eo to accelerate the propagation of Eo.

By the way, the above-mentioned P encoder is configured to search the search information from the left, and the search on the lower bit side depends on the search result on the higher bit side. In such a configuration, when performing a search from the right,
The binary code output from the right direction shown in FIG. 11 (A) is the search information in which the arrangement of the search information shown in FIG. 11 (B) is reversed (search information of 0th bit is 31st bit, 1st bit The search information of the 30th bit is the same as the following.) Binary code output is obtained by inverting each bit.

As described above, the conventional P encoder that performs a search from both left and right directions has a circuit (not shown) that reverses the arrangement of search information to the P encoder that performs a search from either one.
And a circuit (not shown) for calculating the one's complement of the binary code output is added.

(Problems to be Solved by the Invention) As described above, the conventional P encoder is not configured to handle searches from both directions equally, and is optimized only for searches from either one. ing. Therefore, in order to perform a search from both directions, it is necessary to rearrange the search information and invert the output bit by bit. Therefore, hardware for performing such an operation is required, resulting in an increase in hardware and a decrease in search time.

Such a problem was not so serious in the conventional case where the number of bits of search information was relatively small and a high-speed search was not required. However, recently, with the rapid sophistication of computers, the number of bits of search information tends to increase, and higher speed search is required.
It is becoming difficult for a P encoder optimized for a search from one direction to handle it.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to provide a priority encoder capable of performing a search from both directions in an equivalent search time and performing a high-speed search. It is in.

[Structure of the Invention] (Means for Solving Problems) In order to achieve the above object, the present invention first searches for search information composed of binary bit information from the most significant bit direction or the least significant bit direction. Performing a search operation to detect the bit position that is one of the bit information, and making it a priority encoder that gives an encoder output indicating this bit position, each of the unit search information obtained by dividing the search information into a predetermined bit length. Search means for performing a search operation for each of them, giving an encoded output to each, and outputting a detection signal indicating that the unit search information is all the other bit information, and a detection signal and a search direction of each of the search means. Generating means for generating a part of the encoded output of the search information by the search signal indicating A selection signal generating means for generating a selection signal according to the search signal; and a selection means for selecting a predetermined encoded output as a part of the encoded output of the search information according to the selection signal from the respective encoded outputs of the searching means. Composed of.

(Operation) The priority encoder of the present invention generates a part of the encoded output indicating the position of the bit information detected from the search information consisting of a large number of bits from each detection signal and the search signal, and the remaining part. Is an encoded output selected according to a selection signal from encoded outputs for each unit search information.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a priority encoder according to an embodiment of the present invention. The P encoder shown in FIG.
The search information of the bit length is searched according to the search signals PER (right direction) and PEL (left direction, inverted signal of PER) indicating the search direction, and the first bit position of "1" is 5
It is represented by a binary code by bit encoding outputs (PE4, PE3, PE2, PE1, PE0). The configuration of the P encoder shown in FIG. 1 will be described in detail below with reference to FIGS. 2 to 10.

First, the 32-bit search information is divided into 4-bit width blocks, and the 4-bit search information of each block is divided into corresponding P encoders (hereinafter “<G>, <M>, <
"I>, <J>, <K>, <L>, <M>, <N>").

FIG. 2 is a diagram showing a specific structure of this <α> (α = G to N), and <α> has the same structure.

In FIG. 2, <α> is a combination of logic gates, and 4-bit search information (D ₃
~ D ₀ ) encoded output in binary code PRα1
Inversion signal of (1st bit), PRα0 (0th bit) ▲
Generates ▼ and ▲ ▼, and when searching from the left direction, the inverted signals of the encoded outputs PLα1, PLα0 ▲
▼ and ▲ ▼ are generated. further,
Input the search information (D _{3 to} D ₀ ) to the zero detection signal α (α = G to N) that becomes “1” only when the 4-bit search information (D _{3 to} D ₀ ) is all “0”. It is generated by using a NOR gate. In such <α>, the encoded outputs PRα and PLα in the 4-bit search information (D _{3 to} D ₀ ) are
It becomes as shown in FIG. Incidentally, FIG. 3 (B)
FIG. 6 is a diagram showing a Boolean expression of encoded outputs PRα and PLα.

Further, in the zero detection signal α generated by <α>, the logical product of the zero detection signals G and H, I and J, K and L, M and N is calculated as the zero detection signal C,
D, E, F (C = G · H, D = I · J, E = K · L, F = M · N), and zero detection among the zero detection signals C, D, E, F The logical product of the signals C and D, E and F is calculated as the zero detection signals A and B (A = C · D,
B = EF). As shown in FIG. 4, the zero detection signals C, D, E, F become zero detection signals of search information for every 8 bits from the upper bit, the zero detection signal A is the upper 16 bits, and the zero detection signal B is It is the lower 16-bit zero detection signal.

FIG. 5 is a diagram showing a configuration for generating each zero detection signal of <G> to <N>.

The zero detection signal C is the NAND of the zero detection signals G and H,
Further, this result is obtained by inverting, and the zero detection signal D is the same as the zero detection signal C. Further, the zero detection signal A is obtained by taking the NAND of each of the zero detection signals G, H and I, J and taking the NOR of the respective results. The zero detection signals B, E, F are zero detection signals K, L, M, N.
Is obtained in the same manner as described above.

By using the zero detection signals A to N obtained in this way, the P encoder of this embodiment outputs its encoded output (PE4
-PE0), the zero detection signals A to N and the search signal PER are selected from the respective encoded outputs of <G> to <N>.
The 2-bit encode output selected in accordance with (1 indicates a search from the right direction, "0" indicates a search from the left direction), lower-order encode outputs PE1 and PE0
As a result, the higher-order encoded outputs PE4, PE3, PE2 are obtained from the zero detection signals A to N and the search signal PER.

Next, the encode output (PE4 to PE0) of the P encoder is
How to obtain from the zero detection signals A to N and the search signal PER will be described.

Figure 6 shows the encoded output (PE4
~ PE0) and zero detection signals A to N.
In FIG. 6, <G> to <H> represent 2-bit encoded outputs of the respective circuits, and A
= B = “1”, the search information is all “0”.

In FIG. 6, for example, a search from the right direction (PER =
"1") and the zero detection signals B, D, J are "1", "0",
In the case of "1", the zero detection signal I becomes "0", so it can be seen that the first "1" exists in the 20th to 23rd bits. Therefore, the high-order side encode output PE4,3,2 is "1,0,1", and the low-order side encode output PE1,0 is <I
It is obtained by encoding output from the right side of>.

In this way, the encode outputs PE4 to PE2 can be easily obtained from the zero detection signals A to N and the search signal PER, and the encode outputs (PE4 to PE2) at the time of searching from both directions can be calculated by the following equation from FIG. Represented as shown.

PE4 = PER ・ B + ▲ ▼ ・ where PEL = ▲ ▼ PE3 = PER (B ・ D + ・ F) + ▲ ▼ (A ・ + ・) = PER (B ・ D + ・ F) + ▲ ▼ (A ・ + ) Here, from A = C ・ D ・ = B = E ・ F ・ F = ・ F PE2 = PER (B ・ D ・ H + B ・ ・ J + ＋ ・ F ・ L + ・ ・ N) + ▲ ▼ (A ・E ・ + A ・ ・ ＋＋ ・ C ・ + ・ ・) = PER (B ・ D ・ H + B ・ ・ J + + ・ F ・ L + ・ N) + ▲ ▼ (A ・ E ・ + A ・ ・ + + C ・ ・ + ・) Here, · C = C ·· = On the other hand, PE1 and PE0 can select the encoded outputs of <G> to <N> by a two-stage selector circuit.

The first selector circuit in the first stage outputs <G> to <N>(<G>
>, <H>), (<I>, <J>), (<K>, <L
>), (<M>, <N>) to be combined 4
It is divided into two blocks, and the inversion signals ▲ ▼ and ▲ ▼ of the 1st bit encode output and the inversion signals ▲ ▼ and ▲ of the 0th bit encode output of each block according to the first select signal.
One output is selected from each of ▼.

FIG. 7 is a diagram showing the configuration of the first selector circuit in the block (<G>, <M>) as an example. Even if the first selector circuit of another block has this (<G
>, <H>) blocks.

In FIG. 7, the selectors SG1 to SG4 and SH1 to SH4 are clocked inverters, but in reality, transfer gates are sufficient.

▲ ▼, ▲ ▼ are the first select signal ▲
The selectors SG1 and SG2 are selected according to ▼ and ^η , and ▲ ▼ and ▲ ▼ are selected according to the first select signal PER · H.
3, Selected by SG4. Also, ▲ ▼, ▲
▼ is selected by the respective selectors SH1 and SH2 according to the first select signal ▲ ▼ ・ G, ▲
▼ and ▲ ▼ are selected by the respective selectors SH3 and SH4 according to the first select signal PER.
In this way, one output is selected from each of the 1st bit encoded output of <G> and <H> and the 0th bit encoded output. The first bit encoded output selected here is PGH1 and the 0th bit encoded output is PGH0. (<I>, <J>), (<K>,
Even in the respective blocks of <L>) and (<M>, <N>), as shown in FIG.
The select signal selects the encoded output of the 1st bit and the 0th bit as described above.

As is apparent from FIG. 8, the first select signal for performing such selection is the zero detection signals G to N and the search signal PER.
Can be easily generated from a logic gate having two or three stages.

Next, the second selector circuit in the second stage will be described.

FIG. 9 is a diagram showing the configuration of the second selector circuit. In the figure, this second selector circuit is composed of selectors SGH1,0, SIJ1,0, SKL1,0, SMN1,0 composed of clocked inverters.
It is composed of.

This second selector circuit uses the second select signals SS1 to SS4 to select the inversion signals ▲ ▼, ▲ ▼,
1 of P encoder from ▲ ▼ and ▲ ▼
Select the bit 1 encode output PE1 and invert the encode output 0th bit ▲ ▼, ▲
The encoder output PE0 of the 0th bit of the P encoder is selected from ▼, ▲ ▼ and ▲ ▼.

That is, PE1 is ▲ ▼, ▲ ▼, ▲
The second select signal SS from among ▼ and ▲ ▼
Selector SGH1, SIJ1, SKL1, SMN1 by I to SS4
PE0, ▲ ,,
, ▼, the second select signal SS1 ~ S
It is selected by S4 via selectors SGH0, SIJ0, SKL0 and SMN0, respectively. FIG. 10 shows a relatively simplified version of the second select signal shown in FIG.

As is apparent from FIG. 10, such a second select signal is easily generated from the zero detection signals A to N and the search signal PER, and can be obtained with about three stages of logic gates.

As described above, the P encoder shown in FIG. 1 obtains its encoded outputs PE4 to PE0. Where the first
Returning to the figure, the generation circuit 2a for generating the first select signal of the first selector circuit 1a for selecting the encoded outputs of <G> and <H> is composed of three stages of logic gates. > And <J>, <K> and <L>, and <M> and <N> encoded output 1
Each of the generation circuits 2b, 2c, 2d that generate the first select signal corresponding to b, 1c, 1d is also composed of three stages of logic gates like the generation circuit 2a. Therefore, the first select signal is obtained from the input of search information via the four-stage logic gate.

The generation circuit 4a that generates the second select signals SS1 and SS2 of the second selector circuits 3a and 3b and the generation circuit 4b that generates the second select signals SS3 and SS4 of the second select circuits 3c and 3d have the same configuration. It is composed of three stages of logic gates. Therefore, the second select signals SS4 to SS1 are obtained from the input of search information through the five-stage logic gates.

In addition, the encoded output PE2 obtained by passing through a relatively large number of logic gates is obtained by using the logic signal in the process of generating the first and second select signals, and PE2 is used to generate the first and second select signals. It is possible to obtain in parallel. Further, PE3 is obtained by taking the logical sum of the second select signals SS1 and SS3. As a result, the circuit configuration for obtaining PE3 and PE2 can be simplified.

Therefore, the encode outputs PE4, PE3, PE2 of the P encoder shown in FIG.
It is obtained by delaying the logic gates of the stages. PE1 and PE0 are
Even if a clocked inverter is used for the selector and the delay of the select signal is taken into consideration, it can be obtained by delaying the logic gates in six stages.

On the other hand, in the conventional P encoder shown in FIG. 12, on the other hand, an encoded output can be obtained with a delay of about 5 stages of logic gates. However, the number of inputs of the logic gate in the P encoder shown in FIG. 1 is about 2 to 3 on average, whereas it is 4 or more in the conventional case. Therefore, it cannot always be said that the prior art is superior to this embodiment in terms of speed. Further, conventionally, the search is optimized only in one direction, and the additional circuit is required as described above in order to perform the search in both directions. It can be said that the superiority becomes remarkable.

[Effect of the Invention] As described above, according to the present invention, a part of the encoded output of the priority encoder is generated from the detection signal and the search signal, and the remaining part is generated from the encoded output for each unit search information. Since the encoded output is selected in accordance with the selection signal, the search speed can be increased without depending on the search direction.

[Brief description of drawings]

FIG. 1 is a block diagram of a priority encoder according to an embodiment of the present invention, and FIG. 2 is <G>-<in FIG.
N> configuration diagram, FIGS. 3 (A) and 3 (B) are explanatory diagrams of the operation of FIG. 2, FIG. 4 is a diagram showing a relationship between division of search information and a zero detection signal, and FIG. FIG. 6 is a configuration diagram of a circuit for generating a detection signal, FIG. 6 is a diagram showing a relationship between a zero detection signal and an encode output, FIG. 7 is a configuration diagram of a first selector circuit, and FIG. 8 is a diagram showing a first select signal. , FIG. 9 is a block diagram of the second selector circuit, FIG. 10 is a diagram showing the second select signal, FIG. 11 is a diagram showing the relationship between the search information and the encoded output, and FIG. 12 is the conventional 8-bit Fig. 13 is a block diagram of the priority encoder, Fig. 13 is a diagram for explaining the operation of Fig. 12, Fig. 14 is a block diagram of a conventional 32-bit priority encoder, and Fig. 15 is a diagram for speeding up the process of Fig. 14. It is a figure which shows a structure. (Explanation of Codes Representing Main Parts of the Drawing) <G> to <N> ... 4-bit P encoder 1a to 1d ... First selector circuit 2a to 2d ... First select signal generation circuit 3a, 3b ... Second selector Circuits 4a, 4b ... Second select signal generation circuit

Claims (1)

[Claims] 1. A search operation is performed to search for search information consisting of binary bit information in the direction of the most significant bit or the least significant bit, and the bit position which is one of the bit information is detected first. A priority encoder that gives an encoder output shown, performs a search operation for each of the unit search information obtained by dividing the search information into a predetermined bit length, and provides an encoded output for each, and the unit search information is Search means for respectively outputting a detection signal indicating that it is bit information; generation means for generating a part of an encoded output of the search information by each detection signal of the search means and a search signal indicating a search direction; Selection signal generating means for generating a selection signal based on the detection signal and the search signal; and the search means. A priority encoder, comprising: selecting means for selecting a predetermined encoded output as a part of the encoded output of the search information from each encoded output according to the selection signal.