JPH056262A - Multi-input adder circuit - Google Patents

Abstract

PURPOSE:To obtain the adder shortening execution time concerning the multi- input binary adder. CONSTITUTION:An inputted binary number is converted to a redundant binary number by encoding circuits 30 (30-1-30-4). The multi-input redundant binary adder combining the multiple steps of two-input redundant binary adders 32 (32-1-32-3) calculates the total sum of the converted binary numbers. A decoding circuit 34 converts the output of the multi-input redundant binary adder to a normal binary number and outputs it as a final added result. Thus, carry is not propagated for more than two digits in the redundant binary addition. Therefore, the addition can be executed at high speed in comparison with normal binary addition.

Description

Detailed Description of the Invention

[0001]

[Industrial application] Binary arithmetic circuits, especially a plurality of two
The present invention relates to a multi-input adder circuit that adds base number data.

[0002]

2. Description of the Related Art With the development of computer technology, there has been a strong demand for a high-speed binary number arithmetic unit. Particularly, an adder, which is a basic arithmetic device, is required to have extremely high performance because its performance may determine the overall performance of the digital processing device.

In recent years, processing of enormous amounts of data such as image data and audio data is often requested. In such an application, it is often necessary to quickly obtain the sum of many data. In addition, the demand for multi-input adders such as fast Fourier transforms and digital filters has been greatly increasing in recent years.

FIG. 5 shows a block diagram of a conventional multi-input adder. FIG. 5 shows an example in which four binary data are added. In FIG. 5, the four binary data are a,
Represented by b, c, d. First, the adder 10-1 adds a and b and outputs a + b. Next, the adder 10-2 outputs c and d.
Is added and c + d is output. Finally, the adder 10-3 adds a + b and c + d and outputs the final output a + b + c + d.

The above-mentioned three adders 10-1, 10-2,
And 10-3 is an adder for adding two binary numbers. Carry (carry) occurs when adding a normal binary number, but in the worst case, this carry is LS.
It may propagate from B to MSB. For example, 4
This is a case where binary numbers “1111” and “0001” are added. In this case, a carry from the LSB causes a carry to the next digit. Then, a carry to the next digit causes a carry to the next digit.
Hereinafter, the case where the next carry occurs due to the carry in this manner is referred to as carry propagation as described above.

That is, the carry propagation reaches the maximum number of input binary digits. Therefore, in the conventional binary number adder, the calculation time increases in proportion to the number of digits of the input.

[0007]

As described above, the conventional multi-input adder is constructed by connecting two-input adders in multiple stages. Therefore, when a multi-input adder is configured using a conventional adder in which carry propagates as described above,
It was not easy to execute the operation at high speed.

[0008]

In order to solve the above-mentioned problems, the present invention has a multi-input adder circuit in which two-input redundant binary adder circuits are connected in multiple stages.

In the present invention, the input binary number is converted into a redundant binary number by the encoding circuit. A multi-input redundant binary adder circuit, which is configured by connecting two-input redundant binary adders in multiple stages, adds the redundant binary number output from the encoding circuit and obtains the addition output. The addition output is converted into a normal binary number by the decoding circuit.

[0010]

In the addition using the redundant binary number, the carry does not propagate to the upper digits of two or more digits. For this reason, the conventional 2
The time until the addition result is output from the base number adder is shortened.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 1 shows an example in which four binary numbers are added as in the conventional example. In FIG. 1, four binary data are represented as a, b, c, d. Each binary data is encoded by the encoding circuits 30-1, 30-2, 30-3, 30-4.
Converted to redundant binary number. The converted redundant binary numbers are represented as a ^* , b ^* , c ^* , and d ^* , respectively. First, the redundant binary adder 32-1 adds the a ^* and b ^*, and outputs the a ^* + b ^*. Next, a redundant binary adder 32-2 adds the c ^* and d ^*, and outputs the c ^* + d ^*. Further, the redundant binary adder 32-3 adds a ^* + b ^* and c ^* + d ^* to obtain a ^* +
b ^* + c ^* + d ^* is output. Finally, a ^* + b ^* + c ^*
+ D ^* is converted from the redundant binary number to the normal binary number by the decoding circuit 34 and becomes the final output a + b + c + d.

In this embodiment, an encoding circuit 30 and a decoding circuit 34 are newly added as compared with the conventional multi-input adder. Therefore, although the calculation time increases by that amount, the calculation time of the redundant binary adder 32 is shorter than that of the conventional adder, so that the number of input binary numbers increases and the combination of two input (redundant binary ) If the number of stages of the adder is sufficiently large, the calculation time as a whole becomes shorter than the conventional one.

Here, the conventional calculation time and the calculation time of the present invention will be concretely compared. The present inventor calculated a specific time by using a design value of an actual gate array LSI.
The circuit example and the calculated value are shown below in comparison.

FIG. 2 is a block circuit diagram of a conventional normal binary 2-input adder. In FIG. 2, a _{0 to} a ₃ and b _{0 to} b ₃ respectively represent 4-bit input binary numbers.
In addition, y _{0 to} y ₃ are 4-bit binary numbers that are addition results. C _out is a carry to the upper digit. a ₀ ~
First, a ₃ and b _{0 to} b ₃ are HA (HalfAd
der). The output of HA is CLA (Carr
y Look Ahead) circuit. Finally, the output of the CLA circuit and the sum output of HA are EX-ORed.
By performing (Exclusive-OR), y ₀ ~
y ₃ is obtained. Further, C _out to the upper digit is output from the CLA circuit.

When such a circuit is used, for example, the execution time is 3 ns for HA, 4 ns for CLA circuit, and EX-O.
The R gate is 3 ns, and the total execution time is 3 (ns) +4 (ns) +3 (ns) = 10 (ns). This is the case where the input binary number is 4 bits, but when the bit width increases, the time increases by the amount of the CLA circuit. Since the CLA circuit is provided for every 4 bits, when the execution time T _d of the 4 k-bit (k = 1, 2, 3, ...) Adder is calculated, T _d = 4 k + 6 (ns). The execution time T _dm when this 2-input adder is connected in m stages is T _dm = m (4k + 6) (ns).

FIG. 3 is a block circuit diagram of a 2-input adder using redundant binary numbers. In FIG. 3, a and b each represent an input binary number of 4k bits. Further, y is a 4k-bit binary number that is the addition result. C _out is a carry to the upper digit. First, a and b are encoded circuits 4
Converted to a redundant binary number by 0. Redundant converted 2
The binary number is input to the 2-input redundant binary adder 42. The 2-input redundant binary adder 42 adds the converted redundant binary numbers and outputs the addition result. The addition result, which is a redundant binary number, is converted into a normal binary number by the decoding circuit 44 and output.

When such a circuit is used, for example, the execution time is 3 ns for the encoding circuit 40 and the redundant binary adder 42.
Is 8 ns and the decoding circuit 44 is (4 k + 6) ns, and the total execution time is 3 (ns) +8 (ns) +4 k + 6 (ns) = 4 k + 17 (ns). In the case of redundant binary number addition, since the carry does not propagate by two digits or more as described above, the execution time of the redundant binary adder 42 is 8 ns regardless of the number of bits (number of digits). However, since the decoding circuit 44 has a configuration similar to that of a normal binary adder, its execution time is the same as that of the above-described normal binary adder. Therefore, when the 2-input redundant binary adder 42 is connected in m stages, the execution time T _dm-r is T _dm-r = (4k + 9) + 8m (ns).

An example of the graph of the above calculation results is shown in FIG. The horizontal axis represents the number of stages of the 2-input adder, and the vertical axis represents execution time (ns). In this graph, the number of binary digits is 8.
Bit and 16-bit examples are shown. As can be seen from this graph, in the case of 8 bits, the number of stages is 3 or more, and the execution time can be shortened in the embodiment of the present invention. In the case of 16 bits, the number of stages is two or more, and the execution time can be shortened in the embodiment according to the present invention.

[0020]

As described above, according to the present invention,
The execution time can be shortened as compared with a normal multi-input adder. Further, the effect is more remarkable as the bit width is larger.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a multi-input adder according to the present invention.

FIG. 2 is a block circuit diagram of a conventional 2-input adder.

FIG. 3 is a block circuit diagram of a 2-input adder according to the present invention.

FIG. 4 is a graph comparing execution times of a conventional multi-input adder and an embodiment of the multi-input adder according to the present invention.

FIG. 5 is a configuration diagram of a conventional multi-input adder.

[Explanation of symbols]

 10-1, 10-2, 10-3 Adder 30-1, 30-2, 30-3 Encoding circuit 32-1, 32-2, 32-3 Redundant binary adder 34, 44 Decoding circuit 40 -1,40-2 Encoding circuit 42 Redundant binary adder

Claims (1)

Claim: What is claimed is: 1. A multi-input adder circuit for inputting a plurality of binary number data and calculating a sum thereof, an encoding circuit for converting an input binary number consisting of a normal binary number into a redundant binary number. A multi-input redundant binary adder for adding the redundant binary number output of the encoding circuit, and a decoding circuit for converting the redundant binary number output of the redundant binary number adder into a normal binary number. ,
A multi-input adder circuit, wherein the multi-input redundant binary adder is formed by connecting two-input redundant binary adders for adding two redundant binary numbers in multiple stages.