JPH07272491A - Semiconductor memory device and data-erasing method thereof - Google Patents

Abstract

PURPOSE:To uniform threshold values of memory cells in an erased state by faintly writing to the memory cells while a leak current resulting from an over-erasure flows. CONSTITUTION:All memory cells are first turned into an over-erased state and then, word lines 15 of the cells are raised to a write potential by a row decoder 14. The cells are faintly written in an FN tunneling system. A verification voltage Vcheck is impressed to each bit, line 12 during the writing. A sense amplifier 10 compares a V with the Vcheck, and detects the presence/absence of a leak current, from the presence/absence of a voltage decrease for every bit line. A flag is set when the current is zero. When all flags for the whole bit, lines are set, the faint writing is finished. In other words, all of the memory cells are erased in a state where the threshold values are uniformed. An erased state of the memory cell can be verified in a reduced time in this constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of electrically erasing and writing data and a data erasing method thereof.

[0002]

2. Description of the Related Art In a read-only semiconductor memory device having a plurality of memory cells, the stored contents are electrically erased.
A writable one is called a flash EEPROM. FIG. 2 shows a cross-sectional view of the memory cell 1 of the NOR flash EEPROM. This memory cell 1 is one cell transistor having a floating gate 2. In the cell transistor, a source 4 and a drain 5 are formed on a substrate 3. The floating gate 2 is formed above the tunnel oxide film 6 above the channel between the source 4 and the drain 5. Above the floating gate 2,
The control gate 8 is formed via the insulating film 7. The drain 5 is connected to the bit line 12 and the control gate 8 is connected to the word line 14. Data is written to this cell by hot electron injection, that is, by applying 0 V to the source region 4 and a high voltage to the drain region 5 to flow a channel current in the cell transistor and inject hot electrons into the floating gate 2. Done. On the other hand, data erasing is performed by applying a high voltage to the source region 4 and applying 0 V to the control gate 8 to extract electrons from the floating gate 2 to the source region 4.

Flash EE having the above memory cells
When erasing in the PROM, in order to avoid the peculiar problem of over-erasing, the erasing operation is performed after writing to all memory cells. After the erase operation is performed, an erase verification test is performed. In the erase verification test, the target data is read byte by byte to verify whether or not it is in the erased state. When it is confirmed that the data has not been erased, the erasure is performed again, and when it is confirmed that the data has been erased, the verification ends. This will be described in detail below with reference to the flowchart of FIG. First, it is confirmed whether or not the data recorded in the cell is "0" (S1), and when it is determined that the data is not "0" (S1, N), writing is performed (S2). When the data of all cells is judged to be "0" (S1,
Y), subsequently, an erase pulse is applied (S3), and the erase operation is performed. Next, when it is confirmed by the erase verification test that the data is not "1" (S4, N), the erase pulse is applied again to perform the erase operation (S3),
The procedure returns to the erase verification test (S4). When it is confirmed that all the data are "1" by repeating this operation (S
4, Y), erasing is completed.

[0004]

However, when the erase operation is performed without writing to the memory cell, the cell is in the over-erased state, its threshold value is lowered, and the leak current is reduced to the source 4. Flows into the channel between the drain and the drain 5. Due to this leak current, a high voltage cannot be applied to the drain 5, and therefore, writing by hot electron injection cannot rewrite the cell. Further, since the erase verification test only checks whether or not the cell is in the erased state, even if it is determined that the cell is in the erased state, it is not possible to determine whether it is in the overerased state or the predetermined erased state. Absent.

The present invention has been made in view of the above, and an object thereof is a semiconductor memory device in which the threshold voltage of a memory cell in an erased state is made uniform by performing weak writing while a leakage current due to overerasure is flowing. And a data erasing method thereof.

[0006]

According to a first aspect of the present invention, in a semiconductor memory device in which a plurality of memory cells each including a transistor having a control gate and a floating gate are arranged, a leak current flows from the floating gate of the memory cell. Up to the state, between the source and drain of the memory cell in which the electrons are extracted and the data is erased and the erase means for extracting the data, and the verify voltage is applied to generate a leak current between them. Means, and by applying a weak write voltage to the control gate of each of the memory cells while a leak current is flowing to each of the target memory cells, thereby injecting electrons into the floating gate of each of the memory cells, Threshold adjusting write means for performing weak writing to make each memory cell into an erased state in a state where thresholds are uniform Configured as the.

According to a second aspect of the present invention, in the first aspect, the threshold value adjustment writing means is configured to perform writing using an FN tunnel current.

[0008] A third aspect of the present invention is the first or second aspect of the invention, further comprising a determining means for determining whether or not the leak current is flowing.

In a fourth aspect based on the third aspect, a plurality of bit lines are provided, a plurality of memory cells are connected to each of the bit lines, and one end of each of the memory cells is connected to the bit line. , A predetermined voltage is applied to the other end, and each bit line is connected to the verification voltage applying means and the determining means, and the determining means determines that the voltage of the target bit line is It is configured to determine whether or not the leak current is flowing, based on whether the voltage corresponds to the predetermined voltage or the verification voltage.

A fifth aspect of the present invention is a data erasing method for a semiconductor memory device in which a plurality of memory cells each including a transistor having a control gate and a floating gate are arranged. From a floating gate of the memory cell to a state where a leak current flows. A step of extracting electrons to erase data, a step of applying a verification voltage between the source and the drain of the memory cell from which the electrons have been extracted to generate a leak current therebetween, and each memory cell By applying a weak write voltage to the control gate while a leak current is flowing in each of the target memory cells, electrons are injected into the floating gate of each of the memory cells to threshold each of the memory cells. And a step of performing weak writing to make an erased state in which the values are uniform.

[0011]

The eraser removes electrons from the floating gate of the memory cell and erases them. A verification voltage is applied between the source and the drain of the erased memory cell by the verification voltage applying means, and a leak current flows. While the leak current is flowing, the threshold adjustment write voltage is applied to the control gate of the memory cell. While the leak current is flowing, electrons are injected into the floating gate, weak writing is performed, and an erased state with a uniform threshold value is obtained.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows an apparatus according to an embodiment of the present invention. This device is a NOR flash EEPROM. Erasing a plurality of memory cells once in an over-erased state, that is, even when no selection voltage is applied to the gate, erases until a leak current flows, and weak programming is performed while the leak current flows. As a result, the threshold values in the erased state are made uniform. The weak writing referred to here is writing to bring the memory cells into an erased state with a uniform threshold value, and is different from so-called writing in general. In this embodiment,
The presence / absence of leakage current is monitored by applying a verification voltage to the bit line and checking whether the voltage drops.

An embodiment of the present invention will be described with reference to FIG. 1 showing a flash EEPROM. Verification voltage input terminal 9
Are connected to the sense amplifier 10 and the column decoder circuit 11. The sense amplifier 10 is connected to the column decoder circuit 11. The column decoder circuit 11 is connected to a plurality of bit lines 12, and each bit line 12 is connected to a plurality of memory cells 13. The memory cells 13, 13, ... Are each composed of a transistor having a floating gate as shown in FIG. A write inhibit flag (not shown) is provided corresponding to each bit line 12. Each write-inhibit flag is set when the thresholds of the memory cells of the target bit line in the erased state are aligned, and by setting this flag, weak writing is not performed thereafter, and these cells are set to Also prevents it from being written. On the other hand, the row decoder circuit 14 is connected to a plurality of word lines 15, and the word line 15 is connected to the control gate of the memory cell 13.

Next, the operation of the above device will be described. Figure 3
The memory cell 13 is erased according to the flowchart shown in FIG. This flowchart shows the operation for each bit line. First, an erase pulse is applied (S11), an erase operation is performed, and all memory cells are erased in an over-erased state. Then, the row decoder circuit 14 raises the potentials of the word lines 15 of all the memory cells to the writing potential, and weak writing is performed (S1).
2). This weak writing is based on the FN tunneling method, that is, the FN that flows when a voltage is applied to the control gate.
It uses a tunnel current. Therefore, writing can be performed even if a leak current flows. That is, since it is not necessary to apply a high voltage to the drain, weak writing is performed even in the state where a leak current flows. This weak writing can be performed without changing the conventional circuit configuration. During this weak write, the bit line 12
Is applied with a verification voltage V _check . In this state, each bit line voltage V and the verification voltage V _check are input to the sense amplifier 10 and compared. Sense amplifier 10
Determines the presence / absence of a leak current for each bit line based on the presence / absence of a voltage drop. That is, it is determined that the leak current is flowing in any of the memory cells connected to the bit line having the voltage drop (S13, N). When a leak current stops flowing in a bit line, it is known that the predetermined weak writing has been completed in the floating gates of all the memory cells connected to it, a flag is set for that bit line, and the memory cell connected to that bit line is set. About weak writing is prohibited. When the flags for all the bit lines are set, the weak writing for all memory cells is completed. That is, all the memory cells have been erased in the state where the threshold values are uniform.

As described above, whether or not there is a leak current in the memory cell, that is, whether or not each memory cell has been erased in a state where the threshold values are uniform, is applied with a verifying voltage V _check to the memory cell. , It is determined by whether or not the voltage V _check has dropped. That is, the potential V _{check applied} to the bit line 12 by the column decoder circuit 11 at the time of erase verification is separately prepared, and when the voltage drop is not within the allowable range, the memory cell is rewritten (Fail), and when it is within the allowable range, the erase is performed. Verification is completed (Pass). In this way, weak writing is performed on the cell in the over-erased state, and the cell transistor is brought into the erased state in a state where the thresholds thereof are aligned with a predetermined value.

According to the present embodiment described above, the erased state of a memory cell can be verified, for example, even when the memory cell 128 k word is formed by 512 × 256, the verification, that is, the reading can be performed by the number of bit lines. Since it is sufficient, the number of times of reading is 512. Further, it is also possible to verify a plurality of bit lines at the same time, and by doing so, the number of times of reading can be further reduced, so that the time required for erase verification can be shortened. On the other hand, in the conventional method,
For example, in a product of 1 M bits (128 k words × 8 bits), it is necessary to read all addresses, that is, read about 130,000 times for all memory cells.

According to the embodiment of the present invention, a plurality of memory cells are once erased to the over-erased state, and writing is performed to those cells only while the leak current due to the over-erased state is flowing. The threshold values of all the memory cells can be made equal to a predetermined value in the erased state. Further, it is possible to verify the memory cells on a plurality of bit lines at the same time, and in this case, the time required for erase verification can be further shortened. The degree of time reduction increases as the number of memory cells on the bit line increases.

[0018]

As described above, according to the present invention, a weak write operation for injecting electrons into the floating gate is performed only on the memory cell that has been erased until the leak current flows, only while the leak current is flowing. Each memory cell can be erased in a state where the threshold values are uniform.

[Brief description of drawings]

FIG. 1 is a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a memory cell.

FIG. 3 is a flowchart.

[Explanation of symbols]

 1 Memory Cell 2 Floating Gate Section 3 Substrate 4 Source Section 5 Drain Section 6 Tunnel Oxide Film 7 Insulating Film 8 Control Gate Section 9 Verification Voltage Input Terminal 10 Sense Amplifier 11 Column Decoder Circuit 12 Bit Line 13 Memory Cell 14 Row Decoder Circuit 15 Word line

Claims (5)

[Claims] 1. A semiconductor memory device in which a plurality of memory cells each including a transistor having a control gate and a floating gate are arranged, and data is erased by extracting electrons from the floating gate of the memory cell until a leak current flows. A verifying voltage applying means for applying a verifying voltage between the source and the drain of the memory cell from which electrons are extracted to generate a leak current between them, and a control gate of each memory cell Weak write voltage to
While a leak current is flowing through the target memory cells, electrons are injected into the floating gates of the memory cells by applying the leak current to the memory cells to erase the memory cells in a state where the thresholds are aligned. Let's do weak writing,
A semiconductor memory device comprising: a threshold value adjusting writing means. 2. The semiconductor memory device according to claim 1, wherein the threshold value adjusting write means performs write using an FN tunnel current. 3. The semiconductor memory device according to claim 1, further comprising a determination means for determining whether or not the leak current is flowing. 4. A plurality of bit lines are provided, a plurality of memory cells are connected to each bit line, one end of each memory cell is connected to the bit line, and a predetermined voltage is applied to the other end. Each of the bit lines is connected to the verification voltage application unit and the determination unit, and the determination unit is a voltage of the target bit line according to the predetermined voltage. 4. The semiconductor memory device according to claim 3, wherein it is configured to determine whether or not the leak current is flowing based on whether the voltage is a voltage according to the verification voltage. 5. A data erasing method for a semiconductor memory device in which a plurality of memory cells each comprising a transistor having a control gate and a floating gate are arranged, wherein electrons are extracted from the floating gate of the memory cell to a state where a leak current flows. Erasing data, and applying a verification voltage between the source and drain of the memory cell from which electrons have been extracted to generate a leak current therebetween, and to each memory cell control gate, Weak write voltage
While a leak current is flowing through the target memory cells, electrons are injected into the floating gates of the memory cells by applying the leak current to the memory cells to erase the memory cells in a state where the thresholds are aligned. And a step of causing weak writing to be performed.