JPH07272461A - Image signal and voice signal recording method and image signal and voice signal recording/reproducing apparatus - Google Patents

Abstract

PURPOSE:To utilize the data which can be read from the data written a number of times without waste by a method wherein an auxiliary data area is divided into a main area and a sub-area and, in the sub-area, maker-original auxiliary data are recorded after the pack recorded in a maker code. CONSTITUTION:When a header is '11110000', it is defined as 'maker code pack'. In a code pack PC1, a maker code is recorded as a maker identification code. Then 8 bits are recorded in a code pack PC2 and lower 2 bits are recorded in a code pack PC3 as the number TDP of total packs to follow. Further, from the lower third bit of the pack PC3 over a pack PC4, free bits are provided. An area in which auxiliary data accompanying images and voices are recorded is provided in addition to the area in which image signals and voice signals are recorded and the auxiliary data area is divided into a main area and a sub-area and, in the sub-area, maker-original auxiliary data are recorded after the pack recorded in a maker code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal, an audio signal, an image signal and an audio signal recording method for recording an auxiliary signal accompanying the video signal and the audio signal, and an image signal and an audio signal for recording and reproducing the signal. The present invention relates to a recording / reproducing device.

[0002]

2. Description of the Related Art VCRs for encoding and recording video signals and audio signals for recording and reproducing have been implemented. As an example of this, a component type D1 in a commercial VCR,
There is a composite method such as D2. Also, as a consumer digital VCR, an image compression type has been researched and developed.

By the way, the applicant of the present application filed Japanese Patent Application No. 5-27.
1311 etc., the digital VCR as described above.
I made a suggestion about the format. According to this, V
In each optional area of AUX, AAUX, subcode, and MIC, when the manufacturer code pack (F0h) is read, the subsequent areas are defined as the manufacturer's optional area. In the maker's optional area, each maker freely defines the data content of the pack,
This is an area for recording the pack. As shown in FIG. 40, the contents of the maker code pack are F0h as a pack header in PC0, 8 bits as a maker identification code in PC1, and the rest is open.

[0004]

When data is recorded on a recording medium (for example, a cassette tape), there is a possibility that the data may not be restored due to lateral scratches, clogs, etc. when the tape is reproduced. Therefore, the same data is usually written many times to protect it. However, in the configuration as shown in FIG. 40, it cannot be determined by actually reading how long the actually recorded maker's option data continues. Further, as shown in FIG. 41, when the data is written many times, if there is an error in the maker code pack in the middle of the data, it is impossible to know what is the end of one division, and the effect of writing many times weakens. Will end up. That is, in FIG. 41A, if 18 packs are recorded and an error occurs in F2, it becomes impossible to determine whether the pack is 17 packs or 18 packs as a whole. Further, as shown in FIG. 41B, when the same data is written twice, if the leading pack F0 of the second data becomes an error, the length of the first data can be determined. Even if all the data of the second time can be read correctly, it becomes necessary to invalidate all the read data.

Further, pack headers permitted to be used in the manufacturer's optional area are from F0h to FE.
There are 15 types up to h. Of these, F0h has a total of 14 types because its use is determined as a maker code pack, that is, a maker's option header.
However, with 14 different manufacturer code packs,
We cannot fully support the optional use of each manufacturer.

Therefore, an object of the present invention is to provide a recording / reproducing apparatus capable of effectively using the read data even for a large number of times of writing and increasing the number of apparent manufacturer's option packs. Especially.

[0007]

According to the present invention, in addition to an area in which an image signal is recorded and an area in which an audio signal is recorded, an area in which auxiliary data accompanying an image and audio is recorded is provided. In the image signal and audio signal recording method in which auxiliary data is packed and recorded in a fixed-length pack in the area, the auxiliary data area is divided into a main area and a sub area, and in the sub area, the manufacturer code The auxiliary signal unique to each manufacturer is recorded after the pack in which is recorded.

Further, according to the present invention, in addition to the area for recording the image signal and the area for recording the audio signal, an area for recording auxiliary data accompanying the image and sound is provided, and the auxiliary data area is fixed. In an image signal and audio signal recording / reproducing apparatus in which auxiliary data is packed and recorded in a long pack, the auxiliary data area is divided into a main area and a sub area, and a manufacturer code is recorded in the sub area. In addition, it is an image signal and audio signal recording / reproducing apparatus characterized in that auxiliary data unique to each manufacturer is recorded after the pack.

[0009]

The TDP indicating the total number of packs is recorded from PC2 of the manufacturer code pack to the second lower bit of PC3, and the lower third bit of PC3 to PC4 are released. Also, from the lower 3rd bit of PC3 to M of PC3
The first category code by SB and the second category code by PC4
Record the category code of.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to the drawings. To clarify the explanation, (A) Outline of digital VCR to which the present invention is applied (B) Track format, application ID and pack structure (C) Hierarchical structure of option pack (D) Digital VCR The recording / reproducing circuit will be described in this order.

(A) Digital V to which the present invention is applied
Outline of CR In a digital VCR that compresses / records / reproduces a digital video signal, a composite digital color video signal is separated into a luminance signal Y, color difference signals RY and BY, and DCT conversion, variable length coding and It is compressed by a high-efficiency compression method using high-efficiency encoding and recorded on a magnetic tape by a rotary head. SD system (525 lines / 60Hz, 625 lines / 50Hz)
And HD system (1125 lines / 60 Hz, 1250 lines / 50 Hz) can be set, and 1 in the case of SD system
The number of tracks per frame is 10 tracks (in the case of 525 lines / 60 Hz) or 12 tracks (in the case of 525 lines / 60 Hz), and in the case of the HD system, the number of tracks per frame is twice that of the SD system, that is, 20 tracks.
Track (for 1125 lines / 60Hz) or 2
There are 4 tracks (1250 lines / 50 Hz).

(B) Track format, application ID, and pack structure In this digital VCR, data management is easy, and as a system for making the digital VCR usable as a versatile recording / reproducing apparatus, the present application People have previously proposed a system called application ID. With this system, video preliminary data V
AUX (Video Auxiliary data), audio auxiliary data AAUX (Audio Auxiliary data) and subcode,
And a cassette with a memory having a memory called MIC (Memory In Cassette) becomes easy to manage. And
In the present invention, a pack is used to record audio data after-recording, video data insert, and data (broadcast station operation signal, medical signal, etc.) superimposed on the V blanking period.

First, the application ID system will be described. Digital V to which the present invention is applied
In the CR tape, as shown in FIG. 1A, diagonal tracks are formed on the tape. The number of tracks per frame is 10 and 12 tracks in the SD system and 20 and 24 tracks in the HD system.

FIG. 1B shows one track of a tape used in a digital VCR. At the truck entrance side,
There is a timing block for surely performing post-recording called ITI (Insert and Track Information). This is provided in order to accurately position the area when the data written in the subsequent area is post-recorded and rewritten.

In any digital signal recording / reproducing application device, since rewriting of data in a specific area is essential, the ITI area at the track entrance side is always present. That is, a large number of sync blocks having a short sync length are written in the area called ITI, and the sync numbers are assigned in order from the track entrance side. When trying to post-record, if any of the sync blocks in this ITI area can be detected, the current position on the track can be accurately determined from the number written there. Based on this, the post-recording area is determined. Generally, on the track entrance side, it is difficult to hit the head and is unstable due to mechanical precision and the like. Therefore, the detection probability is increased by shortening the sync length and writing a large number of sync blocks.

This ITI area, as shown in FIG.
Preamble, SSA, TIA and Postamble 4
It consists of two parts. The 1400-bit preamble is
It functions as the run-in of the PLL for digital signal reproduction. The SSA (Start Sync block Area) is used for this function, and is composed of 1 block of 30 bits and 61 blocks. Behind that is TIA (Trac
k Information Area). This is 3 blocks 90
Composed of bits. The TIA is an area for storing information related to the entire track, in which the original application ID APT (Application ID of
a Track) 3 bits, SP / LP indicating the track pitch
A total of 6 bits of 1 bit, 1 bit of reserve, and 1 bit of PF (Pilot Frame) indicating a reference frame of the servo system are stored. Finally there is 280 bits of postamble to earn a margin.

Further, in the above-mentioned apparatus, the applicant of the present invention previously mounted a circuit board provided with a memory IC on a cassette for accommodating a recording medium, and when this cassette was mounted on the apparatus, the data was written in this memory IC. It was proposed that the recorded data be read to assist recording / reproduction (Japanese Patent Application No. 4-165444 and Japanese Patent Application No. 4-287875).
issue). In the present application, this is called MIC.

The MIC contains information on the tape itself such as tape length, tape thickness, tape type, etc., as well as TOC (Table Of C
ontents) information, index information, character information, reproduction control information, timer recording information, etc. can be stored. Digital cassette tape with MIC
When it is connected to, for example, the data stored in the MIC is read out, and a still image (photo) is reproduced by skipping to a predetermined program, setting the reproduction order of the program, designating a scene of the predetermined program. It is also possible to record with a timer reservation.

The application ID is the APM in this MIC as well as the APT in the TIA area described above.
It is stored in the upper 3 bits of address 0 as (Application ID of MIC). The definition of the application ID is that the application ID defines the data structure,
I am trying. In short, the application ID does not determine the application example, but merely determines the data structure of the area. Therefore, the following meanings are given. APT: Determines the data structure on the track. APM ... Determines the data structure of the MIC. The value of APT defines the data structure on the track.

That is, the tracks after the ITI area are
As shown in FIG. 3, the data structure is divided into several areas, and the data structure such as the position on the track, the sync block structure, and the ECC structure for protecting data from errors is uniquely determined. Further, each area has an application ID that determines the data structure of the area. The meaning is simply as follows. Application ID of area n ... Determines the data structure of area n.

The application ID has a hierarchical structure as shown in FIG. That is, the area on the track is defined by the original application ID APT, and AP1 to APn are further defined in each area. The number of areas is defined by the APT. Although two layers are shown in FIG. 4, a layer may be further formed below it if necessary. Application I in MIC
The APM that is D is only one layer. As the value, the same value as the APT of the device is written by the digital VCR.

By the way, with this application ID system, a home digital VCR can be diverted as it is from its cassette, mechanism, servo system, ITI area generation detection circuit, etc. to a completely different product group, such as a data streamer or a multi-stream device. It is also possible to make something like a track digital audio tape recorder. In addition, even if one area is decided, its contents can be further defined by the application ID of that area, so when there is a certain application ID value there is video data, and when there is another value there is video / audio data or computer data. It becomes possible to set a very wide range of data settings.

Next, the situation when APT = 000 is shown in FIG. 5A. As shown in this figure, area 1, area 2, and area 3 are defined on the track. Then, the positions on those tracks, the sync block configuration, the ECC configuration for protecting data from errors, the gap for guaranteeing each area, and the overwrite margin for guaranteeing overwriting are determined. Further, each area has an application ID that determines the data structure of the area. The meaning is simply as follows. AP1 ... Determines the data structure of area 1. AP2 ... Determines the data structure of area 2. AP3 ... Determines the data structure of area 3.

The application I of each area
When D is 000, it is defined as follows. AP1 = 000 ... CVCR audio, AAUX data structure is adopted AP2 = 000 ... CVCR video, VAUX data structure is adopted AP3 = 000 ... CVCR subcode, ID data structure is taken Here CVCR: Home digital image signal and audio signal recording / reproducing apparatus AAUX: audio auxiliary data VAUX: video auxiliary data. That is, when implementing a home digital VCR, as shown in FIG. 5B, APT, AP1, AP2, AP3 = 000. Naturally, the APM also takes the value of 000.

When APT = 000, AAUX, VA
Each area of UX, subcode, and MIC is described by a common pack structure. As shown in FIG. 6, one pack is composed of 5 bytes, the first 1 byte is a header, and the remaining 4 bytes are data. A pack is a minimum unit of a data group, and one pack is formed by collecting related data.

The 8 bits of the header are divided into upper 4 bits and lower 4 bits to form a hierarchical structure. As shown in FIG. 7, the upper 4 bits are used as an upper header and the lower 4 bits are used as a lower header to form two layers. Further, by bit assignment of data, it is possible to extend to a layer below it.
Due to this layering, the contents of the pack are clearly systematized, and its expansion is easy. And this upper header,
The space of 256 by the lower header is prepared as a pack header table together with the contents of each pack (see FIG. 8). Each area described above is described using this. The pack structure is basically a fixed length of 5 bytes, but as an exception, a variable length pack structure is used only when character data is described in the MIC. This is to effectively use the limited buffer memory.

The audio and video areas are called the audio sector and the video sector, respectively. FIG. 9 shows the structure of the audio sector. The audio sector is composed of a preamble, a data part and a postamble. The preamble consists of 500 bits, 400 bits of run-up, and two presync blocks. The run-up is used as a run-up pattern for pulling in the PLL, and the pre-sync is used as pre-detection of the audio sync block. The data part consists of 10500 bits. The rear postamble is composed of 550 bits and is composed of one post sync block and 500 bits of guard area. The post sync is for confirming the end of this audio sector by the sync number of the ID, and the guard area is for guarding the audio sector so as not to bite into the video sector after it even after dubbing.

Each of the presync and postsync blocks is composed of 6 bytes as shown in FIGS. 10A and 10B. SP at the 6th byte of presync
There is a determination byte for / LP. SP for FFh, L for 00h
Represents P. The 6th byte of the post sync stores FFh as dummy data. The identification byte of SP / LP is
It also exists as the SP / LP flag in the above-mentioned TIA area, but this is for protection. If the value of the TIA area can be read, it is adopted, and if unreadable, the value of this area is adopted. 6 bytes each of pre-sync and post-sync are converted to 24-25 (24-bit data is converted to 2
The total bit length is: pre-sync 6 × 2 × 8 × 25 ÷ 24 = 100 bits post-sync 6 × 1 × 8 × 25 ÷ 24 = It will be 50 bits.

As shown in FIG. 11, the audio sync block is composed of 90 bytes to form one sync block. The first 5 bytes have the same structure as the presync and postsync. The data part is 77 bytes and has horizontal parity C.
It is protected by 1 (8 bytes) and vertical parity C2 (5 sync blocks). The audio sync block is composed of 14 sync blocks per track, and is recorded after being subjected to 24-25 conversion, so that the total bit length is 90 × 14 × 8 × 25 ÷ 24 = 10500 bits. The first 5 bytes of the data section are for AAUX, and one pack is configured by this, and 9 packs are prepared for one track. The numbers 0 to 8 in FIG. 11 represent the pack numbers in the track.

In FIG. 12, the 9 packs are extracted,
It is the figure described in the track direction. One video frame has 10 tracks for a 525 line / 60 Hz system and 12 tracks for a 625 line / 50 Hz system.
Composed of trucks. Audio and subcode are also recorded and reproduced according to this one video frame. In FIG. 12, numerals from 50 to 55 indicate pack header values (hexadecimal numbers). As can be seen from FIG. 12, the same pack is written 10 times on 10 tracks.
This part is called the main area. Essential items such as the sampling frequency and the number of quantization bits necessary for reproducing the audio signal are mainly stored in this area. It is written many times to protect data. This allows
The data in the main area can be reproduced even if the lateral scratches and one-sided channel clogs that often occur on tape transport occur.

The remaining packs other than that are all connected in order and used as an optional area. 12
Then, as shown in a, b, c, d, e, f, g, h, ..., the packs in the main area are pulled out in the direction of the arrows and connected. In one video frame, 30 packs (525 lines / 60 Hz) or 36 packs (625 lines / 50 Hz) of optional areas are prepared. Since this area is literally an option, a pack may be freely selected and described from the pack header table of FIG. 8 for each digital VCR.

The optional area is composed of common common options (for example, character data) and non-common maker's options whose contents can be independently decided by each maker. Since it is optional, only one or both may be present or both may not be present. If you do not have the information,
It is described using a pack without information (NO INFO pack). The application ID and the areas of both are separated by the appearance of the manufacturer code pack. The maker's optional area is after this pack. When the maker code pack is recorded, it is secured as a maker's optional area until the end of one video frame thereafter. The main area, optional area, common optional area, and manufacturer's optional area have AAUX, VAUX,
The subcode and MIC are all common. further,
The content to be written in the optional area is optional,
With respect to the subcode, since the error correction capability is low, the number of times of writing of the same pack is defined.

FIG. 13 shows the structure of the video sector.
The structure of the preamble and the postamble is the same as that of the audio sector shown in FIG. However, the number of bits in the postamble guard area is larger than that in the audio sector. As shown in FIG. 14, the video sync block has the same 90 bytes as audio, and one sync block is configured. The first 5 bytes have the same structure as the presync, postsync, and audio sync. The data portion is 77 bytes, and as shown in FIG. 15, horizontal parity C1 (8 bytes) and vertical parity C2 (11 bytes).
Sync block). The upper two sync blocks and the one sync block immediately before the C2 parity in FIG. 15 are dedicated VAUX syncs, and 77-byte data is used as VAUX data. Video data of a video signal compressed using DCT (discrete cosine transform) is stored except for the VAUX dedicated sync and the C2 sync. 149 video sync blocks per track
The sync block is composed of sync blocks, which are recorded after being subjected to 24-25 conversion, so that the total bit length is 90 × 149 × 8 × 25 ÷ 24 = 1111750 bits.

FIG. 16 shows the state of the VAUX dedicated sink. The upper two sinks of FIG. 16 are the upper two sinks of FIG.
The bottom sync in FIG. 16 corresponds to one sync immediately before C1 in FIG. When 77 bytes are carved in packs of 5 bytes, 2 bytes remain, but this is not used as a reserve. Like the audio, the numbers are 0-4
Up to 4, 45 packs are secured per track.

FIG. 17 is a diagram in which the 45 packs are extracted and described in the track direction. In FIG.
Numbers from 60 to 65 are packed header values (16
Indicates a decimal number. This is the main area. Like audio, I write the same pack 10 times on 10 tracks. Essential items such as a television system necessary for reproducing a video signal and an aspect ratio of a screen are mainly stored here. As a result, the data in the main area can be reproduced even with respect to the scratches in the lateral direction and one-channel clogs that are likely to occur in tape transport. All other remaining packs are connected in order and used as an optional area. In the same manner as the audio in FIG. 17, the packs in the main area are removed and connected in the directions of the arrows, like a, b, c, ....
One video frame provides an optional area of 390 packs (525 lines / 60 Hz) or 468 packs (625 lines / 50 Hz). The handling of the optional area is the same as that of audio.

In FIG. 15, the 135 sync blocks in the middle are the storage areas for video signals. BU in the figure
F0 to BUF26 each represent one buffering block. One buffering block is composed of 5 sync blocks, and there are 27 buffers per track.
There are 270 buffering blocks for 1 video frame and 10 tracks. That is, an effective area as an image is extracted from the image data of one frame, and digital data obtained by sampling the area is shuffled from various portions of the actual image to form 270 groups. One group is one buffering unit. For each unit, data compression is tried using a compression technique such as the DCT method, and processing is performed while evaluating whether or not it is within the target compression value as a whole. afterwards,
The compressed data of one buffering unit
The buffering blocks are packed into 5 syncs.

Next, the ID section will be described. IDP is
It is used in the same system in each sector of audio, video, and subcode, and is also used as a parity for protecting ID0 and ID1. FIG. 18 shows the contents of the ID section. The IDP is omitted.

In FIG. 18A, ID1 is a place for storing the in-track sync number. This is to sequentially number numbers 0 to 168 in binary notation from the pre-sync of the audio sector to the post-sync of the video sector. The track number within one video frame is entered in the lower 4 bits of ID0. Number one every two tracks. The two can be distinguished by the azimuth angle of the head. The contents of the upper 4 bits of ID0 change depending on the location of the sync. A sequence number of 4 bits is entered in the AAUX + audio sync and the video data sync shown in FIG. 18B. In this method, twelve numbers from 0000 to 1011 are assigned to each one video frame. This makes it possible to distinguish whether or not the data obtained during variable speed reproduction is in the same frame.

In the presync, postsync, and C2 parity syncs shown in FIGS. 9, 11, 13 and 15, the upper 3 bits of ID0 are the application ID,
AP1 and AP2 are stored. Therefore, AP1 is written 8 times and AP2 is written 14 times. In this way, by writing many times and distributing the locations, the reliability and protection of the application ID is ensured.

FIG. 19 is a block diagram of a subcode sector. Unlike the audio sector and video sector, the preamble and postamble of the subcode sector do not have a presync or postsync. It is also longer than other sectors. This is because the sub-code sector is used for frequent rewriting such as indexing, and because it is at the end of the track, the wrinkles tend to be wrinkled in the form in which all the shifts in the first half of the track are added. The sub-code sync block has at most 12 bytes as shown in FIG. The first 5 bytes have the same structure as the presync, postsync, audio sync, and video sync. The following 5 bytes are the data part, and the pack is composed of only this.

The horizontal parity C1 has only 2 bytes,
This protects the data section. Further, unlike audio and video, the so-called product code configuration of C1 and C2 is not used. This is because the subcodes are primarily for high speed searches, and cannot even pick up C2 parity within their limited envelope. Also, 2
The sync length is 12 for high-speed search up to about 00 times.
It's shortened to a bite. The subcode sync block is
There are 12 sync blocks per track.
Since the data is recorded after 25 conversion, the total bit length is 12 × 12 × 8 × 25 ÷ 24 = 1200 bits.

21A and 21B show the subcode I.
It is part D. In the sub-code sector, the contents of the data portion are different between the first half 5 tracks (525 lines / 60 Hz), the sixth track (625 lines / 50 Hz) and the latter half. There is an F / R flag in the MSB of ID0 for distinguishing between the first half portion and the second half portion during variable speed reproduction or high speed search. In the lower 3 bits, the application ID and AP3 are stored in the sync numbers 0 and 6. Other than the sync numbers 0 and 6, an index ID, a skip ID, and a PP ID (photo ID, picture ID) are stored in order from the top. The index ID is for conventional index search, and the skip ID is for cutting unnecessary scenes such as commercial cuts. The PP ID is for still image search. It is the absolute track number that straddles ID0 and ID1. In this method, absolute numbers are sequentially written from the head of the tape, and the MIC performs TOC search or the like based on this. The lower 4 bits of ID1 are an in-track sync number.

FIG. 22 shows the data part of the subcode.
Uppercase letters represent the main area and lowercase letters represent the optional area. Since one sync block of a subcode has one pack, the pack numbers in one track are 0 to 11 and a total of 12 packs. The same characters indicate the same pack contents.
You can see that the contents are different in the first half and the second half.

In the main area, the time code, recording date, and other items necessary for high-speed search are stored. It is called pack search because it can be searched in pack units.
The optional area cannot be used by connecting all of them like AAUX and VAUX. This is because, as described above, since the parity protection is weak, the contents of each track are moved up and down, and the same data is written and protected in the first and second tracks many times. Therefore, six packs can be used as the optional area in each of the first half and the second half. This is 52
5 lines / 60 Hz system, 625 lines / 50 Hz
The system is the same.

FIG. 23 shows the data structure of the MIC. M
The IC is also divided into a main area and an optional area, and is described in a pack structure except for the first byte and unused area (FFh). As described above, only the character data has a variable-length pack structure, and the rest is VAU.
It is stored in a pack structure of fixed length of 5 bytes, which is the same as X, AAUX, and subcode.

At the head address 0 of the MIC main area, there are an MIC application ID, APM 3 bits, and BCID (Basic Cassette ID) 4 bits. BC
The ID is a basic cassette ID and has the same content as an ID board for ID recognition (tape thickness, tape type, tape grade) in a cassette without MIC. ID board,
The MIC reading terminal plays the same role as the conventional 8 mm VCR recognition hole, which eliminates the need to make a hole in the cassette half as in the conventional case.
After address 1, three packs of a cassette ID, a tape length, and a title end are sequentially inserted. The cassette ID pack has a more specific value of the tape thickness and memory information about the MIC.

In the tape length pack, the tape manufacturer stores the tape length of the cassette in the number of tracks, and from this and the next title end pack (recording final position information, recording with absolute track number), the remaining tape is recorded. The amount can be calculated at once. Further, this recording last position information provides a convenient usability when the camcorder is used to reproduce and stop the recording, and then return to the original last recording position or when the timer is reserved.

The optional area is composed of optional events. Main area has addresses 0 to 1
While the fixed area of 16 bytes up to 5, the optional area is a variable-length area at address 16 and thereafter. The length of the area changes depending on the content, and when the event is erased, the remaining events are packed and stored in the address 16 direction. FFh is written in all the data that is no longer needed after the packing operation and is set as an unused area. The optional area is literally an option, and mainly stores the TOC and tag information indicating points on the tape, and character information such as a title related to the program. When reading the MIC, the next pack header appears every 5 bytes or every variable length byte (character data) depending on the contents of the pack header. However, if FFh in the unused area is read as a header, this is a NO INFO pack. Since it corresponds to the pack header of, the control microcomputer can detect that there is no information after that.

(C) Regarding Hierarchical Structure of Option Pack FIG. 24 is an extract of the pack header table shown in FIG. 8 and is a pack header relating to the present invention.
In FIG. 24, a pack group of upper bits = “1111” is shown. When it is "1110000", the manufacturer code pack is "11110001" to "1111111".
When it is “0”, it is specified as an option pack, and when it is “11111111”, it is specified as a NO INFO pack.

FIG. 25 is a diagram showing a maker code pack. When the header is "1110000", it is defined as a maker code pack. The manufacturer code is the manufacturer identification code on the PC1 and the 8 bits of the PC2 and P
Using the lower 2 bits of C3, the total number of packs (TDP) that follows is recorded. Further, it is opened from the lower 3rd bit of PC3 to PC4. This open area is used as a maker's option. That is,
In this area, data contents can be defined for each manufacturer.

The manufacturer's optional area of the VAUX area can record 39 packs per track when all the optional areas are used, and can record up to 24 tracks per frame when recording a high-definition television signal. = 936 packs can be recorded. Therefore, the total number of packs (TDP) is 10 in binary.
Bit needed. The area up to this TDP is a common optional area.

FIG. 26 is a flow chart of a reproducing process for a pack when the above TDP is used. In step 501, it is determined whether the read code is a maker code pack. In the case of a manufacturer code pack, the TDP in the pack is read (step 5)
02). After that, a memory area having a capacity for the number of packs designated by TDP is secured, and all data in the memory area is set to FFh (step 50).
3). After the option pack is read in step 504, if there is no error in the data to be written, it is written in the secured memory area (step 505). In step 506, it is judged whether or not the writing of data for one pack is completed. If not completed, the process returns to step 505. On the other hand, when the writing of data for one pack is completed, it is determined in step 507 whether or not the data of all the maker's option packs have been read. If it has not been read, the process returns to step 504. The total pack number TDP recorded in the manufacturer code pack is used for the determination in step 507. On the other hand, if all the maker's option packs have been read, the process proceeds to step 508.

At step 508, it is judged whether or not the reading of the data for one video frame is completed. When finished, the series of processes is finished. On the other hand, if it is not determined that the reading of the data for one video frame is completed, the process proceeds to step 509.

In step 509, the next pack is read, and in step 510 pack header = FFh (NO
INFO pack) or an error is determined. If the pack header ≠ FFh or an error, the process returns to step 505. As a result, the data is written many times. On the other hand, if pack header = FFh or an error, the pointer of the storage area is advanced by 5 bytes (1 pack) (step 511) and the processing from step 508 is repeated. As described above, since the required number of option packs can be specified by TDP, the read data can be effectively recorded.

FIG. 27 is a diagram of a maker code pack when the option pack has a hierarchical structure. Data similar to that of the maker code pack shown in FIG. 26 is stored from the MSBs of the PC1 and PC2 to the lower second bit of the PC3. The first category code is written in the remaining bits of PC3, and the second category code is written in PC4. The first category code is defined as a layer one level below the manufacturer code, and the second category code is defined as a layer one level below the first category code.

FIG. 28 is a diagram showing the hierarchical structure described with reference to FIG. As can be seen from FIG. 28, option packs having headers F1h to FEh are arranged below the category code.

FIG. 29 is a diagram showing an example of the hierarchical structure of FIG. In this case, the company code (A
Inc.) has the first category code as the first category code (commercial video, computer, business) and second
The subdivision of the categories shown in the first category code (commercial video-digital VCR, television video integrated type, computer-data streamer, commercial-aircraft VCR) is defined as the category code of the. The usability is improved by adopting a different hierarchical structure.

The optional area is composed of optional events. By making the main area into such a hierarchical structure, it is possible to specify a spatially finite option pack according to each application example. Therefore, the number of maker's option packs can be increased and the application can be expanded freely.

(D) Digital VCR Recording / Reproducing Circuit FIGS. 30 to 35 show a digital VCR to which the present invention is applied.
It is a block diagram of a recording system of CR. This digital VC
At R, the composite color video signal is separated into a digital luminance signal Y, color difference signals RY and BY, and DC
The data is compressed and recorded by a high-efficiency coding method using T conversion and variable length coding. Then, using the MIC described above, V
Data for the blanking period is recorded.

In FIG. 30, a television signal is received by the antenna 1. The signal received by the antenna 1 is supplied to the tuner 2. The tuner 2 demodulates this television signal into a composite color video signal and audio signal of the NTSC or PAL system.
The composite video signal from the tuner 2 is supplied to the switch 3a, and the audio signal is supplied to the switch 3b.

An analog composite video color video signal is also supplied to the external video input terminal 4. The composite video signal from the external video input terminal 4 is supplied to the switch 3a. External audio input terminal 5
An analog audio signal is supplied to. This analog audio signal is supplied to the switch 3b.

The switch 3a selects the composite video signal from the tuner section 2 and the composite video signal from the external video input terminal 4. The output of the switch 3a is supplied to the Y / C separation circuit 6 and the synchronization separation circuit 11. The Y / C separation circuit 6 converts the composite video signal from the luminance signal (Y) and the color difference signal (R-
Y, B-Y) are separated.

The luminance signal (Y) and the color difference signals (RY, BY) from the Y / C separation circuit 6 are passed through the low pass filter 7.
A / D converters 8a, 8b, 8c via a, 7b, 7c
Is supplied to. The low pass filters 7a, 7b and 7c are
The band of the input signal is band-limited in order to remove the aliasing distortion. The cutoff frequency of the low-pass filters 7a, 7b, 7c is, for example, 5.75 MH for the luminance signal (Y, sampling frequency 13.5 MHz (rate of 4)).
z, 2.75M at a sampling frequency of 6.75 MHz (rate of 2) for color difference signals (RY, BY)
Hz and a sampling frequency of 3.375 MHz (rate of 1) is set to 1.45 MHz.

The sync separation circuit 11 extracts the vertical sync signal (V sync) and the horizontal sync signal (H sync).
The vertical sync signal (V sync) and the horizontal sync signal (H sync) from the sync separation circuit 11 are PLL (Phase Locked L).
oop) circuit 12. With this PLL circuit 12,
Basic sampling frequency 1 locked to the input video signal
A 3.5 MHz clock is formed. In addition, this 1
The sampling frequency of 3.5 MHz is 4 as described above.
Called the rate of. This basic sampling frequency 1
A 3.5 MHz clock is supplied to the A / D converter 8a. Also, this basic sampling frequency 13.5MHz
Is supplied to the frequency divider 13, and the frequency divider 13 forms a clock having a frequency ¼ of the basic sampling frequency. A clock (rate of 1) having a frequency 1/4 of the basic sampling frequency is used as the A / D converters 8b and 8c.
Is supplied to.

Digital component video signals Y, RY, BY from the A / D converters 8a, 8b, 8c
Are supplied to the blocking circuit 9. The blocking circuit 9 processes the data on the real screen into blocks of 8 samples × 8 lines. The output of the blocking circuit 9 is supplied to the shuffling circuit 10 and shuffled. The shuffling is performed in order to avoid intensive loss of data recorded on the tape due to head clogs or lateral scratches on the tape. At the same time, the shuffling circuit 10 rearranges the luminance signal and the color difference signal so that they can be easily processed in the subsequent stage.

The output of the shuffling circuit 10 is supplied to the data compression encoding unit 14. Data compression encoding unit 14
Is a compression circuit using the DCT method or variable-length coding, an estimator for estimating whether the result can be compressed up to a predetermined data amount, and a quantizer for finally quantizing based on the discrimination result. The video data thus compressed is packed in a predetermined sync block by a framing circuit 15 according to a predetermined rule. The output of the framing circuit 15 is supplied to the synthesizing circuit 16.

On the other hand, the switch 3b selects the audio signal from the tuner 2 and the audio signal from the external audio signal input terminal 5. The output of the switch 3b is supplied to the A / D converter 21. A / D converter 21
At, the analog audio signal is digitized. The digital audio signal thus obtained is supplied to the shuffling circuit 22. Shuffling circuit 2
At 2, the digital audio data is shuffled. The output of the shuffling circuit 22 is supplied to the framing circuit 23. The framing circuit 23 packs the audio data in the audio sync block. The output of the framing circuit 23 is the synthesis circuit 24.
Is supplied to.

The mode processing microcomputer 34 is a microcomputer having a man-machine interface, and operates in synchronization with the field frequency of the television image of 60 Hz or 50 Hz. Since the signal processing microcomputer 20 operates on the side closer to the machine, for example, the number of rotations of the drum is 9
It operates in synchronization with 000 rpm and 150 Hz.

In the mode processing microcomputer 34, pack data of video auxiliary data VAUX, audio auxiliary data AAUX, and subcode is generated, and "title end" is generated.
The absolute track number included in the pack or the like is generated by the signal processing microcomputer 20. TTC stored in subcode
(Time title code) is also the signal processing microcomputer 2
It is generated by 0.

The video preliminary data VAUX generated by the signal processing microcomputer 20 is supplied to the synthesizing circuit 16 via the VAUX circuit 17. The combining circuit 16 combines the video preliminary data VAUX with the output of the framing circuit 15. The audio preliminary data AAUX generated by the signal processing microcomputer 20 is supplied to the synthesis circuit 24 via the AAUX circuit 19. The synthesis circuit 24 outputs the audio preliminary data AA to the output of the framing circuit 23.
UX is synthesized. VDAT output from the synthesizing circuit 16
ADATA which is the output of A (video data) and 24
(Audio data) is supplied to the switch 26.

Based on the output of the signal processing microcomputer 20, the subcode circuit 18 outputs the data SID of the ID portion and AP3,
Subcode pack data SDATA is generated in it,
These are supplied to the switch 26. Further, the sync generation circuit 25 generates each ID portion of AV (audio / video), pre-sync and post-sync,
This is supplied to the switch 26. Also, in circuit 25
P1 and AP2 are generated and fitted into a predetermined ID part. With the switch 26, the output of the circuit 25 and AD
ATA, VDATA, SID, and SDATA are switched at a predetermined timing.

The output of the switch circuit 26 is supplied to the error correction code generation circuit 27. Error correction code generation circuit 2
At 7, a predetermined parity is added. The output of the error correction code generation circuit 27 is supplied to the randomization circuit 29. The randomization circuit 29 performs randomization so that the recorded data is not biased. The output of the randomization circuit 29 is supplied to the 24/25 conversion circuit 30, and 24-bit data is converted into 25-bit data. As a result, the DC component which is a problem during magnetic recording / reproduction is removed. Here, although not shown, a coding process (1 / 1-D ² ) of PRIV (Partial Response, Class 4) suitable for digital recording is also performed.

The output of the 24/25 conversion circuit 30 is supplied to the synthesis circuit 31. The synthesizing circuit 31 synthesizes the output pattern of the 24/25 conversion circuit 30 with the audio / video sync pattern and the subcode sync pattern. The output of the combining circuit 31 is supplied to the switch 32.

The APT, SP / LP, and PF data are output from the mode processing microcomputer 34 that manages the mode of the entire VCR, and these data are output to the ITI circuit 33.
Is supplied to. The ITI circuit 33 generates ITI sector data. The switch 32 outputs the data and the amble pattern by switching the timing.

The data switched by the switch 32 is further switched by the switch 35 in accordance with the head switching timing. The output of the switch 35 is amplified by the head amplifiers 36a and 36b, and the head 3
7a, 37b.

The switch 40 is an external switch of the VCR body and is a switch group for instructing recording, reproduction and the like. There is a switch for setting the SP / LP recording mode, and the result is instructed to the mechanical control microcomputer 28 and the signal processing microcomputer 20. A MIC microcomputer 38 is connected to the mode processing microcomputer 34. The MIC microcomputer 38 generates pack data in the APM and MIC. This data is transmitted via the MIC contact 39 to the MIC.
It is supplied to the attached cassette 41.

As described above, in the digital VCR to which the present invention is applied, the digital luminance signal (Y) and the color difference signals (RY, BY) are compressed and recorded in the video sector, and the digital audio signal is audio. Recorded in the sector. Also, VAUX and AAUX are recorded. The VAUX data and the AAUX data are recorded in a pack structure.

FIG. 31 is a detailed block diagram of the recording side circuit relating to VAUX data. Mode processing microcomputer 3
In the pack data generation unit 51 of No. 4, pack data to be stored in the VAUX area is generated and converted into serial data by the P / S conversion circuit 52. This data is processed by the signal processing microcomputer 2 according to the communication protocol between the microcomputers.
0 to the S / P conversion circuit 53. After being converted into parallel data by the S / P conversion circuit 53, it is stored in the buffer 55 via the switch 54. Also, in the pack data output from the S / P conversion circuit 53, each pack header is detected by the pack header 56. Further, it is determined whether or not the pack requires an absolute track number. When necessary, the switch 54 is switched so that 23-bit data is output from the absolute track number generation circuit 57 every 8 bits and stored in the buffer 55. This storage area is all PC1, PC2 and P
The fixed position is C3. The S / P conversion circuit 53 is a serial I / O in the microcomputer, the pack header detection circuit 56, the absolute track number generation circuit 57 and the switch 54 are microcomputer programs, and the buffer 55 is a RAM in the microcomputer. It Since the processing of the pack structure can be completed in the processing time of the microcomputer, the cost-effective microcomputer is used in this way.

The data stored in the buffer 55 is VA
The signals are sequentially read by the timing signal of the write-side timing controller 58 of the UX circuit 17. At this time, the first half of the 6 packs are stored in the FIFO 6 as main area data.
0, and the subsequent 390 packs are supplied to the FIFO 61 as optional area data. The data is supplied to the FIFO 60 and the FIFO 61 by switching the switch 59.

By the way, the data of VAUX is shown in FIG. 32A.
In-track sync numbers 19, 20, and 156
It is stored in the part of. The track number in the frame is 0,
At 2, 4, 6 and 8-Sync number 156 on azimuth
The main area in the latter half of the year, again 1, 3, 5, 7 and 9
There is a main area in the first half of sync number 19 at + azimuth. FIG. 32B shows this with one video frame. As can be seen from FIG. 32B, nMAI
It becomes the main area when N = “L”. Such a signal is generated by the read side timing controller 62 and supplied to the switch 63. As a result, the data of the FIFO 60 or the FIFO 61 is supplied to the synthesis circuit 16 via the switch 63.

Here, when nNAIN = "L", the data in the main area FIFO 60 is repeatedly read 10 times (525 lines / 60 Hz) or 12 times (625 lines / 50 Hz). When nMAIN = “H”, the data in the optional area FIFO 61 is 1
It is read once for each video frame.

FIG. 33 shows V in the mode processing microcomputer 34.
It is a block diagram of an AUX pack data generation circuit. VA
The UX pack data generation circuit is divided into a main area and an optional area. A signal such as closed caption is input to the main area data collection / generation circuit 71. Main area data collection and generation circuit 7
In No. 1, a data group of television channels, source codes, tuner categories, copy sources, copy generations, etc. is generated based on these data. This data group is assembled into a main pack bit byte structure, and a pack header is added by the switch 72.
After that, the data is converted into serial data by the P / S conversion circuit 74 via the switch 73 and supplied to the signal processing microcomputer 20.

On the other hand, teletext data, program titles, etc. are input from the tuner to the optional area data collection / generation circuit 75. The VCR set determines which pack is recorded in the optional area. The pack header is set by the pack header setting circuit 76, and the switch 77 is switched to add the pack header to the data. Then switch 7
After being converted into serial data by the P / S conversion circuit 74 via 3, the signal is supplied to the signal processing microcomputer 20. In addition,
The P / S conversion circuit 74 is a serial I / O in the microcomputer.
And the other circuit is a microcomputer program.

FIG. 34 shows A in the mode processing microcomputer 34.
It is a block diagram of an AUX pack data generation circuit. The operation of each circuit is almost the same as that of the VAUX pack data generation circuit shown in FIG. However, in this case, the program title input from the tuner may be a title of a music program such as digital audio PCM broadcasting, in addition to the title of a television program. Some tuners, such as so-called A-mode and B-mode digital voices, have a predetermined sampling frequency, number of quantization bits, and the like. Further, when configuring the closed caption pack (55h) of AAUX, the closed caption signal in the vertical blanking is obtained from the tuner, and the audio information is extracted from the decoder audio information extraction circuit 81. This is the AAUX source pack (5
0h) and the source control pack (51h).

FIG. 35 is a detailed circuit block diagram of the MIC processing microcomputer 38. The serial data supplied from the mode processing microcomputer 34 is converted into parallel data by the S / P conversion circuit 91. In the main area shown in FIG. 23, the VCR side rewrites the APM at address 0, the ME flag in the cassette ID pack, and the title end pack. In this, RE (Rec
ording proofed events Exist) flag and ME (MIC Err)
or) flag is generated in the MIC microcomputer 38,
Others are supplied from the mode processing microcomputer 34. S /
Of the outputs of the P conversion circuit 91, the absolute track number, AP
The M, SL flag and BF flag are supplied to the main area data collection / generation circuit 92, and a predetermined data group is generated. This data group is supplied to one end of the fixed terminal of the switch 97 via the switch 94. The switch 94 supplies the pack header 1Fh,
It is turned on only when writing the title end.

On the other hand, among the output data of the S / P conversion circuit 91, data such as recording date, recording time, minute and second, program title, etc. are supplied to the optional area data collection and generation circuit 93. Note that the above data is, for example, the case of a timer recording reservation event. In the pack header setting circuit 95, the optional area data collection / generation circuit 9
The pack header of the data used for 3 is set.
The pack header and data are supplied to the other end of the fixed terminal of the switch 97 via the switch 96. Switch 9
The data selected in 7 is converted into a predetermined format by the IIC bus interface circuit 98 and supplied to the MIC contact 39. The switching timing of each switch is adjusted by the timing adjustment circuit 99.

By the way, in the case of MIC, the simplified MI is used.
It can be considered to be used in a C writing device or the like. In this case, the S / P conversion circuit 91 shown in FIG.
Is excluded.

Next, a digital V to which the present invention is applied
The configuration on the reproducing side of the CR will be described with reference to FIGS. 36 and 37. In FIG. 36, heads 101a and 101
The signals obtained from b are the head amplifiers 102a and 102a.
It is amplified by b and switched by the switch 103. The output of the switch 103 is supplied to the equalizer circuit 104. In order to improve the electromagnetic conversion characteristics of the tape and the magnetic head during recording, so-called emphasis processing (for example, partial response, class 4) is performed, but the equalizer circuit 104 performs the reverse processing.

The output of the equalizer circuit 104 is supplied to the A / D converter 106, and the clock extraction circuit 10
5 is supplied. The clock extraction circuit 105 extracts the clock component. With this extracted clock, the output of the equalizer circuit 104 is digitized by using the A / D converter 106. The 1-bit data thus obtained is F
Written to the IFO 107.

The output of the FIFO 107 is supplied to the sync pattern detection circuit 108. Sync pattern detection circuit 1
The sync pattern of each area is supplied to 08 via the switch 109. The switch 109 is switched by the output of the timing circuit 113. The sync pattern detection circuit 108 has a so-called flywheel configuration, and once a sync pattern is detected, it is checked whether or not the same sync pattern comes again after a predetermined sync block length. If this is correct three times or more, for example, it is regarded as true to prevent erroneous detection.

When the sync pattern is detected in this way,
The shift amount of which part is extracted from the output of each stage of the FIFO 107 to obtain one sync block is determined. Therefore, based on this, the switch 110 fetches necessary bits into the sync block confirmation latch 111. As a result, the fetched sync number is fetched by the extraction circuit 112 and input to the timing circuit 113. The position of the head on the track can be known from the read sync number, so that the switch 109 or the switch 114 can be switched.

The switch 114 is switched to the lower side in the ITI sector, and the IT circuit is separated by the separation circuit 115.
The I sync pattern is separated and supplied to the ITI decoder 116. Since the ITI area is coded and recorded, by decoding it, AP
Each data of T, SP / LP and PF can be taken out. This is a mode processing microcomputer 11 that is connected to an operation key 118 outside the set and determines the operation mode of the entire set.
Given to 7.

The mode processing microcomputer 117 is connected to the MIC microcomputer 119 for managing the APM and the like. MI
Information from the cassette 121 with C is the MIC contact 120.
It is given to the microcomputer 119 with MIC via the, and performs the processing of the MIC while sharing the role with the mode processing microcomputer 117. Depending on the set, the MIC microcomputer may be omitted and the mode processing microcomputer 117 may perform the MIC processing. The mode processing microcomputer 117 cooperates with the mechanical control microcomputer 128 and the signal processing microcomputer 151 to perform system control of the entire set.

In the case of the A / V sector or subcode sector, the switch 114 is switched to the upper side. After the sync pattern of each sector is extracted by the separation circuit 122, it is further supplied to the inverse random number generation circuit 124 through the 24/25 inverse conversion circuit 123 and is returned to the original data string. The data thus extracted is the error correction circuit 12
5 is supplied.

The error correction circuit 125 detects and corrects error data. An uncorrectable data is output with an error flag. Each data is switched by the switch 126.

The circuit 127 is in charge of the ID part of the A / V sector and each of the presync and postsync, and is stored in each of the sync number, track number, presync and postsync. SP /
Each signal of LP is extracted. These are given to the timing circuit 113 to create various timings.

Further, the circuit 127 extracts AP1 and AP2 and supplies them to the mode processing microcomputer 117.
The format is checked. AP1, AP2 = 00
When it is 0, the area 2 is defined as an image data area and operates normally, but in other cases, warning operation such as warning processing is performed.

Regarding the SP / LP, the mode processing microcomputer 117 makes a comparative examination with that obtained from ITI. In the ITI area, S 3 times in the TIA area.
The P / LP information is written, and the reliability is improved by only the majority vote processing. There are two presyncs each for audio and video, and SP / LP information is written at four locations in total. Here, too, the majority vote is taken and reliability is increased. If the two do not finally match, the one in the ITI area is preferentially adopted.

The reproduced data from the video sector is shown in FIG.
The switch 129 of 7 separates the video data from the VAUX data. The video data is supplied to the deframing circuit 130 together with the error flag. The deframing circuit 130 performs inverse framing conversion.

The image data is supplied to the data decompression coding section which is composed of the dequantization circuit 131 and the decompression circuit 132, and is restored to the data before compression. Then, the deshuffling circuit 133 and the deblocking circuit 134 return the data to the original image space arrangement.

After the deshuffling, the processing is performed separately for three systems of the luminance signal (Y) and the color difference signals (RY, BY). Then, it is converted back into an analog signal by the D / A converters 135a, 135b and 135c. At this time, the output divided by the oscillation circuit 139 and the frequency divider 140 is used. That is, the luminance signal (Y) is 13.5 MHz, and the color difference signals RY and BY are 6.75 MHz or 3.375 MH.
z is used.

The signals thus obtained are combined in the Y / C combining circuit 136, and further combined in the combining circuit 137 with the synchronizing signal output of the synchronizing signal generating circuit 141.

The reproduction data from the audio sector is
The switch 143 separates the audio data from the AAUX data. The audio data is returned to the original time axis by the next deshuffling circuit 145. At this time, if necessary, the interpolation process of the audio data is performed based on the error flag. This signal is supplied to the D / A converter 146, converted into an analog audio signal, and then output from the analog audio output terminal 152 via the switch 147 while keeping timing such as lip sync with video data.

The respective data of VAUX and AAUX separated by the switches 129 and 143 are supplied to the VAUX circuit 148 and AAUX circuit 150, and preprocessing such as majority processing at the time of multiple writing is performed with reference to the error flag. Done. The ID portion and the data portion of the subcode sector are supplied to the subcode circuit 149. Also here, the preprocessing such as the majority processing is performed with reference to the error flag. After that, the signal is supplied to the signal processing microcomputer 151, and the final reading operation is performed. At this time, the errors that cannot be removed are given to the signal processing microcomputer 151 as VAUXER, SUBER and AAUXER, respectively. Here, AP3 is extracted by the sub-code circuit 149. The AP3 is supplied to the mode processing microcomputer 117 via the signal processing microcomputer 151. The mode processing microcomputer 117 checks the format. When AP3 = 000, area 3 is defined as a subcode area and normal processing is performed. On the other hand, when AP3 ≠ 000, warning processing such as warning processing is performed.

Supplementing the error processing here,
The signal processing microcomputer 151 further performs analogy from the context of the pack of each data, and performs propagation error processing and data repair processing. The data result thus determined is supplied to the mode processing microcomputer 117. This data result is used as a factor in determining the movement of the entire set.

FIG. 38 is a detailed circuit block diagram of the VAUX circuit 148. It should be noted that the preprocessing is not a majority vote processing but a method of not writing to the memory when an error occurs. The VAUX data input via the switch 129 is the write timing pulse output from the write-side controller 162 (see FIG. 32).
Then, the switch 161 sorts the data into main area data and optional area data. The pack data in the main area is stored in the pack header detection circuit 163.
Will detect the pack header. The output of the pack header detection circuit 163 is applied to the switch 164.
As a result, the switch 164 is switched. Then, the data is written in the main area memory 165 only when there is no error. The memory 165 has a 9-bit configuration, and a halftone dot portion serves as an error flag storage bit.

As the initial setting of the memory for the main area, all contents are set to 1 (no information) for each video frame. And, in case of error, no processing is performed. On the other hand, when there is no error, the data is written and 0 is written in the error flag. Since the same pack is written 10 or 12 times in the main area, the place where 1 is set in the error flag at the end of one video frame is finally recognized as an error.

By the way, since the optional area is basically written only once, the error flag is written as it is in the FIFO 166 for the optional area together with the data. The capacity of the FIFO 166 is prepared for the manufacturer's option. Then, when the error flag is not supplied to the FIFO 166, the data is written. Read side timing controller 167
The data stored in the memory 165 and the FIFO are switched by switching the switch 168 and the switch 169 with.
The data stored in 166 is supplied to the signal processing microcomputer 151. Although the VAUX circuit for VAUX data has been described here, the AAUX circuit including a FIFO or the like for AAUX data has the same configuration and operation.

FIG. 39 is a detailed circuit block diagram of the signal processing microcomputer 151. The signal processing microcomputer 151 performs analysis based on the pack data and the error flag supplied from the VAUX circuit 148. That is, VAUX
Pack data VAUXDT output from the circuit 148
Is supplied to the pack header identification circuit 171, the pack data is distributed, and also supplied to the switch 172. On the other hand, the error data VAUXER is supplied to the read / write circuit 177. Read / write circuit 1
The switch 172 is controlled by the output control signal of 77. The pack data passed through the switch 172 is written in the memory 173. Here, there is no distinction between main area data and optional area data.

If the data is pack data in the main area, no write processing is performed during VAUXER, as in the VAUX circuit 148. As a result, repair can be performed with a value of at least one video frame before. Since it is considered that the content of the main area has a very strong correlation with the value of one video frame before, there is no problem even if this processing is performed. On the other hand, in the case of the pack data of the optional area, it is considered that there is no correlation with the value of one video frame before, so the error propagation processing is performed in the pack unit.

This method is basically carried out by changing all data to FFh if there is an error in the packed data having a fixed length of 5 bytes, but it is also necessary to deal with individual packs. Becomes For example, in the case of Teletext packs, the packs will continue,
Even if there is an error in the pack header in the meantime,
It can be easily replaced with a teletext pack header. Also, even if there is an error in the data part, the pack is not changed to the "no information pack". This is because the restoration of the teletext data is entrusted to the parity check of the teletext decoder. Therefore, even if it is determined that there is an error, the data is left as it is.

The data processed as described above has
It is assumed that the error flag does not exist. The pack data stored in the memory 173 is read to the P / S conversion circuit 174 and converted into serial data. Then, it is supplied to the S / P conversion circuit 175 of the mode processing microcomputer 117 according to the communication protocol between the microcomputers. The parallel data output from the S / P conversion circuit 175 is supplied to the pack data decomposition analysis circuit 176 and analyzed. Note that the processing in the pack data decomposition analysis circuit 176 is as shown in FIG.
The VAUX pack data generation process shown in FIG. 3 is performed in the reverse order.

The P / S conversion circuit 174 and the S / P conversion circuit 175 are serial I / O in the microcomputer, the pack header identification circuit 171, the switch 172 and the read / write circuit 177 are the software of the microcomputer, and the memory 173 is the internal microcomputer. Memory of each. The processing on the reproducing side of the MIC microcomputer 119 is the same as the processing shown in FIG.
The process is performed in the reverse order of the IC data generation process.

[0114]

According to the present invention, since the number of packs used for one division of the maker's option can be grasped, the read data can be used without waste even when writing many times. Also, since the types of maker's option packs can be increased by layering, it is possible to freely define packs suitable for each application.

[Brief description of drawings]

FIG. 1 is a diagram showing a track format of a tape.

FIG. 2 is a diagram showing a track format of a tape.

FIG. 3 is a diagram showing a track format of a tape.

FIG. 4 is a diagram showing a hierarchical structure of application IDs.

FIG. 5 is a diagram showing a track format of a tape.

FIG. 6 is a diagram showing a structure of a pack.

FIG. 7 is a diagram showing a hierarchical structure of a header.

FIG. 8 is a diagram showing a pack header table.

FIG. 9 is a diagram showing a track format of a tape.

FIG. 10 is a diagram showing configurations of a presync and a postsync.

FIG. 11 is a diagram showing a track format of a tape.

FIG. 12 is a diagram showing a track format of a tape.

FIG. 13 is a diagram showing a track format of a tape.

FIG. 14 is a diagram showing a track format of a tape.

FIG. 15 is a diagram showing a track format of a tape.

FIG. 16 is a diagram showing a track format of a tape.

FIG. 17 is a diagram showing a track format of a tape.

FIG. 18 is a diagram showing details of an ID section.

FIG. 19 is a diagram showing a track format of a tape.

FIG. 20 is a diagram showing a track format of a tape.

FIG. 21 is a diagram showing details of an ID section.

FIG. 22 is a diagram showing a track format of a tape.

FIG. 23 is a diagram showing a data structure of MIC.

FIG. 24 is a diagram showing an extracted pack header table.

FIG. 25 is a diagram showing a maker code pack.

FIG. 26 is a flowchart of a reproduction process regarding a pack when TDP is used.

FIG. 27 is a diagram of a maker code pack when the optional pack has a hierarchical structure.

FIG. 28 is a diagram showing a hierarchical structure.

FIG. 29 is a diagram showing an example of a hierarchical structure.

FIG. 30 is a block diagram of a recording system of a digital VCR.

FIG. 31 is a block diagram of a recording system for VAUX data.

FIG. 32 is a diagram showing a relationship between a main area, an optional area and a sync number.

FIG. 33 is a block diagram of a VAUX pack data generation circuit.

FIG. 34 is a block diagram of an AAUX pack data generation circuit.

FIG. 35 is a block diagram of an MIC processing microcomputer.

FIG. 36 is a block diagram of a reproduction system of a digital VCR.

FIG. 37 is a block diagram of a playback system of a digital VCR.

FIG. 38 is a block diagram of a VAUX circuit.

FIG. 39 is a block diagram of a signal processing microcomputer.

FIG. 40 is a diagram showing a maker code pack.

FIG. 41 is a diagram showing an example of recording a manufacturer code pack.

[Explanation of symbols]

 148 VAUX circuit 163 Pack header detection circuit 165 Memory 166 FIFO

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H04N 5/7826 5/91 8224-5D G11B 27/28 A

Claims (4)

[Claims] 1. An area for recording auxiliary data accompanying images and audio is provided in addition to an area for recording an image signal and an area for recording an audio signal, and a fixed-length pack is provided in the auxiliary data area. In the image signal and audio signal recording method in which the auxiliary data is packed and recorded in the sub-area, the auxiliary data area is divided into a main area and a sub area, and a manufacturer code is recorded in the sub area. An image signal and audio signal recording method characterized in that auxiliary data unique to each manufacturer is recorded after the pack. 2. The pack in which the maker code is recorded has data recorded therein indicating how many packs after the pack in which auxiliary data unique to each maker is recorded continue. Image signal and audio signal recording method. 3. The image signal and audio signal recording method according to claim 1, wherein a product category code of each maker is recorded in the pack in which the maker code is recorded. 4. A fixed-length pack is provided in the auxiliary data area, in addition to the area for recording the image signal and the area for recording the audio signal, an area for recording auxiliary data accompanying the image and sound is provided. In an image signal and audio signal recording / reproducing apparatus in which the auxiliary data is packed and recorded in the auxiliary data area, the auxiliary data area is divided into a main area and a sub area, and a manufacturer code is recorded in the sub area. An image signal and audio signal recording / reproducing apparatus characterized in that auxiliary data unique to each manufacturer is recorded after the pack.