JPH07271926A - Ic card reader/writer - Google Patents

Abstract

PURPOSE:To miniaturize and simplify an IC card reader/writer. CONSTITUTION:The clock produced by a crystal 101 is frequency divided at the inside of a CPU 100 into a system clock theta and a synchronizing clock SCK of different frequencies. When the start-stop communication is carried out to an IC card, a buffer 102 is activated and the clock theta is outputted. Meanwhile a buffer 103 is activated and the clock SCK is outputted when the clock synchronizing communication is carried out to the IC card. The clock produced by a single oscillator is frequency divided for generation of plural clocks of different frequencies. Thereby, the constitution of an IC card reader/writer can be simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card reader / writer, and more particularly to an IC card reader / writer capable of switching between synchronous and asynchronous communication.

[0002]

2. Description of the Related Art In recent years, IC cards equipped with a memory and a microcomputer have begun to be used. The IC card reader / writer reads / writes data from / to this IC card, and includes a communication means for transmitting / receiving data to / from the IC card. Such IC
One of the functions required of the card reader / writer is that it can be applied to various types of IC cards. Although the positions of terminals and the like of IC cards that have been conventionally used are standardized, different types of communication systems are used. For example, there are two types of communication systems used for IC cards: an asynchronous system and a clock synchronous system. Therefore, the IC card reader / writer is required to be able to support at least these communication methods.

Here, FIG. 10 shows an outline of the asynchronous communication and the clock synchronous communication. The asynchronous communication shown in (A) of the figure is also called a so-called asynchronous communication system, and is a system for transmitting and receiving data without using a clock for synchronization. A start bit and a stop bit are added before and after the 8-bit data, and the receiving side reads the data with the start bit and the stop bit as a reference. The clock-synchronous communication system shown in (B) of the figure transmits and receives a synchronization clock together with data. On the receiving side, the data can be correctly received by reading the data at each rising edge of the clock.

Further, even IC cards using a clock-synchronous communication system may have different clock frequencies. Therefore, as disclosed in Japanese Patent Application Laid-Open No. 2-5192 and Japanese Patent Application Laid-Open No. 61-148588, an optimum clock is generated for each IC card using a clock generation circuit having different oscillation frequencies.

[0005]

However, in the conventional IC card reader / writer, it is necessary to prepare a plurality of clock oscillation circuits according to the communication system and clock frequency of the IC card. For this reason, the configuration of the IC card reader / writer becomes complicated, leading to an increase in size and cost of the device.

[0006]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an IC card reader / writer which can realize the miniaturization and simplification of the device.

[0007]

The invention according to claim 1 is
In an IC card reader / writer that transmits and receives data to and from an IC card, an oscillating unit that oscillates a reference clock having a predetermined frequency, a clock generating unit that can generate a plurality of clocks with different frequencies based on the reference clock, and a plurality of clock generating units. Selecting any one of the communication methods, and selecting the clock corresponding to this communication method from the plurality of clocks generated by the clock generating means, and the selecting means respectively. An IC card reader / writer comprising: a transmission / reception means for transmitting / receiving data to / from an IC card based on a communication system and a clock.

According to a second aspect of the present invention, the selecting means comprises:
2. The IC card reader / writer according to claim 1, wherein either an asynchronous communication system or a clock synchronous communication system can be selected.

According to a third aspect of the present invention, there is provided an IC card reader / writer characterized in that the clock generating means according to the first aspect divides a reference clock to generate a plurality of clocks having different frequencies. .

The invention according to claim 4 is characterized in that the selecting means according to claim 1 selects a communication system based on a command from a host terminal connected to the IC card reader / writer via a communication line. IC card reader / writer.

According to a fifth aspect of the present invention, the transmitting and receiving means according to the first aspect performs the initial communication according to the selected communication method by the I communication.
The IC card reader / writer is characterized in that it is performed on a C card.

[0012]

According to the first aspect of the invention, the oscillating means oscillates a reference clock having a predetermined frequency, and the clock generating means generates a plurality of clocks having different frequencies based on the reference clock. For example, the system clock of the CPU can be used as the reference clock. The selecting means selects one of a plurality of different communication methods and selects a clock corresponding to the communication method from the plurality of clocks. The transmission / reception unit transmits / receives data to / from the IC card based on the communication method and the clock selected by the selection unit.

Therefore, according to the present invention, it becomes possible to deal with a plurality of IC cards having different communication systems and different clock frequencies by using only a single oscillator. As a result, the IC card reader / writer device can be simplified and downsized.

According to the second aspect of the invention, the selecting means can select either the asynchronous communication system or the clock synchronous communication system. Therefore, according to the present invention, it is possible to support either the start-stop synchronization type or the clock synchronization type communication system by a single oscillating means.

In the invention of claim 3, the clock generating means of claim 1 divides the reference clock to generate a plurality of clocks of different frequencies. As a result, it is possible to generate a plurality of clocks having different frequencies with a single oscillating means, and it is possible to reduce the size of the IC card reader / writer device.

In the invention according to claim 4, the selecting means according to claim 1 is based on a command from a host terminal connected to the IC card reader / writer through a communication line.
Select the communication method. That is, according to the present invention, it becomes possible to freely select the communication system and the clock frequency using the host terminal.

In the invention described in claim 5, the transmitting and receiving means according to claim 1 performs initial communication with the IC card according to the selected communication method. For example, even if the reception timing of the initialization information of the IC card differs depending on the communication method, the transmitting / receiving means can correctly receive the initialization information.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An IC card reader / writer according to an embodiment of the present invention will be described below with reference to the drawings. Figure 1
It is a schematic circuit diagram of an IC card reader / writer according to the present embodiment. This IC card reader / writer has a CPU 100,
It is composed of a RAM 150, an IC 160 for RS-232C, and the like. The crystal 101 connected to the CPU 100 is for clock oscillation and is 9.8304.
It can oscillate a MHz clock (reference clock). This clock is divided inside the CPU 100, and the system clock φ of 4.9152 MHz is output from the port P57 and the synchronous clock SCK of 50 kHz is output from the port P72.

System clock φ and synchronous clock S
CK is input to the gate 105 via the tristate buffers 102 and 103. Also, the buffer 10
An inverter 104 is connected to 2 and 103, and either of the buffers 102 and 103 can be selectively activated. For example, when the port P10 is at the high level, the buffer 102 is activated and the gate 1
The system clock φ is output from 05. If the port P10 is at low level, the buffer 103
Are activated, and the synchronous clock SCK is output from the gate 105.

The RS-232C IC 160 is for performing data communication with a host terminal (not shown), and its operation is controlled by the CPU 100.

FIG. 2 is a block diagram showing a circuit for generating the system clock φ and the synchronous clock SCK inside the CPU 100. The crystal 101 and the oscillator circuit 110 are for oscillating a clock of 9.8304 MHz. This master clock is divided by frequency divider 1
The frequency is divided into 4.9152 MHz by 11, and the system clock φ is generated. The system clock φ is further divided by the dividing circuit 112 to generate a 50 kHz synchronous clock SCK. The system clock φ and the synchronous clock SCK are the buffers 102, 1 as described above.
It is selectively output to the IC card by 03.

FIG. 3 shows an example of commands of the IC card reader / writer. These commands are transmitted from the host terminal to the IC card reader / writer. That is, the operation of the C card can be controlled by transmitting these commands from the host terminal to the IC card reader / writer. In the figure, the command "C
0 "and" C1 "are for switching the clock corresponding to the asynchronous mode and the clock synchronous mode. Therefore, when the command" C0 "is transmitted from the host terminal to the IC card reader / writer, the IC card reader The writer transits to the asynchronous mode, and the command "C
When 1 "is transmitted, the IC card reader / writer transits to the clock synchronous mode.

Next, the operation of the IC card reader / writer configured as described above will be described.

FIG. 4 is a main flowchart of the IC card reader / writer according to this embodiment. In this flowchart, the CPU 100 first initializes the port (S101). That is, the CPU 100 uses the port P1
0, P11, P12, P14, and P15 are set as output ports, and ports P13 and P16 are set as input ports.
In addition, the CPU 100 uses the ports P10, P11, P1.
"0" (low level) is output to 4, P15, P15,
"1" (high level) is output to the port P12.

Next, the CPU 100 sets the serial communication interfaces SCI and SCI2 (S102). SCI1 is for setting the communication method with the IC card, and SCI2 is RS-232C.
This is for setting the communication method for the IC 160 for use. After the reset process, SCI1 and SCI2 are set to the asynchronous mode and the communication speed is set to 9600 bps. The character format is 8-bit data, even parity, and stop bit is 1. Further, the CPU 100 uses the port P5 for the system clock φ.
7 and the synchronous clock port P72 are set as output ports (S103, S104).

CPU 100 is an IC1 for RS-232C
It is assumed that a command is received from the host computer via 60 (S105). The data communication is performed by CR termination. The CPU 100 processes the received command (S107) and sends a response to the host computer (S106). By repeating this processing (S105 to S107), the IC card reader / writer operates according to the instruction from the host computer.

FIG. 5 is a flowchart showing the clock switching process. The CPU 100 identifies the parameter P1 of the command transmitted from the host computer. The parameter P1 being "0" indicates that the asynchronous communication is performed, and the parameter P1 being "1" indicates that the clock synchronous communication is performed. Therefore, when the parameter P1 does not correspond to any of these (NO in S201), an error response is set (S209) and the process returns to the main flowchart.

When the parameter P1 is "1" (S2
YES in 02) indicates the mode 0 indicating the start-stop synchronization mode.
Is set (S203). Then, the CPU 100 outputs "1" to the port P10 to activate the buffer 102 (S204). As a result, the system clock φ can be output from the port P57. Also, the CPU 10
0 initializes SCI2 (S205) and sets SCI2 to the asynchronous mode.

On the other hand, when the parameter P1 is "0" (NO in S202), mode 1 representing the clock synchronous mode is set (S206). And the CPU 10
0 outputs “0” to the port P10, and the buffer 103
Is activated (S207). This allows port P7
The synchronous clock SCK can be output from 2. Also, C
The PU 100 initializes SCI2 (S208), and then S
Set CI2 to clock synchronous mode. After the above processing, the CPU 100 returns to the main flowchart.

FIG. 6 is a flowchart showing the IC card reset process. First, the CPU 100 determines whether an IC card has been inserted into the IC card reader / writer (S201). If the IC card is not inserted (NO in S201), error setting is performed (S3
09), and returns to the main flowchart. If an IC card is inserted (YES in S301), port P
After setting 12 to "0" and port P11 to "1" (S30
2), "1" is output to the port P12 (S303).
As a result, the reset signal RST is output from the port P12, and the IC card is reset.

Next, the CPU 100 determines whether or not the mode indicating the communication system is "0", that is, whether or not it is the start-stop synchronization mode (S304). When the asynchronous mode is set (YES in S304), the ATR information is received at the timing of the asynchronous communication (S305). On the other hand, when the asynchronous mode is not set, that is, when the clock synchronous mode is set (S30
No in 4), A at the timing of clock synchronous communication
The TR information is received (S306). As shown in FIGS. 8 and 9, the timing of receiving the ATR information differs depending on the IC card. In FIG. 8, I / O (IR) represents the timing of input / output data of the start / stop synchronous reset card, and I / O (AR) represents the timing of input / output data of the start / stop external reset card. I / O (SHR) represents the timing of input / output data of the clock synchronous response card. FIG. 9 is a timing chart when the clock synchronous IC card is reset.

The CPU 100 judges whether or not the received ATR information is normal, and when the ATR information is not normal (S3
The error is set to NO in 07) (S309), and A
If the TR information is normal (YES in S307), a response set is performed (S308). After the above processing,
The CPU 100 returns to the main flowchart.

FIG. 7 shows an IC card reader / writer and I
It is a flow chart showing command processing between C cards. When the CPU 100 does not receive the command from the IC card (NO in S401), after the R / W command processing (S407), the response set for the IC card is performed (S408). When the CPU 100 receives the command from the IC card (YES in S401), the CPU 100 executes the processes of S402 and thereafter.

In S402, the CPU 100 determines whether or not the mode is "0", that is, whether or not the start / stop synchronization mode is set (S402). When the start / stop synchronization mode is set (YES in S402), C
The PU 100 performs transmission / reception in an asynchronous method (S403, S404). On the other hand, when the clock synchronous mode is set (NO in S402), the CPU
100 performs transmission and reception by the clock synchronous method (S405, S406). After the above processing is completed, C
The PU 100 returns to the main flowchart.

The present invention is not limited to the above-mentioned embodiments and can be carried out within the scope of the present invention. For example, in the clock synchronous mode, the clock frequency may be switched according to the IC card.

[0036]

As described above, according to the present invention, by dividing a clock having a frequency corresponding to a communication system, data communication can be performed with respect to various IC cards having different communication systems and clock frequencies. Is going. That is, since a clock generated by a single oscillator circuit is divided to generate a plurality of clocks having different frequencies, it is not necessary to prepare a plurality of oscillator circuits. As a result, the device configuration of the IC card reader / writer can be simplified and downsized.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram of an IC card reader / writer according to an embodiment of the present invention.

FIG. 2 is a block diagram of a clock generation circuit of an IC card reader / writer according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of commands of an IC card reader / writer according to an embodiment of the present invention.

FIG. 4 is a main flowchart of an IC card reader / writer according to an embodiment of the present invention.

FIG. 5 is a flowchart showing a clock switching process of the IC card reader / writer according to the embodiment of the present invention.

FIG. 6 is a flowchart showing a reset process of the IC card reader / writer according to the embodiment of the present invention.

FIG. 7 is a flowchart showing command processing of the IC card reader / writer according to the embodiment of the present invention.

FIG. 8 is a timing chart of an IC card according to an embodiment of the present invention.

FIG. 9 is a timing chart of an IC card according to an embodiment of the present invention.

FIG. 10 is a diagram for explaining asynchronous communication and clock synchronous communication.

[Explanation of symbols]

100 CPU (oscillation means, clock generation means, transmission / reception means) 101 Crystal (oscillation means) 102, 103 Buffer (selection means) 110 Oscillation circuit (oscillation means) 111, 112 Dividing circuit (clock generation means)

Claims (5)

[Claims] 1. An IC card reader / writer that transmits and receives data to and from an IC card, and oscillating means for oscillating a reference clock of a predetermined frequency; and a clock capable of generating a plurality of clocks of different frequencies based on the reference clock. Select a communication method from the generation means and a plurality of communication methods,
Selection means for selecting a clock corresponding to this communication method from a plurality of clocks generated by the clock generation means, and transmission / reception of data to / from the IC card based on the communication method and the clock respectively selected by the selection means. An IC card reader / writer, comprising: a transmission / reception means for performing. 2. The IC card reader / writer according to claim 1, wherein the selecting means is capable of selecting either an asynchronous communication system or a clock communication system. 3. The IC card reader / writer according to claim 1, wherein the clock generating means generates a plurality of clocks having different frequencies by dividing the reference clock. 4. The IC card reader / writer according to claim 1, wherein the selecting means selects a communication method based on a command from a host terminal connected to the IC card reader / writer via a communication line. 5. The IC card reader / writer according to claim 1, wherein the transmitting / receiving means performs initial communication with the IC card according to the selected communication method.