JPH07271574A - Microprocessor - Google Patents

Abstract

PURPOSE:To easily allocate variable data with high access frequency to an internal register and to accelerate an arithmetic processing speed by replacing the contents of an external register with the high access frequency with the contents of the internal register with low access frequency. CONSTITUTION:The content replacing means 14 of an MPU 10 inspects flags stored in first flag registers 13-1, 13-2,... 13-32 and second flag registers 13-33, 13-34,..., 13-64 at each prescribed timing. As the result of inspection, when the internal register whose arithmetic processing speed is fast is not accessed and the external register whose arithmetic processing speed is slow is accessed, the contents of the internal register and the contents of the external register are replaced by the content replacing means 14 and the contents of the external register are processed in the internal register. Thus, the variable data of the access frequency are easily allocated to the internal register and the arithmetic processing speed is accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor (hereinafter abbreviated as "MPU") in which register access is devised.

[0002]

2. Description of the Related Art Generally, when an operation is performed by an MPU, an internal register or an external memory of the MPU is used as a storage place for variable data, such as an operand and an operation result. When an external memory is used as a storage location for variable data, the variable data is read from the external memory into the MPU and the variable data is written from the MPU into the external memory. There is a drawback in that the calculation processing speed when processing is performed using an external memory is slower than the calculation execution speed when processing is performed using the external memory.

Therefore, in order to increase the calculation processing speed of the MPU, a human is used when writing a program in an assemble language, and a compiler is used when writing a program in a high-level language. Deal with assigning to the internal register of.

[0004]

As described above, variable data having a high access frequency is generally assigned to the internal register of the MPU by a human or a compiler program. However, when allocating variable data having a high access frequency to the internal register of the MPU, for example, in the allocation by the register allocation algorithm of the compiler, the access frequency on the listing of the program is evaluated and allocated, so the program is started,
For example, when the same flow is executed many times due to conditional branching, the access frequency changes, and variable data with high access frequency is not necessarily optimally assigned to the internal register of the MPU, and the arithmetic processing speed is not improved. There is a problem.

Further, since the access frequency also changes depending on input data and external interrupt conditions, it is not easy to optimally assign variable data having a high access frequency to the internal register of the MPU, and the arithmetic processing speed can be improved. There is a problem that it is difficult. In view of the above circumstances, it is an object of the present invention to provide an MPU in which arithmetic processing speed is improved by easily allocating variable data having high access frequency to an internal register.

[0006]

Means for Solving the Problems An MPU of the present invention that achieves the above object is a microprocessor that sequentially executes a group of instructions. (1) A plurality of internal registers (2) Corresponding to each of the plurality of internal registers Address register that stores a representative address that represents the address of an external register on the memory area (3) Stores a flag that is provided corresponding to each of the plurality of internal registers and that indicates whether or not the corresponding internal register has been accessed First flag register (4) A second flag register (5) which is provided for each of the plurality of internal registers and which stores a flag indicating whether or not the corresponding external register has been accessed Every time, the flags stored in the first and second flag registers are inspected and correspond to each other. When a flag indicating that the first flag register has not been accessed is stored and a flag indicating that the second flag register has been accessed is stored among the first and second flag registers , A content exchange means for exchanging the content of the corresponding internal register with the content of the corresponding external register (6) The first and second flag registers can be accessed to the internal register and the external register at predetermined timings. Flag clear means for clearing to a flag indicating that there was no such change (7) Inverted every time the contents of the internal register and the external register corresponding to each of the plurality of internal registers corresponding to each other are exchanged. Flag register for storing the flag to be stored (8) The flag stored in the third flag register According to the lag, access replacement means for replacing the access of the corresponding internal register with the access of the corresponding external register is provided.

Here, it is preferable that the operation between the internal register and the external register corresponding to each other is prohibited.

[0008]

With the above arrangement, the MPU of the present invention replaces the contents of the external register with high access frequency with the contents of the internal register with low access frequency. Therefore, for example, in the prior art, variable data with high access frequency is assigned to the internal register easily and optimally without variable data with low access frequency due to conditional branch of program, input data, external interrupt, etc. Assigned. As a result, the contents of the external register, which has a high access frequency and a low calculation processing speed, are calculated by the internal register which has a high calculation processing speed, and the calculation processing speed is improved.

Further, when the operation between the internal register and the external register corresponding to each other is prohibited, both the internal register and the external register are efficiently accessed without being frequently accessed.

[0010]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a schematic diagram of a characteristic portion of an embodiment of the MPU of the present invention and a diagram showing a part of an external memory area. MPU
10 has 32 internal registers 11_1, 11_2,
..., 11_32 are provided.

On the other hand, in the area of the external memory 20, the above-mentioned 3
Two internal registers 11_1, 11_2, ..., 11_3
32 external registers 11_3 corresponding to 2 respectively
3, 11_34, ..., 11_64. Further, the MPU 10 has 32 internal registers 11_1,
11_2, ..., 11_32 corresponding to 32 first flag registers 13_1, 13_2, ..., 13
_32 is provided. When an internal register is accessed, the flag "1" is stored in the first flag register corresponding to the internal register.

Further, the MPU 10 has 32 second flag registers 13_3 corresponding to the 32 external registers 11_33, 11_34, ..., 11_64.
3, 13_34, ... 13_64 are also provided. First
When an external register is accessed, the flag "1" is also stored in the second flag register corresponding to the external register, similarly to the flag register.

Further, the MPU 10 has a content replacement means 1
4 is provided. The content replacing means 14 inspects the flags stored in the first and second flag registers at every predetermined timing. As a result of the inspection, when the flags of the first flag register corresponding to each other are "0" and the flags of the second flag register are "1",
The content exchange means 14 exchanges the content of the corresponding internal register with the content of the corresponding external register.

That is, when the internal register having a high calculation processing speed is not accessed and the external register having a low calculation processing speed is accessed, the content replacement means 1
Since the contents of these internal registers and the contents of the external registers are exchanged by 4, the contents of the external registers are processed by the internal registers. This improves the calculation speed.

Further, the MPU 10 is provided with a flag clearing means 15. The flag clearing means 15 allows the first and second inspections by the content replacing means 14.
The flag register is cleared after a predetermined time has elapsed. As a result, it becomes possible to check whether the internal register or the external register has been accessed by the content replacement means 14 at the next timing.

Further, the MPU 10 includes 32 third flag registers 16_1 and 16 corresponding to the 32 internal registers 11_1, 11_2, ..., 11_32, respectively.
_2, ..., 16_32 are provided. Every time the content exchange means 14 exchanges the content between the internal register and the external register corresponding to each other, the flag of the corresponding third flag register is inverted.

Further, the MPU 10 is also provided with an address register 12 and an access replacing means 17. The address register 12 includes 32 external registers 11_33,
A representative address representative of the addresses of 11_34, ..., 11_64 is stored. When the contents of the internal register are replaced with the contents of the corresponding external register according to the flag of the third flag register described above, the access replacing means 17 responds to the access of the internal register according to the contents of the address register 12. Replace with external register access. On the instruction set of the MPU 10, since it is treated as if the MPU 10 has 64 internal registers, a program is easily created.

Next, as a specific example, the internal register 11_
The process when 1 and the external register 11_33 are exchanged will be described. The address of the external register 11_33 is stored in the address register 12. For example, a timer routine is started by the content replacing means 14 and the first flag register 13_1 and the second flag register 13_33 are inspected at a predetermined timing. Here, it is assumed that the flag of the first flag register 13_1 is "0" and the flag of the second flag register 13_33 is "1". Then, before the timer routine of this time is activated, the internal register 11_1 having a high arithmetic processing speed is not accessed, while the external register 11_33 having a low arithmetic processing speed is accessed, so that the content replacement means 14 , The contents of the internal register 11_1 and the contents of the external register 13_33 are exchanged, and at the same time, the flag of the third flag register 16_1 is '1'.
Flip to.

Here, the first flag register 13_
As the combination of the flags of the first and second flag registers 1333, in addition to the combination described above, when the flags of the first flag register 13_1 and the second flag register 13_33 are both “0” or “1”, or There are three combinations in which the flag of the first flag register 13_1 is "1" and the flag of the second flag register 13_33 is "0". In the case of these combinations, the content replacement means 15
The contents of the internal register 11_1 and the external register 13
Even if the contents of _33 are replaced, the calculation processing speed cannot be expected to be improved, and therefore these contents are not replaced.

After that, the first flag register 13_1 and the second register flag 13_33 are cleared by the flag clear means 15. Further, since the flag of the third flag register 16_1 is "1", the access replacing unit 17 replaces the access of the internal register 11_1 with the access of the external register 11_33.

As described above, the contents of the external register 11_33 are accessed by the internal register 11_1, while the contents of the internal register 11_1 are accessed by the external register 11_33. In this way, variable data with high access frequency is processed by the internal register in the MPU 10,
The calculation processing speed is improved.

[0022]

As described above, the MPU of the present invention.
Checks the flags of the internal register and external register that correspond to each other at every predetermined timing, and if the internal register is not accessed and the external register is accessed, the contents of the external register and the internal register are checked. Register contents are exchanged, and variable data that is frequently accessed is easily assigned to internal registers. For this reason,
The calculation processing speed is improved. Further, it is not necessary to distinguish between the internal register and the external register in the program of the assembler or the compiler, and thus the efficiency of the program can be improved.

[Brief description of drawings]

FIG. 1 is a schematic view of a characteristic part of an embodiment of an MPU of the present invention and a view showing a part of an external memory.

[Explanation of symbols]

10 MPU 11_1, 11_2, ..., 11_32 Internal register 11_33, 11_34, ..., 11_64 External register 12 Address register 13_1, 13_2, ..., 13_32 First flag register 13_33, 13_34, ..., 13_64 Second flag register 14 Exchange means 15 flag clear means 16_1, 16_2, ..., 16_32 third flag register 17 access substitution means 20 external memory

Claims (2)

[Claims] 1. A microprocessor that sequentially executes a group of instructions, and a plurality of internal registers, and an address register that stores a representative address representing an address of an external register on a memory area corresponding to each of the plurality of internal registers. A first flag register that is provided for each of the plurality of internal registers and that stores a flag that indicates whether or not the corresponding internal register has been accessed; and a first flag register that is provided for each of the plurality of internal registers A second flag register that stores a flag indicating whether the corresponding external register has been accessed, and the flag stored in the first and second flag registers is inspected at every predetermined timing. , Of the corresponding first and second flag registers, the first flag register is accessed. When the flag indicating that there is no error is stored and the flag indicating that the second flag register has been accessed is stored, the contents of the corresponding internal register and the contents of the corresponding external register are exchanged. Content replacement means, flag clear means for clearing the first and second flag registers to a flag indicating that the internal register and the external register have not been accessed at predetermined timings, and the plurality of internal A third flag register, which is provided for each register and stores a flag that is inverted each time the contents of the corresponding internal register and external register are exchanged, and the third flag register The corresponding internal register is accessed according to the flag stored in the corresponding external register. Microprocessor, characterized in that it comprises an access replacement means for replacing the process. 2. The microprocessor according to claim 1, wherein operations between internal registers and external registers corresponding to each other are prohibited.