JPH01123328A - Computer system - Google Patents

Abstract

PURPOSE:To attain a high-speed parallel arithmetic by executing a data driving type operation with a processing unit independently of a processing to read a program described in an inverse Polish format and update a using variable table. CONSTITUTION:The data driving type operation is executed with a processing unit 5 independently of the processing to read the program described in the inverse Polish format and update the using variable table 31. Namely, the program described in the inverse Polish notation is read successively, and concerning each variable in the read program, items such as the transfer destination of the value of the variable are written for each variable to be used in an already constructed using variable table 31. Thereafter, the operation is executed to a memory device 1, which is provided corresponding to plural processor units, with a data driving format, in parallel with the writing of a variable operation expression, and a high-speed parallel action is executed.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art and problems to be solved by the invention Means for solving the problems Actions Examples Effects of the invention [Summary] In reverse Polish format Regarding a computer method that reads a written program sequentially and executes it in a data-driven format, the purpose is to execute a program written in a reverse Polish format in parallel in a data-driven manner. a memory that holds data; a main control processor that takes out the program in execution order and inputs it to a slave control processor; and a flag indicating an address, value, and identification number 9 various states for each variable of the input program; A slave control that has a used variable table in the form of an associative memory that holds the destination etc. when transmitting the value of the variable, and writes necessary items in the used variable table every time the program is sequentially read or #. a processor; a storage device having an associative memory function for storing the arithmetic instructions retrieved by the main control processor; and a processing unit that executes the arithmetic instructions when data arrives at the storage device and becomes operable. The processing unit is configured to read the program written in the reverse Polish format and perform data-driven calculations in the processing unit independently of the process of updating the used variable table.

[Industrial application field]

The present invention relates to a computer system that sequentially reads a program written in reverse Polish format and executes it in a data-driven format.

Generally, a program written in a high-level language such as FORTRAN is converted into a tree-structured or reverse-Polish intermediate language program by a compiler, etc., and then converted into a sequential object program. It is executed on a so-called Neumann type computer system.

On the other hand, a data-driven calculation method is known as an efficient parallel calculation method.

If a computer system that can execute programs written in the above-mentioned reverse Polish format etc. in parallel in a data-driven format can be realized, it would be possible to maintain compatibility at the high-level language level that can be used with the conventional Neumann system, and to create a high-speed parallel computer system. We can expect this to come true.

[Prior art and problems to be solved by the invention] FIG. 4 is a diagram illustrating a conventional computer system.

In the Neumann method shown in (a) of this figure, a central processing unit (CPU) executes a program written as a chain of instruction sets specific to each computer system and stored on the main memory (MS). It is executed sequentially.

Therefore, the advantage of this method is the simplicity of communication control between the central processing unit (CPtl) and the main memory (MS) by sequentially executing commands, but if this method is adopted, Even if parallel operation is implemented with some innovation, such as the Vibrine method, it is no longer possible to expect a significant increase in speed beyond the current level.

In addition, a multiprocessor system or an array processor system as shown in figures (bl) and (b2),
Although it attempts to operate a large number of processors at the same time, efficiency is greatly affected by the content of the job, the structure of the program, etc.

In other words, there is a problem in that efficiency cannot be improved unless the program is created with sufficient consideration given to the configuration of the computer.

For this reason, there was a problem in that it was not suitable for general use from an economic standpoint.

On the other hand, in the case of the data flow one-way system, an example of which is shown in figure (c), processing is performed by data flows, and there are nodes (α1, α2, etc.) where different data flows intersect.
Since it is a method of defining and executing operations in ),
Although it is expected that efficient parallel operation will occur automatically without the programmer being aware of the hardware configuration.
Since the program is obtained by defining the nodes of the data flow diagram, it is completely different from the conventional Neumann program, and there is a problem in inheritance of program assets.

Furthermore, in calculations that can only be executed sequentially, it is not only inferior to the Neumann method, but also requires searching for each data (variable) destination one by one, which poses a problem in highly parallel calculations. Ta.

In view of the above conventional drawbacks, the present invention sequentially reads a program written in reverse Polish format, and stores each variable in the used variable table that has already been constructed for each variable in the read program. Writes items such as the destination of the value, and executes data-driven calculations in parallel with writing the arithmetic expression for the variable into the storage device provided corresponding to the plurality of processor units. The aim is to provide a computer system that can perform high-speed parallel operations.

[Means for solving problems]

FIG. 1 is a diagram explaining the operating principle of the computer system of the present invention, and the above-mentioned problems arise when a program is written in reverse Polish format.

A memory 1 that holds data; a main control processor 2 that sequentially retrieves the program and inputs it to the slave control processor 3; and a memory 1 that sequentially retrieves the program and inputs it to the slave control processor 3; A slave control processor 3 has a variable-to-use table 31 in the form of an associative memory that holds destinations for sending variable values, and updates the variable-to-use table 31 so that the program can be executed in a data-driven manner. , a local memory 4 having an associative memory function for storing arithmetic instructions retrieved by the main control program; and means for delegating the execution of the arithmetic operation to the processing unit 5 when the local memory 4 has all the data. The problem can be solved by configuring the processing unit 5 to read the program written in the reverse Polish format and perform data-driven calculations independently of the process of updating the used variable table 31. .

[Effect]

Generally, a computer program expresses a procedure for solving an intended problem, but in the conventional Neumann method, there is no index to distinguish between the arguments (operands) of the operation and the result, so the central Processing equipment (CP
In U), the only way to achieve the above problem solving procedure is to execute the program sequentially, and in terms of architecture, as mentioned above, the speed up of calculations mainly depends on pipelining. There was no.

Therefore, in the computer method according to the present invention, a program written in reverse Polish notation is read out sequentially,
For each variable in the read program, write items such as the destination of the value for each variable used in the used variable table that has already been constructed. In parallel with writing the arithmetic expression of the variable into the storage device, the arithmetic operation is executed in a data-driven format, thereby achieving high-speed parallel operation.

The function and operation of the computer system of the present invention in the arithmetic unit will be explained below.

FIG. 1(b) shows a used variable table 31, which is a memory equipped with an associative memory function.

In the tree usage variable table 31, the rOBJ J column is
The variable address (variable ADR3) on both sides of the assignment statement in the program written in reverse Polish notation read from the memory 1, or the variable with an identification number added thereto, is entered. Hereafter, the “variable ADRS”
and the identification number are collectively referred to as "OBJ No."

The next rVALUE J column contains the calculation results or values obtained by memory access for the variables entered in the rOBJ J column.

The rFj column indicates for each "OBJ" whether it is realized by calculation or memory access.
Whether the result has been entered in the rVALUEJ field,
This flag indicates whether the variable has been stored in memory after the operation, whether the variable has been redefined by a subsequent assignment statement, etc.

The above identification number in the above rOBJ NOJ column is
In the OBJ NOJ column, this is used to distinguish between two variables that have the same address caused by variable redefinition.

The last rDHsTINATION J column contains the above rO
“OBJ No” of the variable generated using the variable in the BJ J column as an argument (operand) is entered.

Programs written in reverse Polish notation are sequentially read out from the memory 1 in FIG. 1(a) by the main control processor 2 and sent to the slave control processor 3.

The slave control processor 3 executes the following write operation on the above-mentioned usage variable table 31.

First, the variable “OBJ No” on the left side of the assignment statement written in reverse Polish notation is sent to the slave control processor 3.
rOBJ J
If found, a variable redefinition flag is set in the "F" column of that line, prohibiting writing in the rDEsTINATION J column, and furthermore, the empty line rOBJ J column is set as "OBJ".
Write “NO”.

At that time, if a variable has been redefined, an identification number is assigned so that the variable before and after the redefinition can be distinguished.

Next, perform the following operations for each variable that appears on the right side of the assignment statement. In other words, the argument "variable ADRS" is set to rOBJ.
j Search with I, and if it is not found, leave a blank line rOBJ J
Write “variable ADR5” corresponding to that argument in the column,
Create the corresponding line.

In the corresponding line, “OBJ” held in the above dedicated register
NO” or the corresponding interleave number, which will be described later, in the rDEsTINATIQNJ column.

Here, a memory fetch is performed for the argument to which the blank line is allocated.

In parallel with the above operation, an arithmetic instruction in reverse Polish format is written in the local instruction memory IJ (LIM).

When the argument arrives at the local instruction memory (LIM) and the operation becomes possible, the operation is delegated to the processing unit (PU), where the operation is executed and the result is used for the above-mentioned use. It is written in the rVALUE J column of the corresponding row of the variable table.

If there is a entry in the rDEsTINATION J column above, the above local instruction memory (
All you have to do is send the data to LIM).

The rDEsTINATION J column has a structure such as a pipeline shown in FIG. 1(b) or an i-stracture memory, and can correspond to a plurality of transmission destinations.

The above variable redefinition flag is rFJ41! , when the transmission of the calculation result is completed; otherwise, the memory storage of the calculation result is finished, and rDEsTI
When the NATION J column becomes empty and a certain period of time has elapsed, the corresponding row of the used variable table 31 is purged and prepared for subsequent calculation instructions.

In the present invention, by the above-described operation, the reading of a program written in reverse Polish notation and the data-driven operation by the processing unit (PU) are executed independently, so it is possible to write the reverse Polish format in the object code. By adopting it, without losing versatility,
Compatibility is maintained at the high-level language level that can be used in the Neumann method, and there is no need to explicitly specify memory access when performing assignment statements, so the load on the compiler is reduced, object programs can be generated efficiently, and data Since driving calculations are performed, there is an effect that high-speed parallel calculations can be performed.

〔Example〕 Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram explaining the operating principle of the computer system of the present invention, in which (a) shows an example of the overall configuration, (b) shows an example of the configuration of the variable table used, and FIG. It is a figure showing an example of the write operation to the usage variable table, (a)
3 shows an example of a reverse Polish format program, (b) shows an example of writing a used variable table, FIG. 3 shows an embodiment of the present invention, and (a) shows an example of the overall configuration. , (b) shows a detailed example of the slave control processor (TEP), and (c) shows a connection example of the slave control processor (TEP) 3'. Main control processor in 2. A slave control processor (TEP) 3.3' including a usage variable table 31, a local instruction memory (
LIM) 4 and processing unit (PLI) 5 are the means necessary to implement the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The computer system of the present invention will be explained below with reference to FIGS. 1 to 3.

First, the basic operation of the computer system of the present invention will be explained with reference to FIG.

In the present invention, a program written in reverse Polish format is stored in memory 1.

Therefore, in this computer method, the program written in the reverse Polish format is read out sequentially in the main control processor 2, and the read instructions are sent to the slave control processor (T
EP) 3, the slave control processor (TEP)
), 3, a write operation is performed on the used variable table 31, the format of which is shown in FIG. 3(b).

That is, as mentioned above, first, the "OBJ No." of the variable on the left side of the assignment statement is held in a dedicated register, and it is searched in the rOBJJ column of the used variable table 31, and if it is found, the rFJ No. of that row is stored. Set the variable redefinition flag in the column, prohibit writing in the rDEsTINATION J column, and write 60BJ NO in the blank rOBJ J column.
”.

At that time, if a variable has been redefined, an identification number is assigned so that the variable before and after the redefinition can be distinguished.

Next, perform the following operations for each variable that appears on the right side of the assignment statement. That is, search for the argument "variable ^ORS" in the rOBJ J column of the used variable table 31, and if it is not found, write "variable ADRS" corresponding to the argument in the blank rOBJ J column to create the corresponding line. .

In the corresponding line, write “OBJ” stored in the dedicated register above.
NO” (i.e. DRS to the variable on the left side of the above assignment statement)
).

Or, rDEST the corresponding interleave number.
Write in INATION J column.

Here, the memory for the argument to which the blank line was allocated is
Perform a memory fetch for 1.

In parallel with the above operation, an arithmetic instruction in reverse Polish format (see FIG. 2(a)) is written in the local instruction memory (LIM) 4.

When the argument arrives at the local instruction memory (LIM) 4 and the operation becomes possible, the operation is delegated to the processing unit (PU) 5.
, the calculation is executed, and the result is written in the rVALUE column of the corresponding row of the used variable table 31.

If there is a entry in the rDEsTINATION J column,
Based on that 'OBJ NO', the above local instruction, memory (
All you have to do is send the data to LIM) 4.

The rDEsTINATION J@ is shown in FIG. 1(b)
It has a structure such as a pipeline shown in , or an i-structure memory, and can correspond to a plurality of transmission destinations.

If the above variable redefinition flag is set in the rFJ column, the transmission of the calculation result is completed; otherwise, the memory storage of the calculation result is completed and the rDEsTIN
When the ATION J column becomes empty and a certain period of time has elapsed, the corresponding row of the used variable table 31 is purged and prepared for subsequent calculation instructions.

The second example of writing to the above used variable table 31 is
As shown in the figure.

Here, (a) shows an example of a program written in reverse Polish format.
When sequentially read from the slave control processor (TEP
) In 3, the write operation to the used variable table 31 is performed in the following procedure.

First, assume that rows corresponding to variables "A" and "C" remain in the used variable table 31 as an initial state.

Here, when the assignment statement is read from the memory 1 and the variable "A" on the left side of the assignment statement arrives at the slave control processor 3, the slave control processor 3 stores this variable as rOBJ J
Search for a, find it in the first line, set the redefinition flag for that line to rFJ 8, and use r DESTINATIO
Writing to NJ 41111 is prohibited, and further,
Write the "variable ADRS" of A' in the rOBJ J column of the blank line, and assign its identification number, for example, '002'.

Next, when the variable °B" on the right side of the above assignment statement arrives, it is also searched for in the rOBJ J column. In this case, it is not found, so °B" is written in the empty line rOBJ J 41j1, and its rDEsTINATTON J In the column, enter the variable °A on the left side.

writes and requests memory access.

Furthermore, when the variable 1cl arrives, the corresponding line is found in the "rOBJ" column, so its rDEsTINATION
” column, simply write the variable IAI on the left side of the assignment statement.

The variables +D1 and 'E' are processed in the same way, and operators such as the four arithmetic operators and the 5 equal sign are skipped.

Writing in the rVALUE J column is the result of the above memory access or operation (i.e., β, δ.

−・−) are written as needed by the associative memory function.

The arithmetic instruction specified by each read program is specified by the “variable ADRS” in the “OBJ
No, except that it is written to the local instruction memory (LIM) 4 at all.

The value of the argument arrives at the local instruction memory (LIM) 4,
When the operation becomes partially possible, the operation is delegated to the processing unit (PU) 5, where the operation is executed, and the result is stored in the local instruction memory (LIM) 4. ．． Furthermore,
rVALUE J in the relevant row of the variable used table 31 above
is written in the field.

rDEsTINATION J 41j! When there is a write to the local instruction memory (LIM), the corresponding local instruction memory (LIM)
) All you have to do is send the data to 4.

The rDEsTINATION J column has a pipeline configuration, as shown in FIG. 1(b), and is shifted by 1° to QBJ No' each time data is transmitted.

If the above variable redefinition flag is set in the rF
When the ATION J column becomes empty and a certain period of time has elapsed, the corresponding row of the used variable table 31 is purged and prepared for subsequent calculation instructions.

In the processing unit (PU) 5, the local instruction memory (LIM) 4 is operated independently of the reading of the program by the main control processor 2 and the write operation to the usage variable table 31 by the slave control processor 3. When the data has been collected, the operation instructed by the local instruction memory (LIM) 4 is executed in a data-driven format, and the operation result is stored in the rVALU of the corresponding row of the used variable table 31.
It is written in the E J column.

In this way, the write operation to the used variable table 31 and the calculation in the processing unit (PU) 5 are executed independently of each other, so that parallel operations can be performed at high speed.

FIG. 3(a) shows a case where the memory 1 is divided into a plurality of banks 11 and used in an interleaved manner. 4. A processing unit (PU) 5 is prepared.

At this time, each used variable table 311 local instruction memo I
J (LIM) 4. Processing unit (PU)
5 is given the divided interleave number.・In this figure, B(0-N)11 is a memory bank, and slave control processor TEP(0-N)
3' corresponds to the memory bank B (0 to N) 11, and there is a one-to-one relationship between the memory bank B (0 to N) 11 and the slave control processor (TEP) (0 to N) 3°. It is connected.

In addition, the slave control processors (TEP) 3' are also connected to each other by a bus, and the figure (C) is an example in which the slave control processors (TEP) (0 to 15) 3' are connected in a ring. .

The slave control processor (TEP) (0 to N) 3'' has several local instruction memories (LIMs) 4, in this example, one having a function of associative memory, in which each arithmetic instruction is stored. Each of the local instruction memories (L4M) 4 described above is exclusively equipped with a plurality of (in this example, one) processing units (PU) 5, which perform arithmetic operations, logical operations, and shift operations. Operations such as the following are executed.

On the local instruction memory (LIM) 4, data corresponding to each variable is transmitted from the slave control processor (TEP) (0 to N) 3', and the data necessary to execute the instruction is stored in an associative memory. The local instruction memory (Lr
M) Execution of the arithmetic instructions stored in the CPU 4 is delegated to the processing unit (PU) 5, and the processing unit (PU) 5 will thereafter independently execute the arithmetic operations.

In the main control processor 2, as shown in the figure,
Program counter (pc), instruction register (INS)
T), general register (G REG) used to store and modify addresses, condition code (CC) where the result of conditional branch judgment is stored, program status word (P!V), etc. It is equipped with a register-related transfer operation, performs sequence control using branch instructions, various controls, and operations on external circuits.
A slave control processor (T
EP) (0 to N) 3, the corresponding slave control processor (TE
P) (0~N) Bus connected to 3° (Fig. 3(c)
)) to broadcast the arithmetic instructions extracted from the program in reverse Polish format.

FIG. 3(b) shows the slave control processor (TEP) (
0 to N) 3”, e.g. slave control process,
(TEP), details (however, each slave control processor (TEP)
) (0~N) Of the connection boats (O~3) between 3",
Processing Unison) (PU)5. and local instruction memory (LI
M) 4 is included, and the variable table 31 used in the slave control processor (TEP) 3' is
The used variable table 31 explained in the figure is stored in memory bank 1.
This was established in response to 1.

The aforementioned port (0) ■, which is used for interfacing with other slave control processors (TEP) (1) 3'', etc., is used for data transmission and reception, and the interface ■ with the main control processor 2 is used for reverse Polish format arithmetic instructions. Broadcasting to all slave control processors (Tll!P) (0 to N) 3°, sending condition codes (CC) for conditional branching from each slave control processor (TEP) (0 to N) 3°, etc. The interface (2) with the memory bank 11 stores data using a variable address (variable ADRS).

The internal operation is the first
Since it is exactly the same as that explained in the figure, it will be omitted here.

Machine language programs in this computer method are written sequentially in almost the same way as in the Neumann method, except that the reverse Polish format is used for parts related to arithmetic expressions such as assignment statements. An example of classification of the instruction set used will be explained below.

(1) Arithmetic instructions: Classified into logical instructions, arithmetic instructions, shift instructions, etc., and written in reverse Polish format.

Further, a vector instruction is written by specifying the start address of a vector element and the vector length.

(II) General instructions: As mentioned above, general instructions are almost the same as the Neumann method,
Written sequentially.

1) Control arithmetic instructions: These are for manipulating control variables, modifying addresses, calculating array addresses, etc., and are formally the same as Neumann arithmetic instructions and transfer instructions including memory access.

2) Arithmetic instruction generation instruction A near address generation instruction is used to construct an arithmetic instruction using an address generated by the main control processor 2.

3) Transfer command: Program counter (PC) in main control processor 2
This is a transfer instruction between registers such as a condition code (CC), and does not include store or load instructions for a memory.

4) Sequence control instructions: branch instructions, concatenation instructions for subroutines, jump instructions, etc.

5) Control commands: System control commands such as stop commands, index commands such as supervisor calls, and input/output commands.

The program classified above and composed of instruction groups stored in the memory 1 is sent to the main control processor 2 by the program counter (PC) of the main control processor 2.
The above general instructions are fetched into the instruction/address register (INST/ADR5) and processed by the main control processor 2, whereas the above calculation instructions are calculation instruction generation instructions classified as general instructions. , including those generated within the master control processor 2, are broadcast to the slave control processor (TEP) 3 and stored in the local instruction memory (LIM).
After the data is stored in the processing unit 1-(PU) 5, when the operands are complete, the processing unit 1-(PU) 5 executes it in a data-driven manner.

In the case of vector instructions, each slave control processor (TEP) 3" provided corresponding to each memory bank If
, the target element contained in the corresponding memory bank 11 is extracted from the start address and vector length of the vector element specified by the vector instruction, and the processing unit (PU) 5 connected to each element is extracted.
Delegate and execute.

As described above, the present invention provides, in a computer system that executes a program written in the reverse Polish format in a data-driven format, for each variable in the program read from memory, its address, identification number, value, and the value of the variable. A flag indicating the status of the variable, the destination to which the variable value is sent (variable ADR5,
A usage variable table that holds interleave numbers (interleave numbers) is configured with a memory that has an associative memory function, and each time a program is read from the memory, the usage and generation relationship between the variables is expressed by writing to the usage variable table, and the usage and generation relationships between the variables are expressed and calculated. Its feature is that it is executed in a data-driven format, independent of the above-mentioned program readout and use variable table write operations.

〔Effect of the invention〕

As explained above in detail, the computer method of the present invention is
A memory that holds programs and data written in reverse Polish format, a main control processor that sequentially retrieves the programs and inputs them to the slave control processor, and a memory that stores addresses, values, and calculations for each variable of the input program. Identification numbers assigned for 9Flags indicating various states,
a slave control processor that has a usage variable table in the form of an associative memory that holds the destination of the value of the variable, etc., and writes necessary items in the usage variable table each time the program is sequentially read; and the main controller. A local instruction memory (LIM) for storing arithmetic instructions retrieved by the processor, and means for delegating the execution of the arithmetic instructions to a processing unit when data is available in the local instruction memory (LIM), Since the program written in the reverse Polish format is read and data-driven calculations are performed in the processing unit independently of the process of updating the variable table used above, the object code is written in the reverse Polish notation. By adopting , compatibility is maintained at the high-level language level that can be used in the Neumann method without losing versatility, and there is no need to explicitly specify memory access when performing assignment statement operations, reducing the burden on the compiler. Object programs can be generated efficiently, and since data-driven calculations are performed, high-speed parallel calculations can be performed.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the operating principle of the computer system of the present invention. FIG. 2 is a diagram showing an example of a write operation to a used variable table. FIG. 3 is a diagram showing an embodiment of the present invention. FIG. 4 is a diagram explaining a conventional computer system. It is. In the drawing, 1 is memory. 11 is a memory bank (B(0) to B(N)). 2 is the main control processor. 3 is a slave control processor (TEP). 3″ is the slave control processor (TEP (1) to (N)) 3
is the variable table used. 4 is a local instruction memory (LIM). 5 is a processing unit (Ptl). pc is a program counter. lN5T/ADRS is an instruction/address register. CC is condition code.

Claims (3)

[Claims] (1) A memory (1) that holds programs written in reverse Polish format and data; a main control processor (2) that sequentially retrieves the programs and inputs them to the slave control processor (3); For each variable in the program, there is a variable table (3
1) in the form of associative memory, and each time the program is read out sequentially, the slave control processor (3) writes the necessary items of the used variable table (31), and the main control processor (2) reads out the necessary items. a storage device (4) for storing calculated calculation instructions; and means for delegating the execution of the calculation instructions to the processing unit (5) when data arrives in the storage device (4) and the calculation becomes possible. The processing unit (5) reads the program written in the reverse Polish format from the memory (1) and performs data-driven calculations independently of the process of updating the used variable table (31). A computer method characterized by performing the following. (2) The above used variable table (31) is stored in the memory (1)
is interleaved corresponding to a plurality of memory banks (11), and for each unit of division, one or more specific number of pairs of the processing unit (5) and the storage device (4) are allocated; A patent claim characterized in that data is exchanged between slave control processors (3') equipped with a used variable table (31), and each processing unit (5) independently performs data-driven calculations. range 1
The computer method described in Section. (3) In the computer system described in item (2) above, a vector instruction is expressed by specifying the start address of vector element data and the vector length, and this is expressed in the divided usage variable table (31). The vector instruction is broadcast to the group of slave control processors (3') comprising a plurality of sub-control processors (3'), and executes the vector instruction in parallel for each element data corresponding to each interleaved memory bank (11). The computer method described in Scope 2.