JP3341662B2 - Information processing device and multi-port register file - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an information processing apparatus having a plurality of functional units and a multi-port register file used in such an information processing apparatus.

[0002]

2. Description of the Related Art In recent years, the performance of microprocessors has been improved by parallel processing such as superscalar technology. An information processing apparatus to which this superscalar technology is applied executes a plurality of instructions in parallel by a plurality of functional units, and uses a multi-port register file for data transfer between the plurality of functional units. Have been.

FIG. 13 is a diagram showing a first example of such a conventional information processing apparatus. In this information processing apparatus, when the decoder 105 activates the word line 106 and turns on the transistor 114, data in the memory cell 102 of the multi-port register file 101 is read out to the functional unit 103 via the bit line 110. . When the decoder 105 activates the word line 107 to turn on the transistor 115, data in the memory cell 102 is read out to the functional unit 104 via the bit line 111. When the decoder 105 activates the word line 108 to turn on the transistor 116, the functional unit 1
From 03, data is written to the memory cell 102 via the bit line 112. When the decoder 105 activates the word line 109 to turn on the transistor 117, the functional unit 104 causes the bit line 11
3, data is written to the memory cell 102.
That is, the multi-port register file 101 used in this information processing apparatus has two read ports and two write ports.

FIG. 14 is a diagram showing a second example of a conventional information processing apparatus. A plurality of memory cell blocks 20 are stored in the multi-port register file 201 of this information processing apparatus.
2, 203 are provided, and the word lines 216, 219 are simultaneously activated by the decoders 206, 207 to turn on the transistors 222, 225. As a result, data is written from the functional unit 208 to both the memory cells 204 and 205 via the bit lines 210 and 213. Similarly, word lines 217, 220 are simultaneously activated by decoders 206, 207, turning on transistors 223, 226. As a result, data is written from the functional unit 209 to both the memory cells 204 and 205 via the bit lines 211 and 214. On the other hand, when the functional unit 208 reads data, the word line 218 is activated by the decoder 206, and the transistor 2
24. Data in the memory cell 204 is read out to the functional unit 208 via the bit line 212. Further, when the functional unit 209 reads data, the word line 221 is activated by the decoder 207, and the memory cell 20 is transferred to the functional unit 209 via the transistor 227 and the bit line 215 which are turned on.
The data in 5 is read. That is, this multi-port register file 201 enables parallel processing by the functional units 208 and 209 by providing two memory cells even with one read port.

FIG. 15 is a diagram showing a third example of a conventional information processing apparatus. In this information processing apparatus, an integer operation register file 301 and a floating point operation register file 302 are provided. The integer operation unit (IU) 303 can read data from the integer operation register file 301 via the read ports 305 and 306 and write the operation result to the integer operation register file 301 via the write port 309. Also, a floating point arithmetic unit (FPU) 302
Reads data from the floating-point operation register file 302 through the read ports 307 and 308,
The operation result can be written to the floating-point operation register file 302 via the write port 310.

[0006]

However, in the first conventional example, the multiport register file 101 requires at least the same number of read ports and write ports as the number of functional units 103 and 104. The word lines 106 to 109 and the bit lines 110 to 113 correspond to the read port and the write port, respectively.
And transistors 114 to 117 must be provided. Therefore, there is a problem that the area of the multi-port register file 101 becomes large.

In the second conventional example, a plurality of memory cells 204 and 205 are used to write the same data.
And a write port 210 to each memory cell,
211, 213, 214 had to be provided.
For this reason, there has been a problem that the area of the entire multi-port register file 201 increases and the power consumption increases.

In the third conventional example, the floating-point operation unit 304 includes the integer operation register file 3.
01 to use the data stored in the floating-point operation register file 302 from the integer operation register file 301 via the data line 311.
There was a problem that data had to be read out. Similarly, in order for the integer operation unit 303 to use the data stored in the floating point operation register file 302, first, the integer operation register file 302 is transferred from the floating point operation register file 302 via the data line 311. There was a problem that data had to be read out to 301. These problems have the disadvantage of increasing the number of ports in the register file.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional example, and an information processing apparatus having a reduced area of a multi-port register file used for data exchange between a plurality of functional units. , And such a multi-port register file.

[0010]

To achieve the above object, an information processing apparatus according to a first aspect of the present invention comprises a decoder capable of decoding a plurality of instructions at the same time;
A plurality of functional units capable of simultaneously executing a plurality of instructions simultaneously decoded by the decoder; and a plurality of memory cell blocks each including at least one memory cell, and written in the memory cells. A plurality of read ports for reading the read data to each of the plurality of functional units are provided corresponding to each of the plurality of functional units for each of the plurality of memory cell blocks, and write data to the memory cells. And a multi-port register file provided corresponding to a part of the plurality of functional units for each of the memory cell blocks.

That is, in the above information processing apparatus, each of the plurality of functional units is provided in a part of the plurality of memory blocks via a write port provided corresponding to the functional unit. Data can be written into the memory cells of

In the above information processing apparatus, even if the memory cell blocks to which data can be written in each of the plurality of functional units are limited, reading can be performed from an arbitrary memory cell block. Even if not connected to all of the memory cell blocks of the multiport register file, parallel processing by the plurality of functional units becomes possible. Therefore, the number of write ports provided in the multi-port register file can be reduced, and there is no need to provide a plurality of memory cells for writing the same data in the multi-port register file. Therefore, the area of the entire multi-port register file can be reduced.

In the above information processing apparatus, it is determined by software which of the plurality of instructions uses which memory cell in the plurality of memory cell blocks and which of the plurality of functional units executes. It may be a thing.

The software for determining which of the plurality of instructions uses which memory cell in each of the plurality of memory cell blocks and which of the plurality of functional units is used is, for example, a compiler. Or a dedicated software.

In this case, the information processing apparatus changes a memory cell to be used determined by the software at the time of execution of the instruction, and changes the instruction determined by the software according to the change of the memory cell block. The information processing apparatus may further include changing means for changing a functional unit to be executed.

To achieve the above object, a multi-port register file according to a second aspect of the present invention comprises at least
Multiple memory cell blocks consisting of one memory cell
Number and multiple read and write ports
In the multi-port register file that, the read port
A plurality of functional units are provided for each memory cell block.
The write port is provided corresponding to all
Part of a plurality of functional units for each of the memory cell blocks
It is characterized in that it is provided corresponding to . The note
All the memory cells in the recell block are
Via the write port or the write port
It may be connected to a unit .

[0017]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment] FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to this embodiment. As shown, the information processing apparatus includes an instruction cache 11, a prefetch buffer 12, a decoder 1
3, the multi-port register file 14, the functional unit A15, the functional unit B16, and the data cache 1
7 is comprised.

The instruction cache 11 is a cache memory used to store instructions. The instructions stored in the instruction cache 11 are the respective instructions of the assembler program compiled by the compiler. Each instruction is determined so as to be operated by a functional unit having a write port connected to a register to which an operation result is written by designating the register at the time of compilation. This instruction specifies three registers as described later.

The prefetch buffer 12 is a buffer in which an instruction fetched from the instruction cache 11 via the instruction data line 21 by a data fetching mechanism (not shown) is temporarily stored. The data fetching mechanism can simultaneously fetch a plurality of instructions from the instruction cache, and the prefetch buffer 12 stores these simultaneously fetched instructions.

The decoder 13 simultaneously decodes a plurality of instructions in the instruction sequence stored in the prefetch buffer 12 via the instruction data line 22. The decoder 13
According to the decoding result, a control signal is sent to the memory cell blocks 18 and 19 of the multi-port register file 14 via signal lines 23 and 24. Thereby, reading and writing of data from the functional units A15 and B16 to the registers are performed. The decoder 13 performs an operation indicated by an instruction code using a register designated to one of the functional unit A15 and the functional unit B16 according to distribution information of a functional unit described later stored in the instruction cache 11 corresponding to the decoded instruction. Is executed.

The multiport register file 14 has two memory cell blocks 18 and 19. Each of the memory cell blocks 18 and 19 has three registers each including memory cells having the number of bits of one word. Each of the 18 registers of the memory cell block includes a read port 31 connected to the functional unit A15,
Read port 3 connected to functional unit B16
2 and a write port 35 connected to the functional unit A15. Memory cell block 19
Are connected to a read port 33 connected to the functional unit A15, a read port 34 connected to the functional unit B16, and a write port 36 connected to the functional unit B16.
In addition, data stored in the data cache 17 can be written to each register in the multi-port memory register via the data line 27.

Function unit A15 and function unit B1
Reference numeral 6 denotes a fixed-point arithmetic unit or a floating-point arithmetic unit, and according to the control result of the decoder 13, the memory cell block 1 designated as described above.
The operation indicated by the instruction code is executed using the registers in 8 and 19. That is, the multi-port register file 14
Performs the processing indicated by the instruction code on the data read from the registers in the memory cell blocks 18 and 19, and writes the processing result data to the register specified by the operand section. In this embodiment, the functional unit A15 and the functional unit B15 have the same function, and can perform parallel processing. Whether the operation is performed by the functional unit A15 or the functional unit B16 is determined at a compilation stage according to a register assigned to a variable of the program as described later, and is written in the instruction cache 11 together with each instruction. I have.

The functions of the multi-port register file 14, the functional units A15 and B16 will be described in more detail with reference to FIG. As shown in FIG. 2, the memory cell block 18 of the multi-port register file 14 includes three registers R1 to R3. The memory cell block 19 has three registers R4
To R6.

When the instruction decoded by the decoder 13 is to be executed by the functional unit A15, the registers R1 to R3 in the memory cell block 18
Is read out to the functional unit A15 via the readout port 31. The data stored in the registers R4 to R6 in the memory cell block 19 is transferred to the functional unit A15 via the read port 33.
Is read out. The operation result by the functional unit A15 is transmitted to the memory cell block 1 via the write port 35.
8 are written to the registers R1 to R3.

When the instruction decoded by the decoder 13 is to be executed by the functional unit B16, the registers R4 to R6 in the memory cell block 19
Is read out to the functional unit B16 via the readout port 32. Data stored in the registers R4 to R6 in the memory cell block 19 is transmitted to the functional unit B16 via the read port 34.
Is read out. The operation result by the functional unit B16 is transmitted to the memory cell block 1 via the write port 36.
9 are written to the registers R4 to R6.

That is, the functional unit A15 and the functional unit B16 can read data from the registers included in both the memory cell blocks 18 and 19. On the other hand, the operation result of the functional unit A15 can be written only to the register included in the memory cell block 18. The operation result of the operation unit B16 can be written only to the register included in the memory cell block 19.

Returning to FIG. 1, the data cache 17 is a cache memory used to store data other than instructions. When the instruction executed by the functional unit A15 or the functional unit B16 is a STORE instruction, the operation result is stored in the functional unit data cache 1
7 is also written. In this case, writing to the main storage device (not shown) may be performed by either a write-through method or a write-back method.

The operation of the information processing apparatus according to this embodiment will be described below. Here, it is assumed that this information processing apparatus executes the processing shown in Expression 1.

## EQU1 ## c ← a + be e ← c + d f ← cd

In this embodiment, when compiling a source program for executing the above processing into an assembler program, the compiler performs the following operations as shown in Table 1.
The multiport register file 1 is stored in the variables a to f during the above processing.
4 are assigned to registers R1 to R6.

[Table 1]

Table 2 shows the assembler program compiled by the compiler. The functional units for processing each instruction step are assigned by the compiler as shown in Table 2. These are stored in the instruction cache 11 (however, the instruction address indicates only the last two digits of hexadecimal, and the instruction is stored from address 0x00).

[Table 2]

When the execution of the instructions shown in Table 2 is started as described later, the values of the variables a, b, and d are assumed to be stored in the registers R1, R4, and R6 assigned to them. I do.

The data reading mechanism of the prefetch buffer 12 is configured such that the instruction cache 1
1 are sequentially read out, and a plurality of instructions are stored in the prefetch buffer 12.

Next, the decoder 13 reads out and decodes a plurality of instructions stored in the prefetch buffer 12. Here, since the instruction from address 0x04 uses the execution result of the instruction from address 0x00, it cannot be executed simultaneously with the instruction from address 0x00, but the instruction from address 0x08 is
Since the result of the instruction from the CPU is not used, the execution is performed simultaneously using both the functional unit A15 and the functional unit B.

Hereinafter, execution of the instruction sequence shown in Table 2 in this information processing apparatus will be described with reference to FIGS.

First, the instruction from the address 0x00 is executed by the functional unit A15. The functional unit A15 is
As shown in FIG. 3, the data in the register R1 is read through the read port 31. Also, the read port 33
, The data of the register R4 is read out. Then, the data of the register R1 and the data of the register R4 are added, and the addition result is written to the register R3 via the write port 35.

Next, the execution of the instruction from the address 0x04 by the functional unit B16 and the execution of the instruction from the address 0x08 by the functional unit A15 are performed simultaneously. The functional unit B16 reads the data of the register R3 via the read port 32, as shown in FIG. Further, the data of the register R6 is read through the read port 34. Then, the data of the register R3 and the data of the register R6 are added, and the addition result is written to the register R5 via the write port 36.

On the other hand, the functional unit A15 reads data from the register R3 through the read port 31, as shown in FIG. Further, the data in the register R6 is read through the read port 33. And register R3
Is subtracted from the data of the register R6, and the result of the addition is written to the register R2 via the write port 35. That is, the instruction from the address 0x04 and the instruction from the address 0x08 correspond to the read ports 31 to 34.
Alternatively, the contention between the write ports 35 and 36 does not occur, and it is possible to execute them simultaneously.

As described above, the multi-port register memory 1 provided in the information processing apparatus of this embodiment
In No. 4, only one write port corresponding to each of the memory cell blocks 18 and 19 can be provided, and there is no need to provide a number corresponding to the number of functional units. Also,
There is no need to provide a plurality of memory cells for writing the same data. Therefore, multi-port register file 1
4 can be reduced in overall area.

Further, in the information processing apparatus of this embodiment, as described above, without conflict between the read ports 31 to 34 or the write ports 35 and 36,
The parallel operation of the functional unit A15 and the functional unit B16 becomes possible.

[Second Embodiment] An information processing apparatus according to the second embodiment is that of the first embodiment (FIG. 1).
Is almost the same as However, in this embodiment,
Function of Function Unit A15 and Function Unit B16
Is different from the function provided by the function unit A15.
The functional unit B16 executes the “SUB” instruction, and the functional unit that processes the operation of each instruction is determined at compile time by the type of the instruction. The assignment is determined by what the functional unit that performed the operation writes the result.

Hereinafter, the operation of the information processing apparatus according to this embodiment will be described. In this embodiment, the processing performed by the information processing apparatus is represented by the same equation 1 as in the first embodiment.

In this embodiment, when compiling a source program for executing the above-mentioned processing into an assembler program, as shown in Table 3, the compiler
The multiport register file 1 is stored in the variables a to f during the above processing.
4 are assigned to registers R1 to R6.

[Table 3]

Table 4 shows the assembler program compiled by the compiler. The functional units for processing each instruction step are assigned by the compiler as shown in Table 4. These are stored in the instruction cache 11 (however, the instruction address indicates only the last two digits of hexadecimal, and the instruction is stored from address 0x00).

[Table 4]

When the execution of the instructions shown in Table 4 is started as described later, the values of the variables a, b, and d are assumed to be stored in the registers R1, R4, and R5 assigned to them. I do.

In this embodiment, the operations from the retrieval of the instruction stored in the instruction cache 11 to the decoding of the instruction by the decoder 13 are the same as those in the first embodiment. Here, since the instruction from address 0x04 uses the execution result of the instruction from address 0x00, it cannot be executed simultaneously with the instruction from address 0x00, but the instruction from address 0x08 is
Since the result of the instruction from the instruction unit 04 is not used and the functional units to be executed are different, the functional units A15 and B are executed at the same time.

Hereinafter, the execution of the instruction sequence shown in Table 2 in this information processing apparatus will be described with reference to FIGS.

First, the instruction from the address 0x00 is executed by the functional unit A15. The functional unit A15 is
As shown in FIG. 6, the data in the register R1 is read through the read port 31. Also, the read port 33
, The data of the register R4 is read out. Then, the data of the register R1 and the data of the register R4 are added, and the addition result is written to the register R3 via the write port 35.

Next, the execution of the instruction from the address 0x04 by the functional unit A15 and the execution of the instruction from the address 0x08 by the functional unit B16 are performed simultaneously. The functional unit A15 reads the data of the register R3 via the read port 31, as shown in FIG. Further, the data of the register R5 is read through the read port 33. Then, the data of the register R3 and the data of the register R5 are added, and the addition result is written to the register R2 via the write port 35.

On the other hand, as shown in FIG. 5, the functional unit B16 reads data from the register R3 through the read port 32. Further, the data in the register R5 is read through the read port 34. And register R3
Is subtracted from the data of the register R5, and the result of the subtraction is written to the register R6 via the write port 36. That is, the instruction from the address 0x04 and the instruction from the address 0x08 correspond to the read ports 31 to 34.
Alternatively, the contention between the write ports 35 and 36 does not occur, and it is possible to execute them simultaneously.

As described above, in the information processing apparatus of this embodiment, the functional unit A15 and the functional unit B
16, the read ports 31 to 34
Alternatively, the parallel operation of the functional unit A15 and the functional unit B16 can be performed without contention between the write ports 35 and 36. Therefore, for example, when performing the integer operation and the floating-point operation using different functional units, it is not necessary to provide a register file unique to each functional unit.

[Third Embodiment] FIG. 9 is a block diagram showing a configuration of an information processing apparatus according to the third embodiment. As shown, the information processing apparatus includes an instruction cache 11, a prefetch buffer 12, a decoder 1
3, a renaming mechanism 41, a multi-port register file 42, a functional unit A15, and a functional unit B1.
6 is comprised.

In this information processing apparatus, the configuration of the instruction cache 11, prefetch buffer 12, decoder 13, functional unit A15 and functional unit B16 is the same as that of the first embodiment (FIG. 1). Also, the multi-port file register 42 and the memory cell blocks 43 and 44 included in the multi-port register file 42
Are the same as those in the compiled assembler program except that the logical registers R1 to R6 are accessed as physical registers r1 to r6 converted by the renaming mechanism 41 as described later. It is the same as that of the form.

As will be described later, the renaming mechanism 41 designates the registers assigned to each variable at the time of compilation as logical registers R1 to R6, and for each logical register R1 to R6, the memory cell block 43 of the multiport register file 42. , 44 provided in the physical register r1
To r6. Here, the physical registers r1 to r3
Are provided in the memory cell block 43, and the physical registers r4 to r6 are provided in the memory cell block 44.

Hereinafter, the operation of the information processing apparatus according to this embodiment will be described. In this embodiment, the processing performed by the information processing apparatus is represented by the same equation 1 as in the first embodiment.

In this embodiment, when compiling a source program for executing the above processing into an assembler program, the compiler executes
The multiport register file 1 is stored in the variables a to f during the above processing.
4 logical registers R1 to R6. Further, the renaming mechanism 41 determines whether the assigned logical register R1
, The physical registers r1 to r6 as shown in Table 5.
Assign r6.

[Table 5]

Table 6 shows the assembler program compiled by the compiler. The functional units for processing the respective instruction steps are allocated by the compiler as shown in Table 6 according to the assignment of the logical registers R1 to R6. These are stored in the instruction cache 11 (however, the instruction address indicates only the last two digits of hexadecimal, and the instruction is stored from address 0x00).

[Table 6]

However, in this embodiment, the physical registers r1 to r1 are
Table 6 shows the program to which r6 is assigned and the allocation of functional units at each instruction step and the program to be actually executed.

[Table 7]

When the execution of the instructions shown in Table 6 is started as described later, the values of the variables a, b and d are set to the logical registers R1, R2 and R assigned to them.
Physical registers r1, r4, and r assigned to
3 is stored.

In this embodiment, the operation from the retrieval of the instruction stored in the instruction cache 11 to the decoding of the instruction by the decoder 13 is the same as that in the first embodiment. Here, as shown in Table 6, the decoding result by the decoder 13 indicates the instruction from the address 0x00, the instruction from the address 0x04, and the address 0x08.
Are executed by the functional unit B16, so that parallel processing cannot be performed.

Therefore, the rename mechanism 41 uses the registers allocated in the instruction as logical registers, and allocates the physical registers r1 to r6 to the logical registers R1 to R6 as shown in Table 5. Then, this information processing apparatus is substantially executing the commands shown in Table 7.

Hereinafter, execution of the instruction sequence shown in Table 7 in this information processing apparatus will be described with reference to FIGS.

First, the instruction from the address 0x00 is executed by the functional unit B16. The functional unit B16 is
As shown in FIG. 10, data of the physical register r1 (logical register R1) is read through the read port 52. Also, the physical register r via the read port 54
4 (logical register R2). And
The data of the physical register r1 and the data of the physical register r4 are added, and the addition result is written to the physical register r5 (logical register R4) via the write port 56.

Next, the execution of the instruction from the address 0x04 by the functional unit A15 and the execution of the instruction from the address 0x08 by the functional unit B16 are performed simultaneously. The functional unit A15 reads the data of the physical register r3 (logical register R3) via the read port 51 as shown in FIG. Further, the data of the physical register r5 (logical register R4) is read through the read port 53. Then, the data of the physical register r3 and the data of the physical register r5 are added, and the addition result is written to the physical register r2 (logical register R6) via the write port 55.

On the other hand, as shown in FIG. 12, the functional unit B16 sends the physical register r through the read port 52.
3 (logical register R3). Further, the data of the physical register r5 (logical register R4) is read through the read port 54. Then, the data of the physical register r3 is subtracted from the data of the physical register r5,
The result of the subtraction is written to the physical register r6 (logical register R5) via the write port 56.

That is, the instruction from address 0x04 and the instruction from address 0x08 cannot be executed at the same time if the logical registers shown in Table 6 are directly used as physical registers. By allocating the specific physical registers r1 to r6 to the logical registers R1 to R6, it is possible to execute the physical registers r1 to r6 at the same time without conflict between the read ports 51 to 54 or the write ports 55 and 56.

As described above, in the information processing apparatus of this embodiment, the parallel processing of the functional unit A15 and the functional unit B16 cannot be performed without the assignment of the logical registers R1 to R6 determined at the time of compiling. However, when the rename mechanism 41 assigns the physical registers r1 to r6 to the logical registers R1 to R6, parallel processing of the functional unit A15 and the functional unit B16 becomes possible.

[Modification of Embodiment] In the above-described first to third embodiments, whether the arithmetic processing for each instruction should be performed by the functional unit A15 or the functional unit B16 is determined at the compilation stage. The instruction has been written in the instruction cache 11 together with the instruction. However,
The distribution between the functional unit A15 and the functional unit B16 may be determined by the decoder 13 according to the instruction code in the instruction or the designated register.

In the first to third embodiments, the compiler allocates registers to each instruction and determines the functional unit to be executed when compiling a source program into an assembler program. However, the determination of the functional unit that should execute each instruction may be performed by compiling a source program into an assembler program and then using dedicated software separate from the compiler.

In the above-described first to third embodiments, the instruction from address 0x04 uses the execution result of the instruction from address 0x00 decoded at the same time, and is therefore executed sequentially. However, if the instructions to be decoded at the same time do not use the processing results of the other, the decoder 13
Control may be performed so that the functional units A15 and B16 simultaneously execute a plurality of decoded instructions within a range in which no collision occurs between the write unit 34 and the write ports 35 and 36.

In the above-described first to third embodiments, the case where the present invention is applied to an information processing apparatus provided with two functional units, a functional unit A15 and a functional unit B16, which performs processing in parallel. explained. However, the information processing apparatus of the present invention can have two or more arbitrary number of functional units. In this case, the content of each register (memory cell) in the multi-port register memory provided in the information processing device is connected to the same number of read ports as the number of functional units, and is smaller than the number of read ports (preferably Can be connected to one) write port.

In the information processing apparatuses according to the first to third embodiments, one instruction is composed of four words. In contrast, the present invention provides VLIW (Very Long
The present invention can be applied to an information processing device of the Instruction Word) type. In this case, the distribution of the functional units is performed by a plurality of fields included in the instruction.

[0073]

As described above, according to the present invention,
Even if a plurality of functional units are not connected to each memory cell block of the multi-port register file, parallel processing can be performed by the plurality of functional units. Therefore, the number of write ports provided in the multi-port register file can be reduced, and there is no need to provide a plurality of memory cells for writing the same data. Therefore, the area of the multi-port register file can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a connection between a multi-port register file and a functional unit in the information processing apparatus of FIG. 1;

FIG. 3 is a diagram illustrating an operation according to the first exemplary embodiment of the present invention.

FIG. 4 is a diagram illustrating an operation according to the first exemplary embodiment of the present invention.

FIG. 5 is a diagram illustrating an operation according to the first exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating an operation according to the second exemplary embodiment of the present invention.

FIG. 7 is a diagram illustrating an operation according to the second exemplary embodiment of the present invention.

FIG. 8 is a diagram illustrating an operation according to the second embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of an information processing apparatus according to a third embodiment of the present invention.

FIG. 10 is a diagram illustrating an operation according to the third embodiment of the present invention.

FIG. 11 is a diagram illustrating an operation according to the third embodiment of the present invention.

FIG. 12 is a diagram illustrating an operation according to the third embodiment of the present invention.

FIG. 13 is a diagram showing a configuration of a conventional information processing apparatus.

FIG. 14 is a diagram illustrating a configuration of a conventional information processing apparatus.

FIG. 15 is a diagram showing a configuration of a conventional device in which an integer operation register file and a floating point operation register file are separated.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Instruction cache 12 Prefetch buffer 13 Decoder 14 Multi-port register file 15 Functional unit A 16 Functional unit B 17 Data cache 18, 19 Memory cell block 21, 22 Instruction data line 23, 24 Signal line 25-27 Data line 31-34 Reading Port 35, 36 Write port 41 Renaming mechanism 42 Multi-port register file 43, 44 Memory cell block 51-54 Read port 55, 56 Write port

Claims (6)

(57) [Claims] 1. A decoder capable of simultaneously decoding a plurality of instructions, a plurality of functional units capable of simultaneously executing a plurality of instructions simultaneously decoded by the decoder, and at least one memory each A plurality of memory cell blocks composed of cells, a plurality of read ports for reading data written in the memory cells to each of the plurality of functional units, and a plurality of read ports for each of the plurality of memory cell blocks; A plurality of write ports provided corresponding to each of the functional units, and a plurality of write ports for writing data to the memory cells are provided corresponding to some of the plurality of functional units for each memory cell block. An information processing apparatus comprising: a register file. 2. A method according to claim 1, wherein each of the plurality of functional units stores data in a memory cell in a part of the plurality of memory blocks via a write port provided corresponding to the functional unit. The information processing apparatus according to claim 1, wherein the information can be written. 3. The method according to claim 1, wherein the plurality of instructions use software cells to determine which memory cell in the plurality of memory cell blocks is to be used and which of the plurality of functional units is to be executed. The information processing apparatus according to claim 1, wherein 4. A memory cell to be used determined by the software is changed at the time of execution of an instruction, and a functional unit to execute the instruction determined by the software is changed according to the change of the memory cell block. The information processing apparatus according to claim 3, further comprising a change unit that performs the change. 5. A semiconductor device comprising at least one memory cell.
Has multiple memory cell blocks, read port and write
In a multi-port register file having a plurality of write ports , the read port is provided for each memory cell block.
The write port is provided corresponding to all the functional units , and the write port is provided for each of the memory cell blocks.
A multi-port register file provided corresponding to some of the number of functional units . 6. All notes in the memory cell block
The recell is connected to the read port or the write port.
Connected to the functional unit via That
The multi-port register file according to claim 5, wherein
Le.