JPH0726843Y2 - Semiconductor element isolation structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an element isolation structure of a semiconductor device such as a semiconductor memory device.

<Prior Art> Element isolation in a conventional semiconductor device has been formed by a LOCOS method in which a thick oxide film is locally formed on a semiconductor substrate using a silicon nitride film as a mask.

<Problems to be solved by the invention> In the above-mentioned conventional substrate structure using the Locos method, bird's beaks occur and the element isolation width shifts and becomes large, making it unusable for highly integrated devices. There is.
After that, an Othello method was developed to reduce the bird's beak to suppress the shift, but the process is complicated and the variation is large due to the use of dry etching. Further, a method of digging a groove and a method of filling a hole are being developed, but since an etching method by dry etching is used, there is a large variation and it is difficult to flatten the surface. Further, in the conventional technique, the film loss is a big problem because the surface is exposed to various conditions due to the increase in the number of processes accompanying the high integration. The present invention has been made in view of the above problems of the conventional structure.

<Means for solving the problem> In the present invention, the separation width is eliminated by trench-type separation, and the variation is reduced by flattening by thermal oxidation, and the upper part of the separation trench is covered with a silicon nitride film. The structure prevents the film loss due to hydrofluoric acid or the like.

<Operation> Since the element isolation is performed by the trench digging structure, the area required for the isolation can be reduced and the density can be increased.

<Embodiment> FIG. 1 shows an embodiment according to the present invention, in which a groove 2 formed by etching the substrate 1 is formed in a silicon semiconductor substrate 1 in order to separate adjacent elements. Impurities such as boron are formed as a field dope layer 3 on the peripheral wall of the substrate, if necessary. The inner wall of the groove 2 is covered with an oxide film 4 and a silicon nitride film 5, and the inside of the groove covered with the silicon nitride film 5 is filled with an oxide 6 obtained by oxidizing polysilicon. The upper portion of the oxide 6 is filled with polysilicon so that its height is almost the same as the surface of the substrate covered with the oxide film 8, and the upper portion of the groove thus filled is covered with the silicon nitride film 9. .

Next, the manufacturing process of the element isolation structure will be described with reference to FIGS.

After a silicon oxide film 8 of 300 Å is formed on a silicon substrate 1, a groove 2 having a depth of 3000 Å is formed by anisotropic etching as a photoresist mask.

Next, by oblique ion implantation of boron into the groove, 1 × 10 ¹⁶ / cm
^After the P ⁻ layer ^{3 of} about 3 is formed, the silicon oxide film 8 is removed by using hydrofluoric acid, and the silicon oxide film 4 is again formed on the entire surface by 300 times.
Å is formed, then 100 Å of silicon nitride film 5 is deposited, and then 5,000 Å of polysilicon is further deposited. Next, the upper 5000 Å of the polysilicon is converted into an oxide film by steam oxidation at 950 ° C. and removed by buffered hydrofluoric acid, and the remaining polysilicon is converted to an oxide film 6 by oxidation at 950 ° C. hydrochloric acid. Next, the polysilicon 7 is deposited again at 5000 Å, the upper 5000 Å is changed to an oxide film by steam oxidation at 950 ° C. and removed by buffered hydrofluoric acid, and the silicon nitride film 5 covering the substrate surface other than the trench is removed by RIE. Next, the surface of the polysilicon 7 is nitrided by 50Å in a NH ₃ atmosphere of 1100 ° C. to form a nitride film 9. As described above, an element isolation region having no film thickness reduction due to hydrofluoric acid treatment in the process and having no dimension shift is formed. Elements such as transistors are formed in the silicon substrate region by a conventionally known technique.

<Effects of the device> As described above, the element isolation region according to the present invention can be formed in a small area because there is no dimensional shift, and since it is covered with the silicon nitride film, it is not reduced by hydrofluoric acid treatment during the process Even if the silicon nitride film is not sufficiently covered, since polysilicon exists under the silicon nitride film, the silicon oxide is not corroded by hydrofluoric acid treatment or the like. Further, since the etch back can be processed in the oxidation step, the variation can be reduced and the uniformity can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing an element isolation structure of an embodiment according to the present invention, and FIGS. 2 (a) to 2 (d) are sectional views explaining a manufacturing process of the same embodiment. 1: Silicon substrate, 2: Groove, 4: Oxide film, 5: Silicon nitride film,
6: oxide, 7: polysilicon, 8: oxide film, 9: silicon nitride film.

Claims (1)

[Scope of utility model registration request] 1. An insulating film is formed on an inner wall of a groove formed in a silicon substrate, and the groove covered with the insulating film has a lower part made of a silicon oxide layer and an upper part made of a polysilicon layer.
A semiconductor element isolation structure, wherein a layer filling material is filled and a silicon nitride film is formed on the surface of the polysilicon so as to cover the opening.