JPH07264077A - Error detection and correction circuit - Google Patents

Abstract

PURPOSE:To prevent the frequency of the changeover of an operating mode when a transmission error rate fluctuates near a threshold value in an error detection and correction circuit for changing error correction ability corresponding to the transmission error rate. CONSTITUTION:A data reproduction circuit 12 reproduces data from the input signals of an input terminal 10, an error information detection circuit 14 detects the transmission error rate from the reproduced data and a mode setting circuit 16 outputs a mode control signal for switching an error correction mode so as to provide hysterisis characteristics stipulated by the threshold values (a) and (b) corresponding to the threshold values (a) and (b) from a threshold value setting circuit 17 and error rate information from the circuit 14. The threshold value setting circuit 17 outputs the threshold value (a) or (b) {<(a)} of a numerical value corresponding to the operation of a user to the mode setting circuit 16 and an error correction circuit 18 decodes error correction codes in the reproduced data from the data reproduction circuit 12 by the decoding algorithm of the error correction mode corresponding to the mode control signal from the circuit 16 and detects and corrects transmission errors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detection / correction circuit, and more particularly to an error detection / correction circuit for detecting and correcting an error generated during transmission (including recording / reproduction) of digital data.

[0002]

2. Description of the Related Art Generally, in a digital data transmission (recording / reproducing) system, an error correction code for correcting a transmission error is used. That is, in the conventional digital transmission system, the transmission (recording) side performs error correction coding on the transmission data, and the receiving side receives (reproduces) the data including the error due to the transmission and decodes the error correction code to generate the error. Is detected and corrected, and the correct data is restored as much as possible. Further, when handling digital image data in such a digital transmission system, an interpolation technique of substituting approximate values for uncorrectable data is used. An error detection / correction circuit that allows effective use of such an interpolation technique has been applied as, for example, Japanese Patent Application No. 144530 in 1991 (Japanese Patent Application Publication No. 10422 in 1991).

In this patent application, when the transmission error rate deteriorates, the interpolation process is utilized rather than the error correction to reduce the image quality deterioration of the reproduced image due to the erroneous correction of the transmission error. That is, the information about the number of transmission errors, that is, the information about the transmission error rate is detected from the input data string, and the decoding algorithm of the error correction code is set to two modes, the normal mode and the error rate deterioration mode, according to the detected error rate information. Switch between. If the error correction code is a code capable of two-error correction and the transmission error rate is small, error correction processing is executed for one error and two errors, and if three or more errors are uncorrectable, interpolation processing is executed at a later stage ( (Normal mode), if the transmission error rate deteriorates and exceeds a predetermined threshold value, 1
The correction process is executed only for the error, and the correction process is executed if the error is two or more, and the interpolation process is executed in the subsequent stage (error rate deterioration mode).

FIG. 5 is a characteristic diagram of the error correction probability (and interpolation probability) with respect to the transmission error rate. The vertical axis represents the error correction probability and the interpolation probability, and the horizontal axis represents the transmission error rate. FIG. 5 shows a characteristic example of the decoding error rate in the error rate worsening mode. A straight line 50 indicated by a dotted line is an interpolation probability in two correction modes, that is, a normal mode (probability of interpolation in uncorrectable processing), a straight line 52 indicated by a dotted line is an erroneous correction probability in a normal mode, and a straight line 54 indicated by a dotted line is 1. The correction mode, that is, the interpolation probability in the error rate worsening mode, and the straight line 56 shown by the dotted line is the error correction probability in the error rate worsening mode. As can be seen from FIG. 5, generally, in the error rate worsening mode, the interpolation probability is higher than in the normal mode, but the error correction probability is low.

In the above-mentioned patent application, when the transmission error rate a is smaller than the threshold value a, the normal mode is set, and when the transmission error rate is equal to or higher than the threshold value a, the error rate deterioration mode is set. I have to. As a result, the interpolation probability and the error correction probability change as shown by the thick solid line in FIG. 5, and the received data is decoded in the normal mode in the area where the transmission error rate is small, and the error rate deteriorates in the area where the transmission error rate is large. Decrypted in mode. As a result, the error correction probability can be suppressed to a low value within the allowable range except when the transmission error rate becomes extremely large, and it is possible to prevent extreme deterioration in image quality.

[0006]

In the above-mentioned conventional example, when the transmission error rate repeatedly fluctuates in the vicinity of the threshold value a or when the value continues to take the value in the vicinity of the threshold value a, the switching of the operation modes is frequently repeated, which is a win. As a result, there is a problem that two states having different image qualities are switched many times in a short time, and as a result, an image that is difficult to see is reproduced.

An object of the present invention is to provide an error detection / correction circuit capable of providing an image of stable image quality with stable operation even when the transmission error rate fluctuates as described above.

Further, in recent years, transmission media have become diversified, and it is often seen that the same device is used in transmission lines having different characteristics. In such a situation, it is desirable to be able to select the image quality of the reproduced image according to the usage situation, the transmission path and the preference of the user.

Another object of the present invention is to provide an error detection / correction circuit satisfying such demands.

[0010]

An error detection / correction circuit according to the present invention detects error information relating to the number of errors occurring in an input data string from an input data string and makes an error in accordance with the detected error information. An error detection / correction circuit for determining a correction mode and correcting an error in an input data string in the determined error correction mode, comprising at least two threshold values for determining the error correction mode, Second
The first threshold value is used for the transition to the error correction mode, and the second threshold value is used for the transition from the second error correction mode to the first error correction mode.

Preferably, the first error correction mode corresponds to a small transmission error rate, the second error correction mode corresponds to a large transmission error rate, and the first threshold value is set to the second threshold value. Keep it larger than the threshold.

[0012]

Since the error correction mode is determined by the above means with the hysteresis characteristic, the error correction mode is switched even if the transmission error rate fluctuates in the vicinity of any threshold value for determining the error correction mode. Will not occur frequently. As a result, it becomes possible to supply a stable image with stable image quality.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a schematic block diagram of an embodiment of the present invention.

Referring to FIG. A digital data string including a transmission error is input to the input terminal 10. The data reproduction circuit 12 demodulates the input data from the input terminal 10 and reproduces the data by synchronizing separation and ID recognition. The error information detection circuit 14 detects information about the number of transmission errors, that is, the transmission error rate, from the reproduced data. The error information detected by the error information detection circuit 14 is the mode setting circuit 1
6 is supplied. The mode setting circuit 16 switches the error correction mode according to the error information from the error information detection circuit 14 and the threshold values a and b from the threshold value setting circuit 17 so as to have the hysteresis characteristic defined by the threshold values a and b. Is output. This mode control signal is 1 or 0
It is a bit signal. Threshold values a and b and mode setting circuit 16
Details of will be described later.

The threshold value setting circuit 17 outputs the numerical value threshold values a and b to the mode setting circuit 16 according to a keyboard or a ten key operated by the user. That is, both the threshold values a and b are changeable, but only one of them may be changeable. The user or the like sets the threshold values a and b to appropriate values in consideration of the transmission path to be used, the usage of the data after error correction, and the audience for viewing if the data is video information. As a result, even when the same device is connected to different transmission paths, it is possible to flexibly deal with it.

The error correction circuit 18 is a mode setting circuit 16
The error correction code in the reproduction data from the data reproduction circuit 12 is decoded by the decoding algorithm of the error correction mode according to the mode control signal from ## EQU1 ## to detect and correct the transmission error.
That is, the error correction circuit 18 corrects the transmission error by the optimum decoding algorithm according to the transmission error rate. The error correction circuit 18 outputs correct data, error-corrected data, or erroneous data with a correction flag to the output terminal 20.

A specific description will be given of a case where the error correction code used is a code capable of two-error correction and has two decoding modes (normal mode and error rate worsening mode) according to the transmission error rate. . If the error rate is low, the error correction circuit 1
8 operates in the normal mode, corrects 1 error and 2 errors, but makes 3 or more errors uncorrectable. Further, when the error rate of the transmission line deteriorates beyond a predetermined value, the error correction circuit 18 operates in the error rate deterioration mode and corrects only one error.
Two or more errors are uncorrectable.

In the error correction processing in the error correction circuit 18, the error position and the error pattern are calculated, the error data is corrected using the calculation result, and the corrected data is output.
In the uncorrectable processing, the data of the code determined to be unable to correct the error is output as it is, and the correction flag indicating that the error is included is output. For example, an interpolation circuit in the subsequent stage replaces error data with an interpolation value according to the modification flag.

FIG. 2 shows an operation flowchart of the mode setting circuit 16, and FIG. 3 shows a characteristic diagram of the mode setting circuit 16. Here, a case will be described in which two types of decoding modes can be selected in accordance with the transmission error rate in correspondence with the operation description of the error correction circuit 18.

First, the current mode M is recognized (S1), and then the error information e output from the error information detection circuit 14 is read (S2). The current mode is checked (S3). In the normal mode (that is, M = 0), the error information e and the threshold value a
(S4), and when the error information e is equal to or greater than the threshold value a,
The mode is changed to the error rate deterioration mode (M = 1) (S7), and when the error information e is less than the threshold value a, the normal mode is kept (S7).
5). In addition, the current mode is the error rate deterioration mode (that is,
In the case of M = 1) (S3), the error information e is compared with the threshold value b (S6), and when the error information e is greater than or equal to the threshold value b, the error rate deterioration mode (M = 1) is kept (S7). ), When the error information e is less than the threshold value b, the mode is changed to the normal mode (M = 0) (S5). After S5 and S7, M is output to the error correction circuit 18 as a mode control signal.

The mode setting circuit 16 repeatedly executes the operation shown in FIG. 2 in units of a predetermined time.

In FIG. 2, in the change in the direction in which the transmission error rate deteriorates, when the transmission error rate e exceeds the threshold value a, the normal mode is changed to the error rate deterioration mode, and the transmission error rate improves. In the change, when the transmission error rate e exceeds the threshold value b, the error rate deterioration mode is changed to the normal mode. Since the threshold value a is set to a value larger than the threshold value b, the characteristics of the decoding mode in the error correction circuit 18, that is, the error correction probability and the interpolation probability with respect to the transmission error rate are as shown by the thick solid line in FIG. Become a characteristic. Dotted line 50 to FIG.
56 is the same as the dotted lines 50 to 56 in FIG.

By adopting different thresholds a and b for switching from the error rate worsening mode to the normal mode and switching from the normal mode to the error rate worsening mode, and providing a hysteresis characteristic as shown in FIG. As described above, the frequent switching of operation modes, which has occurred when the transmission error rate repeatedly fluctuates near the threshold value or when the value near the threshold value continues to be eliminated, is eliminated. As a result, it is possible to provide a reproduced image with stable image quality, which eliminates the problem that an invisible image that is repeatedly switched between two states having different image quality within a short time is reproduced.

FIG. 4 shows a schematic block diagram of an embodiment applied to an error detection / correction circuit using syndrome calculation. Similar to the input terminal 10, a digital data string including a transmission error is input to the input terminal 22. The data reproduction circuit 24 demodulates the data string from the input terminal 22 and reproduces the data by synchronizing separation and ID recognition. The reproduction data output from the data reproduction circuit 24 is the recognized ID.
The information is directly written to the data memory 26 and simultaneously applied to the syndrome calculation circuit 28 for error correction.

The syndrome calculation circuit 28 calculates the syndrome of the transmission data by a well-known method, and sequentially writes the syndrome of each code in the syndrome memory 30. The calculation result of the syndrome calculation circuit 28 is also supplied to the syndrome 0 determination circuit 32. The syndrome 0 determination circuit 32 determines whether or not all the syndromes of each code are 0 on a code-by-code basis. The counter 34 counts the number of codes whose syndromes are not all 0, that is, the number of codes in which an error has occurred, based on the judgment result of the syndrome 0 judgment circuit 32. The count value of the counter 34 within a predetermined time indicates the transmission error rate. In this embodiment, the function of the error information detection circuit 14 shown in FIG. 1 is realized by counting the syndrome calculation results.

The counting result of the counter 34, that is, the error information is applied to the mode setting circuit 36. The mode setting circuit 36 includes a threshold setting circuit 37 similar to the threshold setting circuit 17.
Are supplied with two threshold values a and b. According to the counting result (error information) from the counter 34 and the thresholds a and b from the threshold setting circuit 37, the mode setting circuit 36 follows the same algorithm as shown in FIG. 2 and has different hysteresis characteristics with different thresholds a and b. A mode control signal for switching the error correction mode is output to. Also in this embodiment, the threshold value setting circuit 37 outputs the numerical value threshold values a and b to the mode setting circuit 36 according to the keyboard or the numeric keypad operated by the user, like the threshold value setting circuit 17. That is, both the threshold values a and b are changeable, and only one of them may be changeable. The user or the like sets the threshold values a and b to appropriate values in consideration of the transmission path to be used, the usage of the data after error correction, and the audience for viewing if the data is video information. As a result, even when the same device is connected to different transmission paths, it is possible to flexibly deal with it.

The error calculation circuit 40 for calculating the error position and the error pattern is composed of a general-purpose arithmetic processing circuit, and the actual operation is determined by the program module supplied from the microprogram storage circuit 38. The micro program storage circuit 38 stores a plurality of program modules of different decoding algorithms,
The program module designated by the mode control signal from the mode setting circuit 36 is loaded into the error calculation circuit 40. With this configuration, the operation or function of the error calculation circuit 40 is switched according to the current transmission error rate.

Also in the embodiment shown in FIG. 4, the decoding characteristic of the error correction code is set to the hysteresis characteristic as shown by the thick solid line in FIG. 3, so that the transmission error rate repeatedly fluctuates in the vicinity of one threshold value. Even when the value near one threshold value is continuously taken, the decoding algorithm is not frequently switched, and the error correction operation is very stable.

The error calculation circuit 40 reads the syndrome written in the syndrome memory 30 and performs decoding calculation of the error correction code. Here, the error calculation circuit 40
If all the syndromes of the corresponding code are 0, it judges that there is no error and terminates the processing of that code. However, if the syndromes are not all 0s, that is, there is an error, the error can be corrected. If it is determined that the error position and the error pattern are calculated, the data on the data memory 26 is corrected using the calculation result. When it is determined that the error cannot be corrected, the data memory 2 of the corresponding code
The data on 6 is left as it is, and a correction flag indicating that an error is included is written in a predetermined portion of the data memory 26. After the error correction processing is completed, the data and the correction flag on the data memory 26 are read out and output from the output terminal 42 to the outside.

In each of the two embodiments described above, the error correction code capable of correcting up to two errors is taken as an example, but it is obvious that the present invention is not limited to this. Also,
The error correction mode is not limited to two.

In the above embodiment, the transmission error rate threshold a for the transition from the normal mode to the error rate deterioration mode is set to a value larger than the transmission error rate threshold b for the transition from the error rate deterioration mode to the normal mode. However, conversely, the threshold value a may be smaller than the threshold value b in the sense that the frequent switching of the error correction mode due to the fluctuation of the transmission error rate near the threshold value is prevented. For example, when the signal deterioration due to interpolation is less than the signal deterioration due to erroneous correction, the latter is more likely to have less signal deterioration as a whole.

[0033]

As can be easily understood from the above description, according to the present invention, since the hysteresis characteristic is provided in the change of the error correction capability, the threshold value for changing the error correction mode or the error correction capability is set. Even when the transmission error rate repeatedly changes in the vicinity, or when the value near the threshold is continuously maintained, the error correction mode or the error correction capability is not frequently switched. As a result, for example, in the case of an image, it is possible to provide a reproduced image with stable image quality, without switching between two states having different image quality many times within a short time. Further, the present invention can be realized by adding a simple circuit.

Further, by making one or both of the threshold values a and b of the hysteresis characteristic freely changeable, it is possible to flexibly cope with the case where the same device is connected to different transmission lines.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart showing a mode setting algorithm of a mode setting circuit 16.

FIG. 3 is a characteristic diagram according to a mode transition of the present embodiment.

FIG. 4 is a schematic block diagram of a second embodiment of the present invention.

FIG. 5 is a characteristic diagram according to a mode transition of a conventional example.

[Explanation of symbols]

10: Input terminal 12: Data reproduction circuit 14: Error information detection circuit 16: Mode setting circuit 17: Threshold setting circuit 18: Error correction circuit 20: Output terminal 22: Input terminal 24: Data reproduction circuit 26: Data memory
28: Syndrome calculation circuit 30: Syndrome memory 32: Syndrome 0 determination circuit 34: Counter 36: Mode setting circuit 37: Threshold setting circuit 38:
Micro program storage circuit 40: Calculation circuit 42:
Output terminal 50: Interpolation probability in normal mode 52: Error correction probability in normal mode 54: Interpolation probability in error rate worsening mode 56: Error correction probability in error rate worsening mode

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Claims (9)

[Claims] 1. An error information detecting means for detecting error information relating to the number of errors occurring in the input data string from the input data string, and an error correction mode in accordance with the error information detected by the error information detecting means. An error detection / correction circuit comprising: an error correction mode determining means for determining; and an error correcting means for correcting an error in an input data string in an error correction mode according to the output of the error correction mode determining means. Has at least two threshold values that determine the error correction mode, and a first threshold value is used for the transition from the first error correction mode to the second error correction mode, and a first threshold value is used for the transition from the second error correction mode to the first error correction mode. An error detection and correction circuit characterized in that a second threshold value is used for the transition to the error correction mode of. 2. The first error correction mode corresponds to a small transmission error rate, the second error correction mode corresponds to a large transmission error rate, and the first threshold is larger than the second threshold. The error detection and correction circuit according to claim 1. 3. The error information detecting means calculates a syndrome of an error correction code, a syndrome calculating means for judging whether or not the syndrome is all 0s in a code unit, and a syndrome 0 judging means. 3. The error detection / correction circuit according to claim 1, further comprising a counter unit that counts the code determined to be 0 by the fixed period. 4. The error detection / correction circuit according to claim 1, wherein at least one of the first threshold value and the second threshold value is changeable. 5. A syndrome calculation means for calculating a syndrome for error detection and correction from an input data string, a syndrome memory means for storing a calculation result of the syndrome calculation means, and a syndrome calculated by the syndrome calculation means. Syndrome 0 judging means for judging whether all are 0 in a code unit, counter means for counting a code judged to be 0 by the syndrome 0 judging means for a certain period, and an error correction mode according to an output value of the counter means. And an error correction mode that determines the error correction mode determining means and operates in an error correction mode according to the output of the error correction mode determining means. The error correction code is decoded by referring to the syndrome memory means and the error in the input data string is corrected. An error detection / correction circuit comprising an error correction unit, The stage comprises at least two thresholds for determining an error correction mode, the first threshold for transition from the first error correction mode to the second error correction mode, and the second error correction mode for the second error correction mode. An error detection / correction circuit characterized in that a second threshold value is used for transition to 1 error correction mode. 6. The first error correction mode corresponds to a small transmission error rate, the second error correction mode corresponds to a large transmission error rate, and the first threshold is larger than the second threshold. The error detection and correction circuit according to claim 5. 7. The error detection and correction circuit according to claim 5, wherein at least one of the first threshold value and the second threshold value is changeable. 8. An error detection / correction circuit in which the error correction capability can be freely changed according to a transmission error rate, and the error detection / correction circuit is provided with a hysteresis characteristic in the change of the error correction capability. 9. The error detection / correction circuit according to claim 8, wherein at least one of at least two threshold values of the hysteresis characteristic is changeable.