JPH07263620A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide the title semiconductor device capable of making the improvement of the reliability upon the element connection and the mounting density, the reduction in manufacturing cost and the realization of high yield in various functions feasible. CONSTITUTION:Within the title semiconductor device, elements 103 are directly connected through the intermediary of CCB bumps 102 by multiple elements 101 striding over said elements 103 so that the plural elements 101 and 103 mutually comprising the material having the same physical properties such as silicon etc., may be contained between a pair of sheetlike reinforcement members 11. Accordingly, the gap between the reinforcement members 11 is air-tightly sealed with a sealing member 12 so that the connector 10 connecting the elements 101 may be externally protruded from the gap between the reinforcement member 11 for inputting and outputting the external electrical signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effectively applied to miniaturization and improvement of reliability of the semiconductor device.

[0002]

2. Description of the Related Art For example, in a method of mounting a semiconductor device, usually, an individual semiconductor element is enclosed in a package and is fixedly connected to a desired substrate through a plurality of pins projecting outside the package. Technology was common.

Regarding the mounting technique of the semiconductor device,
For example, it is described in documents such as Nikkei McGraw-Hill, June 11, 1984, Nikkei Electronics Separate Volume No. 2 “Micro Devices” P160 to P168.

[0004]

In the above-mentioned conventional technique, since the semiconductor elements are packaged in individual packages, there are problems that (a) the mounting density is low and (b) the mounting delay is large. To solve this problem, MCM (Multi Chip Mo
It is possible to use the technology called dule). That is, a plurality of elements are mounted on a common base. In this case, if the element and the base are connected by the WB (Wire Bonding) technique, other problems such as a small limit of the number of input / output signal electrodes and a large mounting delay occur.

Further, when a multilayer wiring structure is provided in the base and the element and the base are connected by CCB (Controlled Collaspe Bonding) technology, the reliability of the connection portion due to the difference in thermal expansion coefficient between the element and the base is improved. It is only applicable to high value-added and expensive systems due to the problem of increased manufacturing costs due to the use of expensive bases with complicated wiring.

An object of the present invention is to provide a semiconductor device capable of improving the reliability of element connection.

Another object of the present invention is to provide a semiconductor device capable of improving packaging density.

Still another object of the present invention is to provide a semiconductor device capable of reducing manufacturing cost.

Still another object of the present invention is to provide a semiconductor device which can realize various functions with high yield.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the present invention is a semiconductor device in which a plurality of elements having external connection electrodes on the surface directly connect the external connection electrodes to each other to connect the elements.

Further, the present invention is a semiconductor device in which one element is connected to a plurality of other elements so as to connect the plurality of elements.

Each of the plurality of elements can be composed of a CPU and a memory accessed by the CPU. Further, each of the plurality of elements is composed of a CPU, and can form a multi-CPU system. Further, each of the plurality of elements can be formed with each of a plurality of logical function blocks that constitute one CPU. Also,
Each of the plurality of elements can be composed of a bipolar element and a MOS or CMOS element. Further, the plurality of elements are composed of a plurality of memory elements and can form a memory card or a memory module. Further, some of the plurality of elements may have a wiring structure only.

[0015]

According to the above-described semiconductor device of the present invention, since a plurality of elements are directly connected via the external connection electrodes formed on the surface thereof, the elements are made of other materials, for example. As in the case of fixing to the base or the like, it is possible to avoid a decrease in the reliability of the connecting portion due to the difference in the thermal expansion coefficient between the two, and to improve the reliability of the connection between the elements.
Further, since the plurality of elements are connected in a state where some of them are overlapped with each other, the projected area on the mounting surface is reduced and the mounting density is improved. Further, since it is not necessary to use an expensive base member having a complicated wiring structure formed therein, it is possible to reduce the manufacturing cost. Further, since each element can be given an arbitrary function in various processes, a multi-CP in which CPUs having various functions or a plurality of types of CPUs are combined
It is possible to construct various systems such as U and further a memory card. In addition, since the yield at the time of manufacturing is determined for each individual element unit, a higher yield is realized as compared with, for example, a case in which a large number of circuit elements are collectively incorporated in one large chip for multi-functionalization. be able to.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a side view showing an example of the configuration of a semiconductor device which is an embodiment of the present invention, and FIGS. 2, 3 and 4 show an example of the sealing form. It is a schematic sectional drawing shown.

As illustrated in FIG. 1, a plurality of elements 1 made of silicon, for example, are directly connected to an element 3 made of the same silicon via CCB bumps 2 made of solder balls, for example. In this case, the element 3 is
For example, when it is composed of a CPU, the plurality of elements 1 connected thereto may be, for example, a memory or a cache memory accessed by the CPU, or a CPU peripheral circuit element.

Further, a plurality of elements having different types of manufacturing processes can be mixed and integrated without any difficulty, as in the case where the element 3 is a bipolar element and the element 1 is a MOS element or a CMOS element.

In the case of the present embodiment, the structure of FIG. 1 as described above is, for example, the sealing form illustrated in FIG. That is, in FIG. 2, a recess 5 a is formed in the center of the base 5.
Is formed, and the radiation fin 4 is formed so as to cover the recess 5a.
The cap-shaped heat sink 4 having a is airtightly joined. The plurality of elements 1 having the configuration of FIG. 1 are mounted on the base 5 so as to be in close contact with the bottom of the recess 5a via the bonding layer 1a such as a solder layer.
The bottom surface is adhered to the heat sink 4 via the bonding layer 3a such as a solder layer, which dissipates the heat generated during operation to the outside and also the CCB bumps 2 provided in the peripheral portion.
The wiring 6 exposed at the protruding portion around the base 5 via a
Is connected to the inner end of. The outer end of the wiring 6 of the base 5 is electrically connected to a plurality of I / O pins 7 protruding from the bottom surface of the base 5, and the I / O pins 7, the wiring 6 and the CCB bumps 2a are formed. Power and electric signals are exchanged between the element 1 and the element 3 inside and the outside via the.

Further, as the sealing form, for example, the structure illustrated in FIG. 3 can be considered. In the case of FIG. 3, the base 5 has a convex cross section, and the inner end of the wiring 6 is exposed at the central protruding portion. On the element side, a plurality of elements 1 are mounted on the peripheral portion of the element 3 serving as a base via the CCB bumps 2, and C is provided in the empty area in the central portion.
The CB bump 2a is arranged and connected to the inner end of the wiring 6 of the base 5. Also in this case, the top of the element 1 is in close contact with the base 5 via the bonding layer 1a such as a solder layer, and the bottom surface of the element 3 is in close contact with the heat sink 4 via the bonding layer 3a such as a solder layer. , Make efficient heat dissipation.

Further, it is also conceivable to adopt the sealing form illustrated in FIG. In the case of FIG. 4, an element 3 having a plurality of elements 1 mounted thereon is fixed to the upper surface of a flat base 5 via a bonding layer 3a such as a solder layer, and is provided in the peripheral portion of the element 3. A bonding wire 8 is laid between the unbonded bonding pad and the inner end of the wiring 6 of the base 5 to establish electrical connection with the I / O pin 7. The tops of the plurality of elements 1 mounted on the element 3 are in close contact with the central protruding portion of the heat sink 4 via a bonding layer 1a such as a solder layer, and allow heat to be radiated through the heat sink 4.

As described above, in the semiconductor device of this embodiment,
Since a plurality of elements 1 are directly mounted on the elements 3 via the CCB bumps 2, for example, compared to a configuration in which the elements 1 and the like are mounted on a base member or the like made of different materials, C
The thermal stress or the like generated in the CB bump 2 is relaxed, and the reliability of the connection between the element 1 and the element 3 by the CCB bump 2 is improved. In particular, in each of the sealing forms illustrated in FIGS. 2 to 4, the element 1 and the element 3 are constrained by the heat sink 4 or the base 5 side in each case. Although there is a concern that the action of thermal stress may increase, in the case of this embodiment, since both the element 1 and the element 3 are made of the same material such as silicon, the difference in thermal expansion coefficient, etc. There is no concern that the above-described thermal stress will be generated due to the above, and the reliability of bonding by the CCB bump 2 is improved.

In the conventional structure in which the element 1 and the element 3 are mounted on a common base member or the like, the transmission delay of the electric signal between the element 1 and the element 3 is avoided by the length of the wiring provided on the base member or the like. However, in the case of the present embodiment, since both are directly connected via the CCB bump 2,
The signal transmission delay time can be suppressed to a minimum, and the operation speed of the system in which the elements 1 and 3 are combined can be increased. For example, the element 3 is a CPU, and the element 1 is the CP
In the configuration in which the cache memory is accessed by U, the CPU can speed up the access to the cache memory and the like.

Furthermore, when a common base member or the like is used as in the prior art, it is necessary to provide a multilayer wiring structure or the like inside the base member, and the base member itself is expensive due to the complexity of the structure. However, in the case of the present embodiment, it is not necessary to use such an expensive base member or the like, so that the wiring 6 in the base 5 has a minimum necessary amount. A simple structure is sufficient and the manufacturing cost can be reduced.

Further, from the viewpoint of manufacturing yield, when the elements 1 and 3 are collectively formed in the same chip, the defect of only one must be discarded and the other must be discarded. The yield is inevitably low due to an increase in chip size, which is disadvantageous in terms of yield. However, in the case of this embodiment, since the element 1 and the element 3 are manufactured separately, the yield in each manufacturing process becomes high. The overall yield of the system that combines both is also improved.

Further, the signal propagation delay time due to the separation of the element 1 and the element 3 can be minimized by directly connecting the two by the CCB bumps 2, and the performance deterioration from the viewpoint of the propagation delay time can be suppressed. .

Further, since the plurality of elements 1 are superposed on the element 3, the sealing is provided as compared with the conventional configuration in which the elements 1 and 3 are simply mounted on a common base member or the like in a plane. The entire projected area of the stopper structure with respect to the base 5 is also reduced, and the packaging density can be improved and the size can be reduced.

(Embodiment 2) FIG. 5 is a side view showing an example of the configuration of a semiconductor device according to another embodiment of the present invention. FIG. 6 is a perspective view thereof, and FIG. 7 is a sealing form thereof. It is a perspective view which fractures | ruptures a part of FIG.

In the case of this embodiment, a plurality of elements 103
Is configured to be directly connected via the CCB bumps 102 by a plurality of the elements 101 that straddle the elements 103. The element 101 and the element 103 are
They are made of materials having the same physical properties such as silicon.

That is, on the connection surface of the element 103, as shown in FIG.
, A plurality of BLMs (Ball Limitting M
etalization) and other bonding patterns 9 are provided,
The CCB bump 2 on the element 101 side can be connected to an arbitrary position. The connector 10 is connected to some of the elements 101 via CCB bumps 102. The connector 10 can be made of the same material as the elements 101 and 103.

In this case, if both the element 103 and the element 101 are memory elements, a small-sized and large-capacity memory card can be constructed. In addition, each element 103 has a different CP
When U is set, a multi-CPU system can be constructed. In this case, the element 101 connecting the element 103 may have a structure having only a wiring structure, or may be a shared memory or a cache memory accessed by each CPU.

It is also conceivable that one CPU is used in the entire configuration illustrated in FIGS. 5 and 6. In this case, for example, the arithmetic logic unit (ALU) and the memory management unit (MM
U), the advance control circuit, the branch prediction circuit, the cache memory, the register file, the tag storage, etc. are arranged in a distributed manner, and a CPU having various functions and performances is obtained by combining the respective logic function blocks. The configuration may be realized.

Then, the entire configuration illustrated in FIG.
For example, it is sealed as illustrated in FIG. That is, a configuration in which a plurality of elements 103 are directly connected via the element 101 is sandwiched between a pair of plate-shaped reinforcing members 11, and the sealing material 12 is provided in a gap around the reinforcing members 11.
To be hermetically sealed.

The sealing structure of FIG. 7 is, for example, the element 1
When 01 and the element 103 are memory elements, a small and large-capacity IC card, memory card, or memory module can be obtained.

Also in the case of this embodiment, a multi CPU,
A CPU module, a memory card, an IC card, a memory module, and the like can be constructed with high integration, high yield, and reliability, and mounting dimensions can be significantly reduced, and miniaturization can be achieved.

The sealing form of the structure shown in FIG. 5 is not limited to that shown in FIG.
The sealing form illustrated in FIGS. 9 and 10 can also be adopted. The sealing forms of FIGS. 8 to 10 correspond to the above-described FIGS. 2 to 4, respectively, and use the structure of FIG. 5 as an internal structure instead of the structure of FIG.
In order to avoid duplication, the same components will be assigned the same reference numerals and explanations thereof will be omitted.

That is, in the sealing mode shown in FIG. 8, the plurality of elements 103 are provided on the heat sink 4 side with the bonding layer 1 such as a solder layer.
03a, and a plurality of elements 101 connected across them are joined to the base 5 side via a joining layer 101a, and via CCB bumps 102a provided on the element 103 located in the outer peripheral portion. , Wiring 6 on the base 5 side
It is configured to be electrically connected to the inner end of the.

Further, in the sealing form of FIG. 9, a plurality of elements 1
03 on the side of the heat sink 4
a, a plurality of elements 101 connected to each other are joined to the base 5 side via a joining layer 101a, and a base is provided via a CCB bump 102a provided in the central portion of the element 103. The wiring 6 on the 5 side is electrically connected to the inner end of the wiring 6.

In addition, the sealing form of FIG.
03 on the side of the flat base 5 and a bonding layer 103 such as a solder layer.
a, a plurality of elements 101 connected to each other are connected to each other via the bonding layer 101a and the heat sink 4
A bonding pad (not shown) that is bonded to the side of the element 103 and is provided in the peripheral portion of the element 103 is electrically connected to the inner end of the wiring 6 on the side of the base 5 via the bonding wire 8.

Even when the respective sealing forms of FIGS. 8 to 10 are adopted, the CCB bump 1 is formed by the plurality of elements 103 by the plurality of elements 101 extending between the elements 103.
By connecting directly via 02,
The mounting dimensions can be greatly reduced, and high-density mounting can be realized. In addition, since the elements 101 and 103 are made of the same material, the elements 101 and 103 are constrained by the base 5 and the heat sink 4 so that the CCB bump 10 can be prevented.
The thermal stress acting on 2 can be relaxed, and a highly reliable connection structure can be realized. Further, it is not necessary to complicate the structure of the wiring 6 in the base 5 more than necessary to connect the elements 101 and 103, and it is possible to significantly reduce the total manufacturing cost including the sealing structure. Become.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the sealing form is not limited to the one exemplified in the above-mentioned embodiment, and a general sealing form can be widely adopted.

[0044]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

That is, according to the semiconductor device of the present invention,
The effect that the reliability of the connection of the elements can be improved is obtained. Further, it is possible to obtain an effect that the packaging density can be improved. Further, there is an effect that the manufacturing cost can be reduced. Further, there is an effect that various functions can be realized with high yield.

[Brief description of drawings]

FIG. 1 is a side view showing an example of the configuration of a semiconductor device that is an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing an example of the sealing form.

FIG. 3 is a schematic cross-sectional view showing an example of the sealing form.

FIG. 4 is a schematic cross-sectional view showing an example of the sealing form.

FIG. 5 is a side view showing an example of the configuration of a semiconductor device that is another embodiment of the present invention.

FIG. 6 is a perspective view thereof.

FIG. 7 is a perspective view illustrating a part of the sealed form by breaking it.

FIG. 8 is a schematic cross-sectional view showing an example of the sealing form.

FIG. 9 is a schematic cross-sectional view showing an example of the sealing form.

FIG. 10 is a schematic cross-sectional view showing an example of the sealing form.

[Explanation of symbols]

 1 Element 1a Bonding Layer 2 CCB Bump (External Connection Electrode) 2a CCB Bump (External Connection Electrode) 3 Element 3a Bonding Layer 4 Heat Sink 4a Heat Radiation Fin 5 Base 5a Recess 6 Wiring 7 I / O Pin 8 Bonding Wire 9 Bonding Pattern (External) Connection electrode) 10 Connector 11 Reinforcing member 12 Sealing material 101 Element 101a Bonding layer 102 CCB bump (external connection electrode) 102a CCB bump (external connection electrode) 103 Element 103a Bonding layer

Claims (8)

[Claims] 1. A semiconductor device comprising: a plurality of elements each having an external connection electrode on its surface, wherein the external connection electrodes are directly connected to each other. 2. The semiconductor device according to claim 1, wherein one of the elements is connected to the plurality of elements so that the plurality of elements are connected to each other. 3. The semiconductor device according to claim 1, wherein each of the plurality of elements is a CPU and a memory accessed by the CPU. 4. The semiconductor device according to claim 1, wherein each of the plurality of elements is composed of a CPU and constitutes a multi-CPU system. 5. The semiconductor device according to claim 1, wherein each of the plurality of elements is formed with each of a plurality of logical function blocks constituting one CPU in a dispersed manner. 6. The semiconductor device according to claim 1, wherein each of the plurality of elements comprises a bipolar element and a MOS or CMOS element. 7. The semiconductor device according to claim 1, wherein the plurality of elements are composed of a plurality of memory elements and constitute a memory card or a memory module. 8. The semiconductor device according to claim 1, wherein a part of the plurality of the elements has a wiring structure only.