JPH07263536A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device wherein the short between metal silicide layers of each element is prevented, about the semiconductor device wherein the metal.source.drain technology (salicide) is used. CONSTITUTION:An insulating projection 8 is formed for preventing the short between metal silicide layers on the surface of a field insulating film 2 which is formed between diffusion layers 5, 6 formed on the surface of a silicon substrate 1. By this, the metal siliside layers 9 which overhands the surface of the field insulating film 2 are blocked by the insulating projection and the short between the metal silicide layers 9 can be prevented between elements.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using metal source / drain technology (salicide).

[0002]

2. Description of the Related Art With the miniaturization of elements, it has become a problem that the sheet resistance of the source / drain regions increases and causes deterioration of mutual conductance. As a countermeasure against this, a salicide (self-alignment) for selectively silicifying the surface of the diffusion layer of the LSI is performed.
It has been conventionally practiced to use the d-siliconide technology.

FIG. 7 is a sectional view showing the structure of this type of semiconductor device. As shown in FIG. 7, in this semiconductor device, a field oxide film 112 is formed in the element isolation region on the main surface side of the P-type silicon substrate 111, and a gate oxide film 113 is further formed in the element formation region of the substrate 111. Through the gate electrode 114 and N ⁺ for source and drain
Diffusion layers 115 and 116 are formed.

The gate electrode 114 is covered with a SiO ₂ film (silicon oxide film) 117, and also the N ⁺ diffusion layer 11 is formed.
A metal silicide layer 118 made of TiSi ₂ is formed over a part of the surface of the field oxide film 112 adjacent to the surface of each of the films 5 and 116. Next, a method for manufacturing the semiconductor device of FIG. 7 will be described with reference to FIGS.

First, as shown in FIG.
S (Local Oxidation of Sili)
The field oxide film 2 is formed in the element isolation region of the P-type silicon substrate 1 by the (con) method. Further, after forming the gate oxide film 113 on the exposed surface of the silicon substrate 111, the gate electrode 114 is formed on the gate oxide film 113. Then, the gate oxide film 113 is selectively etched to open windows for source and drain regions, and N ⁺ is formed in the surface side of the P-type silicon substrate 111 through the windows.
Diffuses to form an N ⁺ diffusion layer (source / drain) 115,
116 is formed.

Next, after forming an insulating film 117a on the entire surface, the oxide film 117a is etched by a lithography technique to form the gate electrode 114 covered with the oxide film 117 (FIG. 9D). Then, the metal layer 1 on the entire surface
After stacking 18a, annealing is performed (FIG. 9E).
As a result, Si (silicon) in the N ⁺ diffusion layers 115 and 116 reacts with the metal component in the metal layer 1189a to silicify the metal layer 118a. After that, FIG.
As shown in (f), unreacted metal (titanium metal layer 11
By selectively removing the non-silicided portion of 8a, a metal silicide layer 118 is formed on the surfaces of the N ⁺ diffusion layers 115 and 116.

[0007]

However, in the above conventional semiconductor device, the metal silicide layer 11 of each element is
8 is formed so as to overhang a part of the surface of the field oxide film 112, there is a problem that the metal silicide layer 118 of each device is short-circuited when the miniaturization between the devices progresses and the field oxide film 112 is also reduced. It was

An object of the present invention is to provide a semiconductor device capable of preventing a short circuit of the metal silicide layer of each element.

[0009]

The above object is to provide a first and a second diffusion layer formed on the front surface side of the silicon substrate sandwiching a field insulating film formed in an element isolation region of the silicon substrate, In a semiconductor device having a metal silicide layer formed by siliciding the surfaces of the first and second diffusion layers, on the surface of the field insulating film sandwiched between the first and second diffusion layers, This is achieved by a semiconductor device characterized in that an insulating protrusion for preventing a short circuit of the metal silicide layer is formed.

In the above-mentioned semiconductor device, it is desirable that the insulating protrusions are composed of a SiO ₂ layer. In the above-described semiconductor device, it is preferable that the insulating protrusions are made of the same material as the constituent material of the gate electrodes provided near the first and second diffusion layers.

[0011]

According to the semiconductor device of the present invention, the first and second
Since the insulating protrusions for preventing the short-circuiting of the metal silicide layer are formed on the surface of the field insulating film sandwiched between the diffusion layers of, the metal silicide layer protruding on the surface of the field insulating film is blocked by the insulating protrusions. Therefore, it is possible to prevent a short circuit between the metal silicide layers between the respective elements.

[0012]

EXAMPLE A semiconductor device according to an example of the present invention will be described with reference to FIG. As shown in FIG. 1, the semiconductor device of this example (0.5 μm process) has a P-type silicon substrate 1, and a field oxide film 2 is formed in an element isolation region on the main surface side of the P-type silicon substrate 1. Has been formed. Further, in the element formation region of the substrate 1, a gate electrode 4 made of polysilicon, an N ⁺ diffusion layer 5 for source and an N ⁺ diffusion layer 6 for drain are formed via a gate oxide film 3. .

The gate electrode 4 is covered with a SiO ₂ film (silicon oxide film) 7 and extends from the surface of each of the N ⁺ diffusion layers 5 and 6 to a part of the surface of the field oxide film 2 adjacent to the surface. Metal silicide layers 9 (film thickness: about 100 nm) made of TiSi ₂ are formed respectively. Then, an element (N-channel MOS type transistor) having the same structure as described above is formed in an element formation region sandwiching the field oxide film 2, and a metal silicide from both elements is formed on the surface of the field oxide film 2. Insulating protrusions (first protrusions) 8 made of a SiO ₂ layer are formed with a film thickness of 100 to 200 nm to prevent a short circuit due to overhang of the layer 9.

Next, a method of manufacturing the semiconductor device of FIG. 1 will be described with reference to FIG.
3 and FIG. First, as shown in FIG. 2A, the field oxide film 2 is formed in the element isolation region of the P-type silicon substrate 1 by the LOCOS method. That is,
A SiO ₂ film and Si ₃ N ₄ are formed on the surface of the P-type silicon substrate 1.
After sequentially forming a film and a film, a pattern for selective oxidation is formed by this Si ₃ N ₄ film, and the silicon substrate 1 is field-oxidized by using this pattern as a mask.
A field oxide film 2 is formed on the main surface side of.

Further, a gate oxide film 3 is formed on the exposed surface of the silicon substrate 1, a polysilicon layer is further formed on the entire surface, and a pattern for a gate electrode is formed on the surface of the polysilicon layer by using a lithography technique. Form. Then, the polysilicon layer is etched using this pattern as a mask to form the gate electrode 4. Thereafter, the gate oxide film 3 is selectively etched to open windows for source and drain regions, and the P-type silicon substrate 1 is opened through the windows.
N ⁺ diffusion is performed in the surface side of the N to form N ⁺ N diffusion layers (source / drain) 5 and 6. At this time, a thin oxide film 3a is formed on the surfaces of the N ⁺ diffusion layers 5 and 6 (see FIG. 2).
(B)).

Next, after forming an oxide film 7 (film thickness: about 100 to 200 nm) on the entire surface by CVD, a photoresist is further applied and exposed and developed to form a resist pattern (FIG. 2C). This resist pattern is
The insulating projection 8 forming resist 7a selectively remains on the surface of the oxide film 7, and the resist also remains on the surface of the oxide film 7 on the gate electrode 4 (not shown).

Then, the oxide film 7 is etched by using the resist pattern as a mask, and the field oxide film 2 is formed.
An insulating protrusion 8 (film thickness: about 100 to 200 nm) is formed on the surface, and the gate electrode 4 is covered with an oxide film 7 (FIG. 3D). Then Ti over the entire surface
(Titanium) is vacuum-deposited to form a titanium metal layer 9a and then annealed (FIG. 3E).

As a result, Si (silicon) in the N ⁺ diffusion layers 5 and 6 reacts with Ti in the titanium metal layer 9a, and the titanium metal layer 9a is silicided in a self-aligned manner (no mask is required). After that, as shown in FIG. 3F, if the unreacted metal (the non-silicided portion of the titanium metal layer 9a) is selectively removed, the metal silicide layer (TiSi) is formed on the surface of the N ⁺ diffusion layers 5 and 6. ₂ ) 9 is formed,
A semiconductor device having the configuration shown in FIG. 1 can be obtained.

At this time, the metal silicide layer 9 is formed so as to extend to a part of the surface of the field oxide film 2 described above. According to this embodiment, the N ⁺ diffusion layer 5,
Since the formation of the insulating projections 8 made of SiO ₂ is interposed between the field insulating film 2 on the surface 6, if, even when the element spacing is shortened (reduced field oxide film 2) miniaturization The protruding metal silicide layer 9 is blocked by the insulating protrusion 8. This can prevent a short circuit between adjacent elements.

Next, a semiconductor device according to another embodiment of the present invention will be described with reference to FIG. The same elements as those in FIG. 1 are designated by the same reference numerals. In this embodiment, as the insulating protrusion formed on the surface of the field oxide film 2, the same polysilicon as the electrode material of the gate electrode 4 is used. That is, the polysilicon layer 4A formed on the surface of the field oxide film 2 and the polysilicon layer 4
An insulating projection 7A that covers A forms an insulating projection 8A (second projection).

A method of manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. First, similar to the above embodiment,
After the field oxide film 2 is formed in the element isolation region of the P-type silicon substrate 1 by the LOCOS method (FIG. 5A), the gate oxide film 3 is formed, and the polysincone layer is further formed on the entire surface. Then, a pattern for forming the polysilicon layer 4A of the insulating protrusion 8A and the gate electrode 4 is formed on the surface of the polysinccon layer by using a lithography technique. Next, using this pattern as a mask, the polycincon layer is etched to form the polysilicon layer 4A and the gate electrode 4 (FIG. 5B).

Thereafter, similarly to the above-mentioned embodiment, the gate oxide film 5 is selectively etched to diffuse N ⁺ into the surface side of the P-type silicon substrate 1 to form N ⁺ diffusion layers 5 and 6. Then, after forming the oxide film 7 on the entire surface, a photoresist is further applied and exposed and developed to form a resist pattern (FIG. 5C). Further, the oxide film 7 is etched using the resist pattern as a mask to form a shape in which the polysilicon layer 4A on the surface of the field oxide film 2 is covered with the oxide film 7 and the insulating protrusion 8A (film thickness: 100 to 2).
(About 00 nm) and the gate electrode 4 is covered with the oxide film 7 (FIG. 6D).

After that, in the same manner as in the above embodiment, the T
After i (titanium) is vacuum-deposited to form a titanium metal layer 9a (FIG. 6E), annealing is performed to selectively remove unreacted metal to form the metal silicide layer 9 (FIG. 6). (F)), the semiconductor device having the configuration shown in FIG. 4 is obtained. Various modifications are possible without being limited to the above-mentioned embodiment of the present invention.

For example, in the above embodiment, N channel MOS
Although the example of the type transistor has been described, it may be a P-channel MOS type transistor. In the above embodiment has formed the metal silicide layer of TiSi ₂ in view of the advantage of the reaction temperature, for example, Pt (platinum) or by using Co (cobalt), metal silicide PtSi and CoSi ₂ You may make it form a layer.

[0025]

As described above, according to the semiconductor device of the present invention, an insulating protrusion that prevents a short circuit of the metal silicide layer is formed on the surface of the field insulating film sandwiched between the first and second diffusion layers. Since the metal silicide layer is formed, the metal silicide layer overhanging on the surface of the field insulating film is blocked by the insulating protrusion, so that a short circuit between the metal silicide layers can be prevented between the respective elements.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process diagram (1) showing the method for manufacturing the semiconductor device of FIG.

FIG. 3 is a process diagram (2) showing the method for manufacturing the semiconductor device of FIG. 1;

FIG. 4 is a sectional view showing a semiconductor device according to another embodiment of the present invention.

FIG. 5 is a process diagram (1) showing the method for manufacturing the semiconductor device of FIG. 4;

FIG. 6 is a process diagram (2) showing the method for manufacturing the semiconductor device of FIG. 4;

FIG. 7 is a cross-sectional view showing a configuration of a conventional semiconductor device.

FIG. 8 is a process diagram (1) showing the method for manufacturing the semiconductor device of FIG. 7;

FIG. 9 is a process diagram (2) showing the method for manufacturing the semiconductor device in FIG. 7;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate 2 ... Field oxide film 3 ... Gate oxide film 4 ... Gate electrode 4A ... Polysilicon layer 5, 6 ... N ⁺ diffusion layer 7 ... Insulating film 7a ... Resist 8 ... 1st protrusion 8A ... 2 protrusions 9 ... Metal silicide layer 9a ... Titanium metal layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/336 H01L 29/78 301 P

Claims (3)

[Claims] 1. A first and second diffusion layer formed on the front surface side of the silicon substrate with a field insulating film formed in an element isolation region of the silicon substrate interposed therebetween, and the first and second diffusion layers. In a semiconductor device having a metal silicide layer formed by siliciding the surface of the metal silicide layer, a short circuit of the metal silicide layer is prevented on the surface of the field insulating film sandwiched between the first and second diffusion layers. A semiconductor device having an insulating protrusion. 2. The semiconductor device according to claim 1, wherein the insulating protrusion is composed of a SiO ₂ layer. 3. The semiconductor device according to claim 1, wherein the insulating protrusions are made of the same material as the constituent material of the gate electrodes provided near the first and second diffusion layers. A semiconductor device characterized in that.