JPH10284617A - Semiconductor device and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having n-type and p-type transistors with gate electrodes capable of being made with the same low resistance, and a method for manufacturing the semiconductor device. SOLUTION: Upon the formation of the semiconductor device, a polysilicon film 25 is deposited on a device isolation region 23 and a gate oxide film, and boron ions are implanted into a p-type transistor region 26, while arsenic ions are implanted into an n-type transistor region 29. A conductive diffusion preventing film 31 of TiN is formed, and a conductive p-type polysilicon film 32 is formed on the conductive antidiffusion film 31. The polysilicon/TiN/p-type polysilicon deposited film is patterned into gate electrodes 33. Sidewalls 36 are formed on the side surfaces of the gate electrodes 33, and a titanium film is deposited. First heat processing is performed to form a silicide contact between a p-type polysilicon layer 32 of sources/drains and the gate electrodes 33, and the titanium film. Then, unreactive titanium is selectively removed, and second heat processing is performed, to obtain a low-resistant titanium silicide film 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a dual gate type CMOS semiconductor device having a gate electrode having a silicide and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in a CMOS semiconductor device,
As the gate electrodes of the p-type transistor and the n-type transistor, both n-type polysilicon gate electrodes are used. In this case, the n-type transistor has a surface channel, and the p-type transistor has a buried channel type.
Each was used.

However, with the miniaturization of CMOS semiconductors, it has become difficult to suppress the short channel effect in the buried channel type.

Therefore, in order to make the p-type transistor not the buried channel type but the surface channel type, the gate of the p-type transistor must be formed in the same manner as when the n-type polysilicon gate electrode is used as the gate electrode of the n-type transistor. It is necessary to adopt a so-called dual gate structure using a p-type polysilicon gate electrode as the electrode. As a result, the p-type region and the n-type region are mixed in the gate electrode of the same polysilicon layer.

On the other hand, since the polysilicon layer has a relatively high sheet resistance as compared with the metal layer, a high-melting-point metal silicide layer is formed on the polysilicon layer to reduce the resistance of the gate electrode. Must be realized.

Therefore, conventionally, a polycide gate structure has been used to reduce the resistance of the gate electrode (JP-A-1-265542, JP-A-2-183565).
JP-A-2-192161).

In such a conventional semiconductor device in which a p-type region and an n-type region coexist in the same polysilicon layer serving as a gate electrode, in each case, the distance between the polysilicon layer and the refractory metal silicide thereon is high. Is provided with a conductive layer (TiN or the like) serving as a barrier layer for preventing diffusion of impurities.

[0008]

However, Japanese Patent Application Laid-Open Nos. 1-265542 and 2-183 disclose such a method.
In the semiconductor device described in Japanese Patent Application Laid-Open No. 565-565 and Japanese Patent Application Laid-Open No. 2-192161, a process using a polycide gate as a gate electrode is premised, and as shown in FIGS. There is a problem that it cannot cope with a salicide process using titanium silicide.

That is, in the conventional semiconductor device,
First, as shown in FIG.
After that, an n-well 2 is formed, and then an element region and an element isolation region 3 are formed by a field oxide film. A gate oxide film 4 is formed in this element region by thermal oxidation to a thickness of 6 nm, and a polysilicon film 5 is formed on the element isolation region 3 and the gate oxide film 4 by 2 nm.
Deposit 00 nm.

Next, as shown in FIG. 11, a resist pattern 6 having an opening in the p-type transistor region is formed by lithography, and using this as a mask, boron 7 is formed on the polysilicon film 5 in the p-type transistor region. Ion implantation is performed at an acceleration voltage of 10 keV, an implantation amount of 2E15 / cm @ 2.

After removing the resist pattern 6, as shown in FIG. 12, a resist pattern 8 having an opening in the n-type transistor region is formed by lithography, and the resist Arsenic 9 is ion-implanted into the silicon film 5 at an acceleration voltage of 50 keV and an implantation amount of 2E15 / cm2.

Next, as shown in FIG. 13, a polysilicon / T layer is formed by a lithography technique and a reactive etching method.
The gate electrode 10 is formed by patterning the laminated film of iN / polysilicon. The LDD structure (Lightly
Ion implantation for forming a Doped Drain Structure (low-concentration diffusion drain structure) is performed to form an n-type low-concentration impurity region 11 and a p-type low-concentration impurity region 12.

Further, as shown in FIG. 14, a silicon oxide film is formed on the entire surface by LPCVD (Low Pressure Chemical Vapor Deposition).
r Deposition: low-pressure CVD), and a silicon oxide film formed by anisotropic dry etching is etched back to form a gate electrode 1
A sidewall 13 is formed on the side surface of the zero.

Then, as shown in FIG. 15, ion implantation for source / drain formation is performed to form an n-type high-concentration impurity region 14 and a p-type high-concentration impurity region 15, and after heat treatment for activation, A 30 nm titanium film 16 is deposited on the entire surface.

Next, as shown in FIG. 16, annealing at 675 ° C. for 10 seconds, which is the first heat treatment, is performed to
The silicide is formed at a place where the drain and gate electrodes 10 are in contact with the titanium film 16 to form a silicide film 17. Thereafter, the unreacted titanium 16 on the field oxide film and the sidewalls 13 is removed by selective etching, and then annealing is performed at 800 ° C. for 10 seconds, which is a second heat treatment, to lower the resistance of the silicide film 17. I do.

There is also a problem in the case of a salicide process using titanium silicide. That is, since titanium silicide is formed on the polysilicon by using the salicide process, the p-type polysilicon region and the n-type polysilicon region are mixed in the underlying polysilicon gate electrode, and a difference occurs in silicide formation. There was a problem. For example, the sheet resistance of a gate electrode formed by depositing a 30-nm titanium film and performing a salicide process is 4 [ohm / square] for the underlying p-type polysilicon.
On the other hand, in the base n-type polysilicon, 30
[Ohm / square]. As described above, there is a problem that silicidation on n-type polysilicon is suppressed, and a sufficiently low resistance cannot be obtained as compared with the underlying p-type polysilicon.

Therefore, according to the first aspect of the present invention, there is provided a semiconductor device in which a p-type region and an n-type region are mixed in the same polysilicon layer serving as a gate electrode. The impurity diffusion preventing layer, the conductive polysilicon layer and the silicide layer are sequentially formed to prevent the mutual diffusion of impurities between the upper conductive polysilicon layer and the lower polysilicon layer. It is an object of the present invention to provide a semiconductor device which can cope with a salicide process using titanium silicide and can reduce the resistance of the gate electrodes of both an n-type transistor and a p-type transistor to the same extent. .

According to a second aspect of the present invention, the conductive polysilicon layer is a p-type polysilicon layer, so that the upper conductive polysilicon layer of both the p-type transistor and the n-type transistor becomes a p-type polysilicon layer. It is another object of the present invention to provide a semiconductor device which is uniformly silicidized to have a low resistance and which can further reduce the gate electrodes of both n-type and p-type transistors to the same extent.

According to a third aspect of the present invention, after a gate oxide film is deposited on a semiconductor substrate, a polysilicon layer is formed immediately above the gate oxide film, and the polysilicon layer is formed as a p-type MOS transistor region of the polysilicon layer. A p-type impurity is selectively introduced into a polysilicon region to be an n-type MOS transistor region, and an n-type impurity is selectively introduced into a polysilicon region. A conductive impurity diffusion preventing layer is deposited on the polysilicon layer. By forming a conductive polysilicon layer on the diffusion preventing layer and forming a silicide layer on the conductive polysilicon layer, mutual diffusion of impurities between the upper conductive polysilicon layer and the lower polysilicon layer is performed. Can be prevented by a conductive impurity diffusion preventing layer, a salicide process using titanium silicide can be supported, and the gate width of both the n-type transistor and the p-type transistor can be reduced. And its object is to provide a method of manufacturing a semiconductor device capable of reducing the resistance of the gate electrode to the same extent.

According to a fourth aspect of the present invention, the p-type polysilicon layer is formed as the conductive polysilicon layer, so that the upper conductive polysilicon layer of both the p-type transistor and the n-type transistor is a p-type polysilicon layer. It is an object of the present invention to provide a method of manufacturing a semiconductor device in which silicide is uniformly reduced to a low resistance and the gate electrodes of both an n-type transistor and a p-type transistor can be further reduced to the same level.

[0021]

According to a first aspect of the present invention, there is provided a semiconductor device in which a p-type region and an n-type region are mixed in the same polysilicon layer serving as a gate electrode.
At least on the polysilicon layer serving as the gate electrode,
The above object is achieved by sequentially forming the conductive impurity diffusion preventing layer, the conductive polysilicon layer and the silicide layer.

According to the above configuration, conductive impurity diffusion prevention is performed on at least the polysilicon layer serving as the gate electrode of a semiconductor device in which the p-type region and the n-type region are mixed in the same polysilicon layer serving as the gate electrode. Since the layer, the conductive polysilicon layer and the silicide layer are sequentially formed, mutual diffusion of impurities between the upper conductive polysilicon layer and the lower polysilicon layer is prevented by the conductive impurity diffusion preventing layer. Accordingly, it is possible to cope with a salicide process using titanium silicide, and it is possible to reduce the resistance of the gate electrodes of both the n-type transistor and the p-type transistor to the same extent.

In this case, for example, the conductive polysilicon layer may be a p-type polysilicon layer.

According to the above configuration, since the conductive polysilicon layer is a p-type polysilicon layer, the upper conductive polysilicon layer of both the p-type transistor and the n-type transistor becomes a p-type polysilicon layer, and Therefore, the gate electrode of both the n-type transistor and the p-type transistor can be further reduced in resistance to the same extent.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a p-type region and an n-type region are mixed in the same polysilicon layer serving as a gate electrode. After depositing an oxide film, a polysilicon layer forming step of forming a polysilicon layer immediately above the oxide film, and a p-type impurity for selectively introducing a p-type impurity into a polysilicon region of the polysilicon layer to be a p-type MOS transistor region. Type impurity introducing step and n-type M
An n-type impurity introducing step of selectively introducing an n-type impurity into a polysilicon region to be an OS transistor region; an impurity diffusion preventing layer forming step of depositing a conductive impurity diffusion preventing layer on the polysilicon layer; A conductive polysilicon layer forming step of forming a conductive polysilicon layer on the conductive impurity diffusion preventing layer, and a silicide layer forming step of forming a silicide layer on the conductive polysilicon layer, by sequentially performing The above objective has been achieved.

According to the above structure, after depositing a gate oxide film on a semiconductor substrate, a polysilicon layer is formed immediately above the gate oxide film, and selectively formed in a polysilicon region of the polysilicon layer which is to be a p-type MOS transistor region. n-type MO
An n-type impurity is selectively introduced into a polysilicon region to be an S transistor region, a conductive impurity diffusion preventing layer is deposited on the polysilicon layer, and a conductive polysilicon is deposited on the conductive impurity diffusion preventing layer. Since a layer is formed and a silicide layer is formed on the conductive polysilicon layer, mutual diffusion of impurities between the upper conductive polysilicon layer and the lower polysilicon layer is prevented by a conductive impurity diffusion preventing layer. In addition to being able to cope with a salicide process using titanium silicide, the gate electrodes of both the n-type transistor and the p-type transistor can be reduced in resistance to the same extent.

In this case, for example, in the conductive polysilicon layer forming step, a p-type polysilicon layer may be formed as the conductive polysilicon layer.

According to the above configuration, since the p-type polysilicon layer is formed as the conductive polysilicon layer, the upper conductive polysilicon layer becomes the p-type polysilicon layer for both the p-type transistor and the n-type transistor. Therefore, silicidation can be uniformly performed to have a low resistance, and the gate electrodes of both the n-type transistor and the p-type transistor can be further reduced in resistance to the same extent.

[0029]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. It should be noted that the embodiments described below are preferred embodiments of the present invention, and therefore, various technically preferable limitations are added. However, the scope of the present invention is not limited to the following description. The embodiments are not limited to these embodiments unless otherwise specified.

FIGS. 1 to 9 are views showing one embodiment of a semiconductor device and a method of manufacturing the semiconductor device according to the present invention. In this embodiment, gate electrodes of a p-type transistor and an n-type transistor are used. forming a TiN layer for preventing diffusion of impurities on the p-type polysilicon and the n-type polysilicon,
Manufacturing a semiconductor device and a semiconductor device in which both a p-type transistor and an n-type transistor can have the same low resistance by forming a p-type polysilicon layer uniformly thereon and forming silicide thereon. The method is shown.

The semiconductor device according to the present embodiment first has a structure shown in FIG.
As shown in FIG. 1, a p-well (p-type region) 21 and an n-well (n-type region) 22 are formed on a silicon substrate (not shown), and an element region and an element isolation region 23 are formed by a field oxide film. A gate oxide film 24 is formed on the element region by thermal oxidation.
Is formed to a thickness of 6 nm, and a polysilicon layer 25 is deposited on the device isolation region 23 and the gate oxide film 24 to form a polysilicon layer 25 of 200 nm.

Next, as shown in FIG. 2, a resist pattern 27 having an opening in the p-type transistor region 26 is formed by lithography, and boron is ion-implanted into the polysilicon film 25 using the resist pattern 27 as a mask. A p-type impurity introduction step of introducing a p-type impurity is performed. The acceleration voltage in this ion implantation is 10 keV, and the implantation amount is 2E15 / cm2.

Then, as shown in FIG. 3, after removing the resist pattern 27, a resist pattern 30 having an opening in the n-type transistor region 29 is formed by lithography, and the polysilicon film 25 is formed using the resist pattern 30 as a mask. An arsenic 41 is ion-implanted to perform an n-type impurity introduction step of introducing an n-type impurity. The acceleration voltage in this ion implantation is 50 keV, and the implantation amount is 2E15
/ Cm2.

Next, as shown in FIG. 4, after the resist pattern 30 is removed, TiN is removed by sputtering.
Is formed as a conductive diffusion prevention film 31 to a thickness of 10 nm.

Then, as shown in FIG. 4, a conductive p-type impurity doped with boron, which is a p-type impurity implanted in the p-type impurity introducing step, is deposited immediately above the diffusion preventing film 31 which is a TiN film. A conductive polysilicon layer forming step of depositing and forming the mold polysilicon film 32 to a thickness of at least 30 nm is performed.

Next, as shown in FIG. 5, polysilicon 25 / T is formed by a lithography technique and a reactive etching method.
The deposited film of iN31 / p-type polysilicon 32 is patterned to form a gate electrode 33, and an LDD structure (Lightl
y Doped Drain Structure: Low concentration diffusion drain structure
Is performed to form a p-type low-concentration impurity region 34 and an n-type impurity region 35.

Further, a silicon oxide film is formed on the entire upper surface by LP.
As shown in FIG. 6, a film is formed to a thickness of 150 nm by a CVD (Low Pressure Chemical Vapor Deposition) method, and the silicon oxide film is etched back by an anisotropic dry etching method. Next, a sidewall 36 is formed on the side surface of the gate electrode 33.

Next, as shown in FIG. 7, ion implantation for forming a source / drain is performed, and a heat treatment for activation is performed to form a p-type high-concentration impurity region 37 and an n-type high-concentration impurity region. After forming 38, a titanium film 39 is deposited on the entire upper surface to a thickness of 30 nm.

Then, as shown in FIG. 8, annealing is performed at 675 ° C., which is the first heat treatment, for 10 seconds, so that the p-type polysilicon layer 32 of the source / drain and gate electrodes 33 and the titanium film 39 come into contact with each other. Where it is silicidated. Thereafter, the unreacted titanium on the field oxide film and the sidewalls is removed by selective etching, and then annealing is performed at 800 ° C. for 10 seconds, which is the second heat treatment, to lower the resistance of the titanium silicide film 40.

As described above, according to the semiconductor device of this embodiment and the method of manufacturing the semiconductor device, the p-type region (p-well) is formed in the same polysilicon layer 25 serving as the gate electrode 33.
Polysilicon layer 25 serving as at least gate electrode 33 of a semiconductor device in which 21 and n-type region (n-well) 22 coexist
Since a conductive impurity diffusion preventing layer 31, a conductive polysilicon layer (p-type polysilicon film) 32, and a silicide layer (titanium silicide film) 40 are sequentially formed thereon,
Inter-diffusion of impurities between the upper conductive polysilicon layer 32 and the lower polysilicon layer 25 can be prevented by the conductive impurity diffusion preventing layer 31, which also supports a salicide process using titanium silicide. And the n-type transistor 29 and the p-type transistor 26
The resistance of both gate electrodes can be reduced to the same extent.

That is, between the lower p-type polysilicon layer 25 and the n-type polysilicon layer 25, which determine the work function, and the upper p-type polysilicon film 32, a conductive film of a TiN film for preventing diffusion of impurities is formed. , The diffusion of impurities between the upper polysilicon layer 25 and the lower polysilicon film 32 does not occur. Therefore, it does not affect the work function of the gate electrode 33, and thus the threshold voltage of the device.

Further, by the first heat treatment after the formation of the titanium film 39, the titanium film 39 is silicided where the p-type polysilicon layer 32 of the source / drain and gate electrodes 33 is in contact with the titanium film 39. At this time, the gate electrode 33
On top, a p-type polysilicon layer 32 is at least 30 nm.
Since it is formed, the deposited 30 nm titanium film 3
9 can be sufficiently silicided. Further, the uppermost part of the gate electrode 33 is connected to the n-type transistor 29 and the p-type transistor 29.
Since both the type transistors 26 are p-type polysilicon layers, they can be uniformly silicified to have a low resistance.

For example, when the p-type polysilicon film 32 is used as the conductive polysilicon film as in the above embodiment, as shown in FIG. 9, the conventional example has a resistance value of p-type transistor and n-type transistor. In contrast, the p-type transistor and the n-type transistor can reduce the resistance substantially equally, and compared with the reference example using the n-type polysilicon film as the conductive polysilicon film. As a result, the resistance can be significantly reduced. That is, in the conventional example, 4 [ohm / square] is used for the p-type transistor.
re], n-type transistor and 30 [ohm / square]
On the other hand, in the reference example using an n-type polysilicon film as the conductive polysilicon film as the conductive polysilicon film, both the p-type transistor and the n-type transistor have 30 [ohm / square]. And p
The type transistor and the n-type transistor had similar resistance values. Further, in the semiconductor device of this embodiment using the p-type polysilicon film as the conductive polysilicon film, both the p-type transistor and the n-type transistor have 4 [ohms].
/ Square], the p-type transistor and the n-type transistor have the same value, and the resistance value is significantly reduced.

As described above, the invention made by the inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to the above, and various modifications can be made without departing from the gist of the invention. It goes without saying that it is possible.

[0045]

According to the semiconductor device of the first aspect of the present invention, at least the polysilicon layer serving as the gate electrode of a semiconductor device in which the p-type region and the n-type region are mixed in the same polysilicon layer serving as the gate electrode Since a conductive impurity diffusion preventing layer, a conductive polysilicon layer, and a silicide layer are sequentially formed thereon, mutual diffusion of impurities between the upper conductive polysilicon layer and the lower polysilicon layer is performed. And a salicide process using titanium silicide, and the gate electrodes of both the n-type transistor and the p-type transistor can be similarly reduced in resistance. it can.

According to the second aspect of the present invention, since the conductive polysilicon layer is a p-type polysilicon layer, the upper conductive polysilicon layer of both the p-type transistor and the n-type transistor is p-type. It becomes a polysilicon layer and can be uniformly silicidized to have a low resistance, so that the gate electrodes of both the n-type transistor and the p-type transistor can have a further lower resistance.

According to a third aspect of the present invention, after a gate oxide film is deposited on a semiconductor substrate, a polysilicon layer is formed immediately above the gate oxide film, and the p-type MOS transistor of the polysilicon layer is formed. A p-type impurity is selectively introduced into a polysilicon region serving as a region, and an n-type impurity is selectively introduced into a polysilicon region serving as an n-type MOS transistor region. Is deposited, a conductive polysilicon layer is formed on the conductive impurity diffusion preventing layer, and a silicide layer is formed on the conductive polysilicon layer, so that the upper conductive polysilicon layer and the lower polysilicon Inter-diffusion of impurities between the layers can be prevented by the conductive impurity diffusion preventing layer, and it is possible to cope with a salicide process using titanium silicide. Together, n-type transistor and the p
The gate electrodes of both the type transistors can be reduced in resistance to the same extent.

According to the method of manufacturing a semiconductor device of the present invention, since the p-type polysilicon layer is formed as the conductive polysilicon layer, both the p-type transistor and the n-type transistor have an upper conductive layer. The polysilicon layer becomes a p-type polysilicon layer, can be uniformly silicified to have a low resistance, and the gate electrodes of both the n-type transistor and the p-type transistor can have a further lower resistance.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device to which an embodiment of a semiconductor device and a method of manufacturing the semiconductor device according to the present invention are applied. FIG. 3 is a front sectional view of a state where a film is formed.

FIG. 2 is a front sectional view showing a state where p-type impurities are introduced into the semiconductor device of FIG. 1;

FIG. 3 is a front sectional view showing a state where n-type impurities are introduced into the semiconductor device of FIG. 2;

FIG. 4 is a front sectional view showing a state where a conductive polysilicon layer is formed after forming an impurity diffusion film in the semiconductor device of FIG. 3;

FIG. 5 shows a state after forming a gate electrode on the semiconductor device of FIG. 4;
FIG. 4 is a front sectional view showing a state where a low-concentration impurity region is formed.

FIG. 6 is a front sectional view of the semiconductor device of FIG. 5 in a state where sidewalls are formed on a gate electrode.

FIG. 7 is a front sectional view showing a state where a titanium film is formed after a high-concentration impurity region is formed in the semiconductor device of FIG. 6;

8 is a front cross-sectional view showing a state where the resistance of a titanium silicide film is reduced after silicidation of the semiconductor device of FIG. 7;

9 is a diagram showing a comparison between sheet resistances of gate electrodes of a conventional example, the semiconductor device of the embodiment of FIG. 1, and a reference example.

FIG. 10 is a front sectional view showing a state in which a field oxide film is used to form an element region and an element isolation region on a p-well and an n-well of a conventional semiconductor device, and then a polysilicon film is formed.

11 is a front sectional view showing a state where p-type impurities are introduced into the semiconductor device of FIG. 10;

FIG. 12 is a front sectional view showing a state where n-type impurities are introduced into the semiconductor device of FIG. 11;

13 is a front sectional view showing a state where a low concentration impurity region is formed after forming a gate electrode in the semiconductor device of FIG. 12;

14 is a front sectional view of the semiconductor device of FIG. 13 in a state where a sidewall is formed in a gate electrode.

FIG. 15 is a front sectional view showing a state where a titanium film is formed after forming a high-concentration impurity region in the semiconductor device of FIG. 14;

FIG. 16 shows a semiconductor device of FIG. 15 after silicidation;
FIG. 4 is a front sectional view of a state where the resistance of the silicide film is reduced.

[Explanation of symbols]

 21 p-well 22 n-well 23 element isolation region 24 gate oxide film 25 polysilicon film 26 p-type transistor region 27 resist pattern 28 boron 29 n-type transistor region 30 resist pattern 31 diffusion prevention film 32 p-type polysilicon film 33 gate electrode 34 p-type low concentration impurity region 35 n-type impurity region 36 sidewall 37 p-type high concentration impurity region 38 n-type high concentration impurity region 39 titanium film 40 titanium silicide film 41 arsenic

Claims (4)

[Claims] In a semiconductor device in which a p-type region and an n-type region are mixed in the same polysilicon layer serving as a gate electrode,
At least on the polysilicon layer serving as the gate electrode,
A semiconductor device, comprising: a conductive impurity diffusion preventing layer, a conductive polysilicon layer, and a silicide layer sequentially formed. 2. The semiconductor device according to claim 1, wherein said conductive polysilicon layer is a p-type polysilicon layer. 3. A method for manufacturing a semiconductor device in which a p-type region and an n-type region are mixed in the same polysilicon layer serving as a gate electrode, wherein a gate oxide film is deposited on a semiconductor substrate.
A polysilicon layer forming step of forming a polysilicon layer thereabove, a p-type impurity introducing step of selectively introducing a p-type impurity into a polysilicon region of the polysilicon layer to be a p-type MOS transistor region, An n-type impurity introducing step of selectively introducing an n-type impurity into a polysilicon region to be an n-type MOS transistor region of the polysilicon layer;
An impurity diffusion preventing layer forming step of depositing a conductive impurity diffusion preventing layer on the polysilicon layer; and a conductive polysilicon layer forming step of forming a conductive polysilicon layer on the conductive impurity diffusion preventing layer. A method of forming a silicide layer on the conductive polysilicon layer, and a silicide layer forming step of forming a silicide layer on the conductive polysilicon layer. 4. The method according to claim 3, wherein said conductive polysilicon layer forming step includes forming a p-type polysilicon layer as said conductive polysilicon layer.