JPH07263456A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device, in particular, a bipolar transistor of high withstand voltage which is excellent in high frequency characteristics. CONSTITUTION:In a semiconductor device, in particular, a lateral, type bi,polar transistor device, a gap is formed between the high concentration part of a second N-base layer of high impurity concentration for supplying a base current and the high concentration part of a second P-collector layer 6 of low impurities. Thereby contact is evaded, so that the concentration of the P-collector layer of low concentration can be made high without deteriorating the withstand voltage, and the collector resistance can be lowered. The voltage between an emitter and a base at the time of transistor operation can be decreased, and current capacity can be improved. Hence high frequency and large current operation of a transistor is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device,
Particularly, it relates to a bipolar transistor having a high breakdown voltage and a high speed.

[0002]

2. Description of the Related Art In general, power ICs, LSIs, signal transistors, etc. require bipolar transistors of high breakdown voltage, high current amplification factor, and high speed. However, it is difficult to realize these characteristics at the same time. Conventionally, in order to achieve a high current amplification factor, the base is thinned to sacrifice the breakdown voltage, or the Darlington transistor configuration is used to sacrifice the speed. The method is used.

For example, in a bipolar linear IC, an npn transistor and a pnp transistor are mixed in order to increase the degree of freedom in circuit design and to simplify the circuit configuration, but in order to reduce the number of manufacturing steps. The npn transistor has a vertical structure and the pnp transistor has a lateral structure. In this case, the influence of not being able to simultaneously realize a bipolar transistor having a high breakdown voltage, a high current amplification factor, and a high speed is serious. This is because in the lateral pnp transistor, the collector junction breakdown voltage is achieved by spreading the depletion layer in the base (semiconductor substrate region) having a low concentration, but in order to prevent the so-called punch-through phenomenon in which the depletion layer reaches the emitter junction, The distance between the emitter and collector (base width) is designed to be wider than the depletion layer width at the design breakdown voltage of the collector junction. As a result, the current amplification factor is significantly lower than that of the vertical transistor.

Various element structures have been proposed to solve the problem of the lateral type transistor. As an example, a pnp transistor disclosed in JP-A-59-127865 is known. This transistor has an n base region having a higher impurity concentration than the base region on one main surface side of the n type base region, ap emitter region in the n base region, and a first p region in the base region distant from the n base region.
A collector region, a first collector region extending from the first p collector region toward the n base region and surrounding the n base region, and a second impurity region having a lower impurity concentration than the n base region.
The p collector region is formed. According to this structure, when the low voltage is applied, the second collector region becomes the collector, and when the high voltage is applied, the depletion layer spreads in the second collector region, and the first collector region becomes the collector. As a result, the current amplification factor and the cutoff frequency are increased. And the withstand voltage can be improved together.

However, in this structure, the consideration of the base resistance is not taken into consideration, and there is a problem that the noise voltage becomes large due to the large base resistance when used in a linear IC. To solve it, Japanese Patent Application 1-
The structure disclosed in 268959 is known. This structure releases a part of the first collector region surrounding the n base region of the pnp transistor disclosed in the above-mentioned Japanese Patent Laid-Open No. 59-127865, and uses that part as a high impurity concentration n base. The second collector layer is connected to the second high impurity concentration base layer for the base electrode outside the collector region. According to this, the base resistance can be reduced, and as a result, a pnp transistor with a low noise voltage can be formed.

High breakdown voltage, which is one of the typical representative problems
A lateral pnp transistor of a high-speed linear IC will be described as an example. High breakdown voltage and higher speed linear circuit (I
7 and 8 are plan views and cross-sectional views of the lateral pnp transistor disclosed in Japanese Patent Application No. 1-268959 in order to realize C). In order to improve the cutoff frequency, the p-emitter 3 and the p-collector 6 which are effective operating regions
If the width of the n base layer 2 between them is remarkably narrowed, the contribution of the base resistance and the collector resistance to the cutoff frequency becomes large, and it is necessary to reduce them.

On the other hand, when the breakdown voltage is increased, the length of the second collector region 6 which is the distance between the n base 2 and the first p collector region 4, which acts as an electric field relaxation region, becomes large, and as a result, the collector resistance is increased. Increase. Further, the distance of the second n-base 5 pulled out from the n-base 2 also becomes long, resulting in an increase in base resistance. In order to reduce the resistance, if the base impurity concentration of the extraction portion is made higher than that of the first n-base 2, the impurity of the second p-collector region 6 and the second n-base 5 is applied when the reverse bias of the transistor is applied. Electrolytic concentration is severe at the contact portion of, and the breakdown voltage is lowered.
In order to prevent the reduction of the breakdown voltage, it is necessary to reduce the impurity concentration of the second collector region 6, and as a result, the collector resistance increases and the cutoff frequency decreases.

On the other hand, in this transistor, when the emitter 3 is lengthened on the side opposite to the second n base layer 5 in order to increase the current capacity, the relation between the first n base 2 and the p emitter 3 is current amplified. Since it is determined by the rate specification,
The base resistance from the second n-base 5 end to the emitter 3 end is large, and as a result, the emitter-base voltage decreases from the second n-base 5 direction to the opposite side during high current operation, and the emitter-base voltage decreases. This non-uniformity of the base-to-base voltage causes a decrease in current amplification factor, cutoff frequency, and noise voltage in the high current region.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a high withstand voltage and a high frequency characteristic, particularly a bipolar transistor, which has an excellent noise characteristic without sacrificing the withstand voltage.

[0010]

In order to solve the above problems, according to the present invention, a first semiconductor region of one conductivity type and a first semiconductor region extending inward from one main surface of the first semiconductor region are provided. A second conductivity type second semiconductor region having a higher impurity content, a third conductivity type third semiconductor region extending inward from an exposed surface of the second semiconductor region and having a higher impurity content than the second semiconductor region, The first semiconductor region has an annular shape that extends inward from one main surface and has an exposed surface that is open and substantially surrounds the second semiconductor region, and has a higher impurity concentration than the first semiconductor region. 4 semiconductor region and the first semiconductor region from one main surface to the inside, one end of which is connected to the second semiconductor region and the other end of which extends from the open portion of the fourth semiconductor region to the second semiconductor region. First to extend away
Located between the second semiconductor region and the fourth semiconductor region, and one conductive type fifth semiconductor region having a higher impurity concentration than the second semiconductor region and the second semiconductor region, and contacting both regions. , On the outer peripheral side of the fifth semiconductor region portion, in the void, extending inward from one main surface of the first semiconductor region and having a higher impurity concentration than the first semiconductor region and a lower impurity concentration than the fourth semiconductor region, A conductive type sixth semiconductor region, and an exposed surface of the third semiconductor region which is covered with the second semiconductor region and at least a part of the sixth semiconductor region via an insulator formed on the main surface. A first electrode in ohmic contact with the first opening, and a second electrode in ohmic contact with the second opening that is an exposed surface of the fourth semiconductor region,
A third semiconductor device is provided with a third electrode that makes ohmic contact with a third opening that is an exposed surface of the fifth semiconductor region.

In the above semiconductor device, the third semiconductor region may have an ohmic contact in which the first opening in the exposed surface is biased far away from the fifth semiconductor region, and the fourth semiconductor region. The shape may be such that at least a part of the portion that does not face the region is removed. In the semiconductor device, on the side of the main surface facing the fourth semiconductor region, at least smaller than the second semiconductor region, extending inward from one main surface of the first semiconductor region, the second semiconductor region is formed. It is also possible to have a seventh semiconductor region that is deeper and has a lower impurity than the third semiconductor region, while having a conductivity type seventh semiconductor region. Further, in the semiconductor device, the first semiconductor region may be one of a plurality of island regions provided on one main surface side of the semiconductor substrate so as to be electrically insulated from each other.

As described above, according to the present invention, the semiconductor device,
Especially in lateral bipolar transistor devices,
Contact between the high-concentration portion of the second n base layer, which is the fifth semiconductor region having a high impurity concentration for supplying the base current, and the high-concentration portion of the second p collector layer, which is the sixth semiconductor region having a low impurity concentration, is performed. By avoiding this, when applying a reverse bias to this transistor, the electric field at this junction can be relaxed, resulting in
The breakdown voltage can be prevented from lowering. Therefore, it is possible to prevent the cutoff frequency from decreasing without decreasing the impurity concentration of the second collector layer that is the sixth semiconductor region, that is, without increasing the collector resistance.

Further, when the length of the p-emitter region which is the third semiconductor region is increased to increase the current capacity, the distance from the second base region which is the fifth semiconductor region increases.
The first n base region, which is the second semiconductor region, becomes high resistance by being pinched by the emitter region, which is the third semiconductor region, and the current in the high current region is increased due to bias of the emitter current during transistor operation. The gain and cutoff frequency are significantly reduced. Therefore, the first semiconductor which is the second semiconductor region
In order to reduce the resistance of the base region of the transistor, as one means, the bottom of the p-type emitter region, which is the third semiconductor region other than the effective base region of this transistor, is the impurity of the seventh semiconductor region that has a low resistance. By providing a diffusion layer or removing the central portion of the p-type emitter region, which is the third semiconductor region that does not oppose the effective base region, to expose the base diffusion layer, a pinch of the emitter diffusion of the first base diffusion layer is performed. High resistance can be prevented.

Further, in order to increase the cutoff frequency to a high current,
For the purpose of preventing non-uniformity of the emitter-base voltage at the emitter junction far from the base electrode, the first biased first electrode is biased far from the base electrode which is the third electrode in the emitter region which is the third semiconductor region. You may provide the emitter electrode which is an electrode. The semiconductor device of the present invention is a linear IC.
Can be suitably used as the high frequency pnp transistor.

[0015]

According to the present invention, in the high breakdown voltage bipolar transistor, the second base region, which is the fifth semiconductor region, and the p collector region, which is the sixth semiconductor region with low impurities, do not contact each other. In the structure, it is possible to avoid a portion where an electric field is concentrated when a voltage is applied, and thus it is possible to reduce the sheet resistance of the second p collector layer that is the sixth semiconductor region without lowering the breakdown voltage, and as a result, the collector resistance is reduced. The cutoff frequency can be improved. Furthermore, in order to reduce the effect of biasing the emitter at high current, a low impurity layer of the base is provided under the emitter, and the emitter region that is not the effective emitter region is removed, so that the contact position within the emitter is further changed from the base electrode. By arranging them at a distant position, the emitter-base voltage of the emitter junction can be made uniform and the base resistance can be reduced, and the cutoff frequency can be improved even in the high current region.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device of the present invention will be described in detail below with reference to the drawings showing the embodiments. Embodiment 1 FIG. 1 and FIG. 2 respectively show a plan view and a sectional view of a lateral pnp transistor showing a first embodiment of the present invention.
In FIGS. 1 and 2, reference numeral 1 denotes an island-like buried structure in which an n-type buried layer 10 in contact with the insulating film 30 is provided on the polycrystalline silicon 21 to form an island shape. It is a base region which is a first region exposed at 22.

Reference numeral 2 is a base region having n-type conductivity, which is a second region extending inward from a part of one main surface 22 of the base region 1 and having a higher impurity than the base region 1. Three
Is a p-type conductivity type emitter region which is a third region extending inward from the exposed surface of the base region 2 and having a higher impurity concentration than the base region 2. 4 is the main surface 2 of the base region 1
P-type conductivity, which is a fourth region extending inward from the base region 2 and surrounding the n base region 2 at a predetermined distance on the main surface 22 so as to surround the base region 2 and have a part thereof open to have a higher impurity concentration than the base region 1. It is the collector region of the mold.

The reference numeral 5 extends inward from one main surface 22 of the base region 1, one end is connected to the n base region 2 and the other end is extended away from the open part of the collector region 4, and is higher than the base region 2. It is a connecting base region which is a fifth region having a concentration layer. 6 extends inward from the one main surface 22 of the base region 1, and includes an n base region 2 and a collector region 4.
And the connection base region 5 and a part of the substrate 1 appears on the surface between the base region 1 and the connection base region 5 and has a higher impurity concentration than the base region 1 and a lower impurity concentration than the collector region 4. 6 is a p-collector region which is a region of 6.

Reference numeral 31 denotes one main surface 2 of the semiconductor substrate 20.
Reference numeral 41 denotes an insulating film formed on the second insulating film 31, and reference numeral 41 denotes a base electrode which is a third electrode that makes low resistance contact with at least a part of the base region 5 through the opening 51 of the insulating film 31 and serves as a B terminal. 42 has a low resistance contact with at least a part of the emitter region 3 through the opening 52 of the insulating film 31, and faces the collector region 4 via the insulating film 31; the base region 2; the connecting base region 5; and the p-collector region 6. The emitter electrode, which is the first electrode covering a part of the above, becomes the E terminal.

43 has a low resistance contact with at least a part of the collector region 4 through the opening 53 of the insulating film 31 and faces the n base region on the collector region 4 and beyond the collector region through the insulating film 31. Direction p-collector region 6
The collector electrode, which is a third electrode covering a part of the upper part and a part of the base region 1 exposed on the outer peripheral main surface of the collector region, serves as a C terminal. Reference numeral 8 is a polycrystalline silicon thin film for forming the same impurity diffusion window forming the n base region 2 and the emitter region 3, and is buried in the insulating film 31.

Specific examples of each dimension and the like in this embodiment are shown below. The single crystal island 1 has a thickness of 40 μm, and the buried layer 10 has a diffusion concentration and a diffusion depth of 5 × 10 ¹⁸ / cm ³ and 1, respectively.
0 μm, the diffusion concentration and the diffusion depth of the n base region 2 are 2 × 10 ¹⁷ / cm ³ and 2.5 μm, respectively, and the emitter region 3
The diffusion concentration and the diffusion depth are 5 × 10 ¹⁵ / cm ³ respectively.
And 0.5 μm, the diffusion concentration and the diffusion depth of the collector region 4 are 1 × 10 ¹⁸ / cm ³ and 3.5 μm, respectively, and the diffusion concentration and the diffusion depth of the connection base region 5 are 1 × 10 ²⁰ respectively.
/ Cm ³ and 2.0 μm, and the diffusion concentration and the diffusion depth of the p-collector region 6 are 6 × 10 ¹⁵ / cm ³ and 5.0 μm, respectively.
m.

The base region 2 and the connecting base region 5 are also provided.
The distance between the collector region 3 and the collector region 3 is 15 μm.
The distance between the buried layer 10 and the buried layer 10 is 15 μm, and the covering length of the emitter electrode 42 from the base region 2 and the connecting base region 5 in the p-collector region 6 direction is 8 μm. In addition, between the connection base region 5 and the p-collector region 6 is 7 μm between the photomasks.
m. The area of the emitter electrode in contact with the emitter diffusion layer is 3 μm × 3 μm, and the length and width of the emitter are each 15 μm.

According to the present invention, the connecting base region 5 is p-.
Compared with the conventional structure that traverses the collector region 6, the p − concentration can be improved by about 10% without lowering the breakdown voltage. The characteristics of this element are as follows: Collector-emitter breakdown voltage BV _CEO ~ 1
50 V, the current amplification factor 130, the cutoff frequency f _r to 230
Since the frequency is MHz, the collector resistance can be reduced by increasing the concentration of the p-collector region 6, and the cutoff frequency can be improved by about 7%.

Embodiment 2 FIG. 3 shows a lateral pn showing a second embodiment according to the present invention.
It is a top view of a p-transistor. In this structure, the emitter region 3 is elongated in the direction opposite to the connection base region 5 in order to increase the current capacity in the first embodiment of the present invention, and the contact region 52 of the emitter region 3 is further formed.
Are arranged offset in the opposite direction to the connection base region 5. Other configurations are the same as those in the first embodiment.

The contact region 52 of the emitter which is in contact with the emitter region 3 is 3 μm × 3 μm, and the emitter region is 15 μm wide and 50 μm long. Characteristics of the element, the collector - emitter breakdown voltage BV _CEO ~150V, current amplification factor 130, a cut-off frequency f _r ~180MHz, also compared to a transistor contact region 52 is not biased, about 10% current capacity is improved did it.

Embodiment 3 FIG. 4 shows a lateral pn showing a third embodiment according to the present invention.
It is a top view of a p-transistor. In this structure, in the second embodiment of the present invention, in order to increase the current capacity, particularly when the emitter region 3 is elongated in the lateral direction, a collector current is obtained in proportion to the length of the emitter. A part of the emitter portion other than the lateral emitter that effectively operates in opposition to is removed to expose the surface of the base region 2. For configurations other than the emitter shape,
This is the same as the second embodiment.

According to this structure, since the base resistance can be reduced, the emitter-base voltage difference near and far from the base electrode can be reduced, which is advantageous when the emitter length is increased. Characteristics of the element, the collector - emitter breakdown voltage BV _CEO ~150V, the current amplification factor 130, the cutoff frequency f _r ~190MHz, is almost equal to that of Example 2, was the current capacity improved by about 10%.

Embodiment 4 FIGS. 5 and 6 are a plan view and a sectional view of a lateral pnp transistor showing a fourth embodiment according to the present invention. In the structure according to the first embodiment of the present invention, this structure opposes the collector so as to obtain a current proportional to the length of the emitter region 3, particularly when the emitter region 3 is elongated in the lateral direction. The second base region 23, which is a seventh semiconductor region having a low resistance of the n-type base having the same polarity as the base, is formed in the emitter portion other than the lateral emitter, that is, below the emitter.
Is provided. The configuration other than the emitter shape is the same as that of the first embodiment.

The surface concentration and diffusion depth of the second base region 23 are 5 × 10 ¹⁸ / cm ³ and 4 μm, respectively. According to this structure, when the emitter region 3 is long, the base resistance under the emitter is small, so that the emitter-base voltage difference near and far from the base electrode can be reduced, and as a result, when the emitter length is increased. Be advantageous to. The characteristics of this element are that the collector-emitter breakdown voltage BV _CEO ~
150 V, the current amplification factor 130, the cutoff frequency f _r to 15
It was 0 MHz, which was almost the same as that of Example 3, but the current capacity could be improved by about 20%. It should be noted that these embodiments are not limited to the dielectric isolation substrate, and are effective when applied to a pn isolation substrate or the like.

[0030]

According to the semiconductor device of the present invention, the collector resistance can be reduced without lowering the breakdown voltage. As a result,
When the emitter length is increased to increase the current capacity, a current capacity approximately proportional to the current can be obtained, and a high-frequency pnp transistor suitable for a high-frequency linear IC can be provided.

[Brief description of drawings]

FIG. 1 is a plan view showing an example of a semiconductor device of the present invention.

FIG. 2 is a sectional view of FIG.

FIG. 3 is a plan view showing another example of the semiconductor device of the present invention.

FIG. 4 is a plan view showing another example of the semiconductor device of the present invention.

FIG. 5 is a plan view showing another example of the semiconductor device of the present invention.

6 is a sectional view of FIG.

FIG. 7 is a plan view showing a conventional semiconductor device.

FIG. 8 is a sectional view of FIG.

[Explanation of symbols]

1 ... Base region (first region), 2 ... Base region (second region), 3 ... Emitter region (third region), 4 ... Collector region (fourth region), 5 ... High-concentration linked base Region (fifth region), 6 ... Low concentration p collector region (sixth region), 8 ... Poly Si, 10 ... Buried layer, 20 ... Semiconductor substrate, 21 ... Support, 22 ... Main surface, 23 ... Low base resistance region (seventh region), 30, 31 ... Insulating film, 41 ... Base electrode (third electrode), 42 ... Emitter electrode (first electrode), 43 ... Collector electrode (second electrode) ), 51, 5
2, 53 ... Contact, E ... Emitter terminal, B ... Base terminal, C ... Collector terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masamitsu Inaba 7-1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (6)

[Claims] 1. A conductive first semiconductor region and a first conductive region
A second semiconductor region of one conductivity type that extends inward from one main surface of the semiconductor region and has higher impurities than the first semiconductor region, and extends inward from an exposed surface of the second semiconductor region A third semiconductor region of the other conductivity type having a high impurity, and a second semiconductor region which substantially extends from one main surface of the first semiconductor region to the inside and has an open exposed surface, and which substantially surrounds the second semiconductor region, A fourth semiconductor region of the other conductivity type having a higher impurity concentration than that of the first semiconductor region, and a fourth semiconductor region extending inward from one main surface of the first semiconductor region, the one end being connected to the second semiconductor region and the other end being the fourth semiconductor region. A fifth semiconductor region of one conductivity type that extends away from the second semiconductor region through an open part of the semiconductor region and has a higher impurity concentration than the first semiconductor region and the second semiconductor region; Second semiconductor region and fourth semiconductor In contact with both regions located between the band,
Furthermore, on the outer peripheral side of the fifth semiconductor region portion, in the void, the first semiconductor region extends from one main surface to the inside, and
On the main surface on the other conductivity type sixth semiconductor region having a higher impurity concentration than the fourth semiconductor region and a lower impurity concentration than the fourth semiconductor region, the second semiconductor region and at least a part of the sixth semiconductor region. A first electrode which is in ohmic contact with the first opening, which is an exposed surface of the third semiconductor region, and a second opening which is an exposed surface of the fourth semiconductor region. A second electrode in ohmic contact with the part,
A semiconductor device comprising: a third electrode that makes ohmic contact with a third opening that is an exposed surface of the fifth semiconductor region. 2. The semiconductor device according to claim 1, wherein the first opening in the exposed surface of the third semiconductor region is in ohmic contact with a distance from the fifth semiconductor region. 3. The semiconductor device according to claim 2, wherein at least a part of the third semiconductor region which does not face the fourth semiconductor region is removed. 4. On the side of the main surface facing the fourth semiconductor region, at least smaller than the second semiconductor region, extending inward from one main surface of the first semiconductor region, and extending from the second semiconductor region. 4. The semiconductor device according to claim 1, wherein the semiconductor device is deep and has a seventh semiconductor region of one conductivity type having a lower impurity than the third semiconductor region. 5. The first semiconductor region is one of a plurality of island regions provided on one main surface side of a semiconductor substrate so as to be electrically insulated from each other. 1 to
4. The semiconductor device according to any one of 4 above. 6. A linear IC using the semiconductor device according to claim 1 as a high frequency pnp transistor.