JPH07262007A - Information processor - Google Patents

Abstract

PURPOSE:To process two instructions at maximum in one cycle by-replacing the combination of two instructions decided in advance with one compound instruction equivalent to these two instructions. CONSTITUTION:A CLI instruction is extracted from an IBR 10 by a first instruction extraction shifter 20 and stored in an IRP 30. On the other hand, a BC instruction is stored in an IRS by a second instruction extraction shifter 40. A replace instruction generating circuit 90 generates the CLI-BC compound instruction by detecting that the combination of those CLI and BC instructions has been stored in the IRP 30 and the IRS 50. That CLI-BC compound instruction is processed on the respective stages of a pipeline as one instruction. Thus, the insertion of an instruction following two instructions to the pipeline can be made faster by one cycle, and the processing speed can be accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device,
In particular, the present invention relates to a pipeline type information processing device capable of improving an instruction processing speed.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration example of a pipeline type information processing apparatus according to the prior art, FIG. 7 is a diagram for explaining an example of instructions used, and FIGS. 8 to 11 are instruction pipelines. It is a time chart for explaining the processing, and hereinafter, an information processing apparatus according to the related art will be described with reference to these drawings. In FIG. 6, 10 is an instruction buffer register (hereinafter referred to as IBR), 20 is an instruction fetch shifter, 30 is an instruction register (hereinafter referred to as IR),
32 is an instruction length code (hereinafter referred to as ILC) decoder,
60 is a pointer (hereinafter, referred to as IBROP), 70 is an adder, 100 is a branch instruction detection circuit, 110 is an instruction decoder, 130 is a control memory, 140 is an address adder for operand, 150 is TLB for operand, 160 is for operand A buffer storage device, 170 is an operation execution unit, 180
Is a general-purpose register, 200 is an address adder for instruction, 21
Reference numeral 0 is an instruction TLB, and 220 is an instruction buffer storage device.

The information processing apparatus according to the prior art shown in FIG. 6 is configured to include the functional blocks shown in the figure, and each functional block is configured to have the functions described below.

The IBR 10 is a register that holds an instruction to enable high-speed access of the instruction, and the instruction fetch shifter 20 selects the instruction to start the processing next.
It has a function to take out from BR10. IR30
Is a register in which the instruction supplied from the instruction fetch shifter 20 is stored.
The ILC 32 indicating the instruction length of the instruction stored in 0 is decoded to obtain the instruction length of the instruction stored in the IR 30.
The adder 70 uses the IBR1 of the instruction fetched by the IR 30.
The contents of the IBROP 60 holding the start position in 0 and the output of the ILC decoder 32 are added, and IBROP6
It has a function to update the contents of 0.

The branch instruction detection circuit 100 detects that a branch instruction is stored in the IR 30, and the instruction decoder 110
Has a function of decoding an instruction stored in the IR 30, and the control memory 130 stores information for controlling the arithmetic operation performed by the arithmetic execution unit 170 as a microprogram. The operand address adder 140 is
The logical address of the operand is calculated, and the TLB for operand 150 has a function of converting the logical address into a physical address.

The operand buffer storage device 160 is
The data specified by the physical address from the TLB for operand 150 is supplied to the operation executing unit 170, and the operation executing unit 170 stores the operand buffer storage device 160, for example, the general-purpose register 18 including a group of 16 registers.
Operand data supplied from 0 is used to perform operations under the control of the output from the control memory 130. The instruction address adder 200 calculates the logical address of the instruction, and the instruction TLB 210 determines the instruction address adder 20.
Convert a logical address from 0 to a physical address. The instruction buffer storage device 220 supplies the instruction specified by the physical address from the instruction TLB 210 to the IBR 10.

Next, an example of instructions used in the information processing apparatus having the above-mentioned configuration will be described with reference to the format shown in FIG.

The CLI instruction is an instruction for comparing the size of two operand data and reflecting the result in the condition code. OP is an operation code indicating that this instruction is a CLI instruction, I2 is a field indicating the second operand data used for the operation, B1 is a field designating the base address register, and D1 is a field indicating the displacement address. In this instruction, the logical address of the first operand stored in the main memory can be obtained by adding the contents of the base address register indicated by the B1 field and the contents of the D1 field.

The BC instruction is a conditional branch instruction that branches to the branch destination address designated by the second operand when the condition code is set in the state designated by the mask field. OP is an operation code indicating that this instruction is a BC instruction, M
1 is a mask field, X2 is a field for designating an index address register, B2 is a field for designating a base address register, and D2 is a field for indicating a displacement address. In this instruction, the logical address of the branch destination instruction stored in the main memory device is obtained by adding the contents of the index address register shown in the X2 field, the contents of the base address register shown in the B2 field, and the contents of the D2 field. It can be obtained by

The BCT instruction subtracts "1" from the value of the general-purpose register specified by the R1 field, and when the content of the register after the subtraction is not "0", the branch destination address specified by the second operand is used. The instruction is to branch. OP is an operation code indicating that this instruction is a BCT instruction, R1 is the above-mentioned R1 field indicating the value of a general-purpose register, X2 is a field designating an index address register, B2 is a field designating a base address register, and D2 is This is a field indicating a displacement address. In this instruction, the logical address of the branch destination instruction stored in the main memory device is obtained by adding the contents of the index address register shown in the X2 field, the contents of the base address register shown in the B2 field, and the contents of the D2 field. It can be obtained by

The L instruction is an instruction to transfer the data in the main storage device designated by the second operand to the general-purpose register designated by the first operand. OP
Is an operation code indicating that this instruction is an L instruction, R1 is a field indicating the above-mentioned first operand,
X2 is a field for specifying the index address register, B
2 is a field for specifying the base address register, D2
Is a field indicating a displacement address. In this instruction, the address of the second operand data stored in the main memory adds the contents of the index address register shown in the X2 field, the contents of the base address register shown in the B2 field, and the contents of the D2 field. It can be obtained by

The LTR instruction transfers the contents of the general-purpose register specified by the second operand to the general-purpose register specified by the first operand, checks the sign of the second operand, and reflects the result in the condition code. It is an instruction. OP is an operation code indicating that this instruction is an LTR instruction, and R1 and R2 are fields indicating the above-mentioned first and second operands.

Next, with reference to FIGS. 8 to 11, the processing operation in the case of processing a certain instruction sequence having the above-mentioned instruction in the conventional technique configured as described above will be described. In these figures, the horizontal axis at the top indicates the execution cycle of the pipeline and is numbered for convenience of reference. Further, D, A, T, B, L, and E in the figure represent pipeline stages, and perform the following processes, respectively.

The D stage decodes the instruction stored in the IR 30 and refers to the general register 180 for the logical address generation performed in the A stage. At this time, the adder 70 adds the contents of the IBROP 60 and the instruction length obtained by the ILC decoder 32 to obtain I
The content of BROP 60 is updated to point to the instruction next to the instruction stored in IR 30. The addition result is also supplied to the instruction fetch shifter 20 for fetching the subsequent instruction. Therefore, in the next cycle, the instruction following the instruction stored in the IR 30 can be stored in the IR 30. The command stored in IR30 is
It is sent to the instruction decoder 110 and its decoding is performed.

The A stage uses the contents of the general register 180 and a part of the contents of the IR 30 referred to in the D stage to perform a process for obtaining the logical address of the operand by the operand address adder 140. In the case of a branch instruction, the instruction address adder 200 is also used at this stage.
The process for obtaining the logical address of the branch destination instruction is performed by.

In the T stage, the logical address of the operand obtained by the operand address adder 140 in the A stage is converted into a physical address by the TLB for operand 150. Further, in the case of a branch instruction, the logical address of the branch destination instruction obtained by the instruction address adder 200 is converted to a physical address by the instruction TLB.

The B stage refers to the operand buffer storage device 160 in accordance with the physical address of the operand determined by the operand TLB 150 in the T stage and performs a process of obtaining operand data. Also,
In the case of a branch instruction, the TLB2 for the instruction in the T stage
Based on the physical address of the branch destination instruction obtained in step 10, the instruction buffer storage device 220 is referenced to perform processing for obtaining the branch destination instruction sequence. Further, by referring to the control memory 130 based on the instruction decoding information from the instruction decoder 110, processing for obtaining the control information required by the operation executing unit 180 for executing the instruction is performed.

In the L stage, in the B stage, the operand data obtained in the operand buffer storage device 160 is transferred to the operation execution unit 170, and the data stored in the general register 180 is used as an operand data for general purpose. A process of referring to the register 180 and transferring the content thereof to the operation executing unit 170 is performed. Further, in the case of a branch instruction, in the B stage, processing for transferring the branch destination instruction sequence obtained from the instruction buffer storage device 160 to the IBR 10 is performed. If the branch of the branch instruction is taken, the branch destination instruction is stored in the IR 30. That is, when the branch of the branch instruction is taken, the branch destination instruction is input to the pipeline in the cycle next to the L stage of this branch instruction. On the other hand, the control information obtained from the control storage 130 at the B stage is transferred to the arithmetic execution unit 170.

The E stage is operated by the arithmetic execution unit 170.
Using the operand data obtained previously, processing for executing an operation based on the control information is performed. The operation result is written in the general-purpose register 180 or is reflected in the condition code and used for the branch determination of the conditional branch instruction.

Each stage of the above-mentioned processing can be performed without conflict of the logic used, and by utilizing this, the processing can be executed by overlapping each stage. The above-mentioned conventional technique thereby executes the pipeline processing as shown in FIGS.

The time chart shown in FIG. 8 shows the pipeline flow when the branch of the BC instruction is not taken when the CLI instruction and the BC instruction are continuously executed.

In FIG. 8, it is assumed that instructions 0 to 4 are executed in order, instruction 1 is a CLI instruction, and instruction 2 is a BC instruction. Usually, whether or not a branch of a BC instruction is taken can be predicted at the D stage of the instruction.
Therefore, when the branch of the BC instruction as shown in FIG. 8 is not taken, the instruction 4 can be pipelined and processed in the cycle next to the D stage of the BC instruction.

That is, in the case of this example, one instruction can be input to the pipeline every cycle, the operation result can be obtained every cycle, and the instruction processing speed is one instruction per cycle. Ideal processing can be performed.

However, in reality, the processing speed of one instruction per cycle cannot be obtained due to various factors. One of the factors is the overhead of reading the branch destination instruction.

The time chart shown in FIG. 9 shows an example of such a case, and shows the pipeline flow when the branch of the BC instruction is taken when the CLI instruction and the BC instruction are continuously executed. Shows.

In FIG. 9, instructions 0 to 2 are the same as those in FIG. 8, instruction 5 is a branch destination instruction obtained as a result of the branching of the BC instruction, and instruction 6 follows the instruction 5. It is an instruction. In the case of this example, it is possible to predict that the branch will be taken at the D stage of the BC instruction, but the instruction 5 that is the branch destination instruction is input to the pipeline because, as already described, the L stage of the BC instruction. It will be later. For this reason,
In the example of FIG. 9, the branch instruction is input to the pipeline in the third cycle, whereas the branch destination instruction, instruction 5, is input to the pipeline in the eighth cycle, which is four machine cycles. There is a vacancy.

The time chart shown in FIG. 10 shows the pipeline flow when the branch of the BCT instruction is taken.

In FIG. 10, instructions 0 and 1 are B of instruction 2.
Instructions preceding the CT instruction, and instructions 5 and 6 are a branch destination instruction obtained as a result of the branch of the BCT instruction being taken and an instruction following it. In the case of this example as well, it is possible to predict that the branch will be taken at the D stage of the BCT instruction as in FIG. 9, but the instruction 5 which is the branch destination instruction is injected into the pipeline in the eighth cycle. This will result in empty machine cycles.

The time chart shown in FIG. 11 shows the L instruction,
4 shows a pipeline flow of an LTR instruction.

In FIG. 11, instructions 1 and 2 are L respectively.
The instruction is the same as the case of FIG. 8 except that it is an LTR instruction. In the case of this example, as in the case shown in FIG. 8, one instruction can be input to the pipeline every cycle, and the operation result can be obtained every cycle.

As a conventional technique relating to the information processing apparatus of the above-mentioned pipeline processing system, for example, the technique described in Japanese Patent Laid-Open No. 63-195736 is known.

[0032]

The information processing apparatus having the pipeline processing mechanism according to the above-mentioned prior art has a problem that the processing speed is limited to one instruction per cycle at the maximum. Also, due to various overheads such as the overhead for reading the branch destination instruction,
Actually, there is a problem that it takes several cycles on average to process one instruction.

The object of the present invention is to solve the above-mentioned problems of the prior art, and to replace a predetermined combination of two instructions with one instruction of a composite instruction equivalent to the two instructions.
An object is to provide an information processing device capable of processing a maximum of two instructions in a cycle.

Another object of the present invention is to enable at least a part of processing of a branch instruction to be processed in parallel with pipeline processing of an instruction preceding the branch instruction,
Accordingly, it is an object of the present invention to provide an information processing apparatus capable of reducing the read overhead of a branch destination instruction.

[0035]

SUMMARY OF THE INVENTION According to the present invention, the above object is to combine instructions so that the decoded instruction can be executed as one instruction and the branch destination instruction can be read faster. It is achieved by

That is, in addition to the first instruction fetch means for normal pipeline processing,
Second instruction fetching means for fetching a subsequent instruction of the instruction fetched by the instruction fetching means, and first instruction storing means for storing the instruction fetched by the first instruction fetching means, and second instruction fetching means The second instruction storage means for storing the instruction to be retrieved by the first instruction storage means and the instructions stored in the first instruction storage means and the second instruction storage means are checked to see if they are a predetermined instruction combination, Replacement instruction generating means for replacing the two instructions with an equivalent compound instruction, and when the replacement instruction generating means generates a replacement instruction, the first instruction storing means stores the second instruction storing means. Means for controlling the first instruction fetching means so as to store the instruction immediately after the instruction stored in, and whether or not the instruction stored in the second instruction storing means is a branch instruction, Branching life And the instruction stored in the first instruction storage means is a branch instruction, and the reading of the branch destination instruction of the branch instruction is the second. When it is started by the branch instruction detecting circuit, the first branch instruction detecting circuit is provided to suppress the reading of the branch destination instruction due to the storage of the branch instruction in the first instruction storing means. .

[0037]

When the replacement instruction generation circuit detects that the two instructions stored in the first instruction storage means and the second instruction storage means are a combination of predetermined instructions, the two instructions are combined into one. Replace with a compound command that is compounded into a command. Then, in the next cycle, the instructions following these two instructions are stored in the first instruction storage means. The replaced compound instruction is processed as one instruction at each stage of the pipeline.

As a result, according to the present invention, the pipeline injection of the instruction subsequent to the above-mentioned two instructions can be advanced by one cycle, and the processing speed can be improved.

When the instruction fetched by the second instruction fetch means is a branch instruction, the branch instruction detection circuit immediately starts reading the branch target instruction. Therefore, the first
In parallel with the processing in each stage of the pipeline of the instruction preceding the branch instruction fetched by the instruction fetching means, the reading of the branch destination instruction is processed in each stage of the pipeline, and the reading of the branch destination instruction Overhead can be reduced.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an information processing apparatus according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an information processing apparatus by a pipeline processing system according to an embodiment of the present invention, FIG. 2 is a time chart showing a pipeline flow when a branch of a BC instruction is not taken, and FIG. Is a time chart showing the pipeline flow when the branch of the BC instruction is taken, FIG. 4 is a time chart showing the pipeline flow when the branch of the BCT instruction is taken, and FIG.
It is a time chart which shows the pipeline flow which decodes and executes a TR instruction. In FIG. 1, 40 is a second instruction fetch shifter, 50 is a second instruction register, and 52.
Is a second ILC decoder, 80 is a selector, 90 is a replacement instruction generation circuit, 105 is a second branch instruction detection circuit, and other reference numerals are the same as those in FIG. However, in the embodiment of the present invention, the description will be given by adding the "first" to the one provided with the same functional block as the "second" in addition to the prior art and the one provided conventionally. To do.

The embodiment of the present invention shown in FIG. 1 is the same as the prior art described with reference to FIG.
0, second instruction register 50, second ILC decoder 5
2, a selector 80, a replacement instruction generation circuit 90, and a second branch instruction detection circuit 105 are added. First, these functional blocks will be described. Note that the same block in the conventional technique has the same function as that described as the conventional technique, and thus the description thereof will be omitted.

The second instruction fetch shifter 40 uses the first instruction fetch shifter 20 based on the instruction length code ILC21 indicating the instruction length of the first instruction of the instruction sequence fetched by the first instruction fetch shifter 20. It has a function of fetching the instruction immediately after the instruction stored in the IRP 30 by fetching the instruction from the position which is indicated by the ILC 21 from the head of the fetched instruction sequence. The second instruction register IRS50 is used by the second instruction fetch shifter 40.
Stores the instruction fetched by.

The second ILC decoder 52 has an IRS 50.
It has a function of obtaining the instruction length of the instruction stored in the IRS 50 from the second ILC 51 indicating the instruction length of the instruction stored in the. The adder 70 receives the contents of the IBROP 60 and the first I
It has a function of adding the contents of the LC decoder 32 and the value supplied by the selector 80 to update the contents of the IBROP 60. The selector 80 is “0” or the second ILC.
One of the outputs of the decoder 52 is selected and supplied to the adder 70.

When the IRP 30 and the IRS 50 store a predetermined combination of instructions, the replacement instruction generation circuit 90 replaces them with one composite instruction,
Otherwise, it has a function of directly outputting the contents of the IRP 30. The second branch instruction detection circuit 105 uses the IR
It is detected that the branch instruction is stored in S50.

Next, the operation of the embodiment of the present invention configured as described above will be described. Note that the information processing apparatus according to the embodiment of the present invention also uses the instructions described with reference to FIG. 7, as in the case of the above-described conventional technique.

First, the case where the CLI instruction and the BC instruction are consecutive in this order and these instructions are replaced by the CLI-BC compound instruction will be described as an example with reference to FIGS.

FIG. 2 is a diagram showing a pipeline flow in the case where the branch of the BC instruction is not taken. This pipeline flow will be described below.

In FIG. 2, the instruction 0 is an instruction preceding the CLI instruction, the instruction 3 is an instruction subsequent to the BC instruction, and the instruction 4 is an instruction subsequent to the instruction 3, which are added for convenience of description.

In the embodiment of the present invention shown in FIG. 1, first, the instruction 0 is transferred to the IB by the first instruction fetch shifter 20.
It is taken out from R10 and stored in IRP30. Then, the D stage of the instruction 0 is started in the first cycle.
At the same time, the CLI instruction, which is the instruction following the instruction 0,
The second instruction fetch shifter 40 fetches to the IRS 50.

In the D stage of instruction 0, replacement instruction generation circuit 90 inspects the contents of IRP 30 and IRS 50. The replacement instruction generation circuit 90 holds a combination of instructions that can be composited in advance, and detects that the combination of instructions in this case is not the target of instruction composition. Based on this result, the selector 80 is controlled by the replacement instruction generation circuit 90 to select "0", and "0" is added to the adder 7
Supply to 0.

Therefore, the contents of IBROP 60 are updated to the sum of the old value and the length of the instruction in IRP 30, that is, instruction 0. Then, this value is supplied to the first instruction fetch shifter 20.

As a result, in the second cycle, the IRP
30 to the CLI by the first instruction fetch shifter 20.
The instruction is stored, and the BC instruction is stored in the IRS 50 by the second life instruction fetch shifter 40. The replacement instruction generation circuit 90 uses the CLI instruction and the B
It detects that the combination with the C instruction is stored in the IRP 30 and IRS 50, and generates the CLI-BC compound instruction.

On the other hand, the second branch instruction detection circuit 105
It is detected that the branch instruction is stored in the RS 50, and the reading of the branch destination instruction is started.

As a result, in the second cycle, CL
The D stage of the I-BC instruction and the D stage of reading the branch destination instruction are processed in parallel. In this D stage, it is possible to predict whether or not the branch of the BC instruction is taken,
In the case of the example shown in FIG. 2, branch failure is predicted. As a result, the replacement instruction generation circuit 90 outputs the pseudo operation code assigned to the CLI-BC instruction to the instruction decoder 11
In addition to supplying 0, the selector 80 is controlled to select the output of the second ILC decoder 52.

As a result, the adder 70 is supplied with the instruction length of the BC instruction from the selector 80, and adds the instruction length of this BC instruction, the old value of IBROP 60, and the instruction length of the CLI instruction to obtain the sum. Store in IBROP60. That is, the contents of the IBROP 60 are updated to point to the instruction 3 which is the subsequent instruction of the BC instruction. Since the output of the adder 70 is also supplied to the first instruction fetch shifter 20, the instruction 3 is fetched to the IRP 30 by the first instruction fetch shifter 20 in the third cycle.

In the second cycle, the instruction decoder 11
0 is the CLI-B supplied from the replacement instruction generation circuit 90.
The decoding information of the pseudo operation code assigned to the C instruction is generated. Further, the general-purpose register 180 is referenced by the B1 field of the CLI instruction stored in the IRP 30, and the content and the content of the D1 field of the CLI instruction are supplied to the operand address adder 140. Further, the general-purpose register 180 is referenced by the X2 and B2 fields of the BC instruction stored in the IRS 50, and the contents and the contents of the D2 field of the BC instruction are supplied to the instruction address adder 200.

In the third cycle, the A stage of the CLI-BC compound instruction and the A stage of reading the branch destination instruction are processed in parallel. Operand address adder 14
0 adds the data supplied from the general-purpose register 180 and the IRP 30 to obtain the logical address of the first operand of the CLI-BC compound instruction. Further, the instruction address adder 200 includes a general-purpose register 180 and an IR.
By adding the data supplied from S50,
Obtain the logical address of the branch destination instruction.

In the fourth cycle, the T stage of the CLI-BC compound instruction and the T stage of reading the branch destination instruction are processed in parallel. The operand TLB 150 has a CLI-value obtained by the operand address adder 140.
The logical address of the first operand of the BC compound instruction is converted into a physical address. Further, the instruction TLB 210 converts the logical address of the branch destination instruction obtained by the instruction address adder 200 into a physical address.

In the fifth cycle, the B stage of the CLI-BC compound instruction and the B stage of reading the branch destination instruction are processed in parallel. The control memory 130 is referred to by the instruction decoding information fetched from the instruction decoder 110,
The control information necessary for executing the CLI-BC compound instruction can be supplied to the arithmetic execution unit 170. The operand buffer storage device 160 is referred to by the physical address of the first operand of the CLI-BC compound instruction obtained by the operand TLB 150, and the first operand data necessary for executing the operation can be supplied to the operation executing unit 170. Becomes In addition, the instruction buffer storage device 220 uses the instruction TLB 2
The branch destination instruction can be supplied to the IBR 10 by being referred to by the physical address of the branch destination instruction obtained in 10.

In the sixth cycle, the L stage of the CLI-BC compound instruction and the L stage of reading the branch destination instruction are processed in parallel. The control information of the CLI-BC compound instruction extracted from the control storage 130 is the operation execution unit 170.
Second operand, which is the content of the I2 field in the CLI instruction and the first operand data of the CLI-BC compound instruction transferred to the operand buffer storage device 160.
Operand data is also transferred to the operation execution unit. The branch destination instruction fetched from the instruction buffer storage device 220 is supplied to the IBR 10. However, if the branch is not taken, this branch destination instruction is not used. Therefore, in the case of the example shown in FIG. 2, this branch destination instruction is not used.

In the seventh cycle, the operation executing section 170
Executes the operation of the CLI-BC compound instruction. That is, the operation executing unit 170 uses the first operand data read from the operand buffer storage device 160 and C
The second operand data, which is the content of the I2 field in the LI instruction, is compared, and the condition code is set according to the comparison result.

On the other hand, as described above, in the second cycle, the first instruction fetch shifter 20 is controlled so as to fetch the instruction string from the position of the instruction 3, so that the instruction 3 receives the IRP 30 in the third cycle. Is set to.
Further, in the subsequent fourth cycle, the instruction 4 is sequentially input to the pipeline.

As described above, according to the embodiment of the present invention, the CL
When the I instruction and the BC instruction are consecutive, these instructions can be compounded to execute the BC instruction processing in parallel with the CLI instruction pipeline processing, and B
When the branch of the C instruction is not taken, the instruction 3 and the instruction 4 which are the subsequent instructions of the BC instruction can be input to the pipeline from the third cycle. As a result, the embodiment of the present invention can advance the injection of the instruction 3 and the instruction 4 into the pipeline by one cycle as compared with the flow shown in FIG. 8 for explaining the operation in the case of the conventional technique under the same condition. The processing speed of the information processing device can be improved.

FIG. 3 is a diagram showing the pipeline flow when the branch of the BC instruction is taken, and this pipeline flow will be described below.

In FIG. 3, the instruction 0 is an instruction preceding the CLI instruction, the instruction 5 is a branch destination instruction of the BC instruction, and the instruction 6 is an instruction following the instruction 5, which are added for convenience of description.

In FIG. 3, D of instruction 0 in the first cycle
The stage is executed, and the D stage of the CLI-BC compound instruction and the D stage of reading the branch destination instruction are processed in parallel in the second cycle, which is the same as the case where the branch is not taken in FIG. 2 described above. In the case of this example, since the branch taken can be predicted in the processing of the D stage of the second cycle, the CLI-BC compound instruction and the branch destination instruction read A can be executed without starting the read processing of the instruction 3.
The stage, T stage, B stage, and L stage are processed in parallel and sequentially. This processing is also the same as the case where the branch is not taken in FIG. 2 described above.

In the seventh cycle, as described above, the operation executing section 170 executes the operation of the CLI-BC compound instruction and sets the condition code.

On the other hand, in the L stage in the sixth cycle, the instruction 5 which is the branch destination instruction transferred from the instruction buffer storage device 220 to the IBR10 is set in the IRP30 in the subsequent seventh cycle, and the processing by the pipeline is started. To be done. In the following 8th cycle, instruction 6
Are sequentially put into the pipeline.

As described above, the embodiment of the present invention uses CL
By compounding the I instruction and the BC instruction, the processing of the BC instruction is performed by the C instruction.
When executed in parallel with the pipeline processing of the LI instruction and the branch of the BC instruction is not taken, the instruction 5 which is the branch destination instruction and the subsequent instruction 6 can be input to the pipeline from the seventh cycle. As a result, the embodiment of the present invention will be described with reference to FIG.
Compared with the flow shown in (1), the instruction 5 and the instruction 6 can be input into the pipeline one cycle earlier, and the processing speed of the information processing apparatus can be improved.

Next, as an operation example capable of reducing the overhead due to the reading of the branch destination instruction, BCT
The processing of the instruction will be described. Since the BCT instruction requires the operation of the general-purpose register indicated by R1, contention occurs in the arithmetic units, and all the processing cannot be executed in parallel with the preceding instruction. Therefore, only the read processing of the branch destination instruction is executed in parallel without being converted into a composite instruction.

FIG. 4 is a diagram showing a pipeline flow when an instruction string including a BCT instruction is executed by the information processing apparatus shown in FIG. 1, which will be described below.

The flow shown in FIG. 4 is an example in the case where the branch of the BCT instruction is taken. Instruction 0 and instruction 1 are instructions preceding the BCT instruction, instruction 5 is the branch destination instruction of the BCT instruction,
The instruction 6 is an instruction following the instruction 5, and is added for convenience of description.

In the first cycle, after instruction 0 is input to the pipeline, in the second cycle,
Instruction 1 is put into the pipeline. At this time, the first instruction fetch shifter 20 sends the fetched instruction 1 to the IRP.
At the same time, the second instruction fetch shifter 40 stores the BCT instruction, which is a subsequent instruction of the instruction 1, in the I.
Store in RS50. Second branch instruction detection circuit 105
Detects that the BCT instruction, which is a branch instruction, has been set in the IRS 50, and starts reading the branch destination instruction.

As a result, in the second cycle, the D stage of the instruction 1 and the D stage of reading the branch destination instruction are processed in parallel. In the D stage of the second cycle, it is predicted that the branch of the BCT instruction will be taken. Further, as described above, since the instruction 1 and the BCT instruction are not the target of instruction combination, the replacement instruction generation circuit 90
Operation code of the instruction decoder 110 as it is
And the selector 80 is controlled to select "0". The adder 70 receives “0” supplied from the selector 80, the old value of the IBROP 60, and the first IL.
IBROP60 is performed by calculating the sum with the output of the C decoder 32.
Update the value of. As a result, IBROP 60
Is updated to point to a BCT instruction that is a subsequent instruction of.

Since the output of the adder 70 is also supplied to the first instruction fetch shifter 20, the BCT instruction is fetched by the first instruction fetch shifter 20 and stored in the IRP 30 in the subsequent third cycle. Also, instruction 1
Is an instruction that requires a memory operand,
Reference is made to the general-purpose register 180 that is needed to obtain the logical address of the operand.

On the other hand, the BCT set in the IRS 50 to obtain the logical address of the branch destination instruction of the BCT instruction.
General-purpose register 180 according to the X2 and B2 fields of the instruction
Is referred to, and the content and the content of the D2 field of the BCT instruction are supplied to the instruction address adder 200.
Further, the detection result of the second branch instruction detection circuit 105 and the result of the replacement instruction generation circuit 90 are sent to the first branch instruction detection circuit 100, and the branch destination instruction read processing in the third cycle is suppressed.

In the third cycle, the A stage of the instruction 1 and the A stage of reading the branch destination instruction are processed in parallel. The instruction decoder 110 includes a replacement instruction generation circuit 90.
Decode the operation code of the instruction 1 supplied from the device and generate the decryption information. Further, the operand address adder 140 includes a general-purpose register 180 and an IRP 30.
Instruction 1 is added by adding the data supplied from
The logical address of the operand of. The instruction address adder 200 calculates the logical address of the branch destination instruction by adding the data supplied from the general-purpose register 180 and the IRS 50.

In the fourth cycle, the T stage of the instruction 1 and the T stage of reading the branch destination instruction are processed in parallel. The operand TLB 150 converts the logical address of the operand of the instruction 1 obtained by the operand address adder 140 into a physical address. TLB for instruction
210 converts the logical address of the branch destination instruction obtained by the instruction address adder 200 into a physical address.

In the fifth cycle, the B stage of instruction 1 and the B stage of reading the branch destination instruction are processed in parallel. The control memory 130 is referred to by the instruction decoding information supplied from the instruction decoder 110, and prepares the control information necessary for executing the instruction 1. The operand buffer storage device 160 is referred to by the physical address of the operand of the instruction 1 obtained by the TLB 150 for the operand, and prepares the operand data necessary for executing the operation of the instruction 1. The instruction buffer storage device 220 uses the instruction TLB 2
The branch destination instruction is prepared by referring to the physical address of the branch destination instruction obtained in step 10.

In the sixth cycle, the L stage of the instruction 1 and the L stage of reading the branch destination instruction are processed in parallel. The control information of the instruction 1 prepared in the control memory 130 is transferred to the operation executing unit 170, and the operand data of the instruction 1 prepared in the operand buffer storage device 160 is also transferred to the operation executing unit 170. The branch destination instruction prepared in the instruction buffer storage device 220 is supplied to the IBR 10.

In the seventh cycle, the operation executing section 170
Executes the operation of instruction 1. Further, the instruction 5 which is the branch destination instruction of the BCT instruction is stored in the IRP 30 via the first instruction fetch shifter 20. On the other hand, the BCT instruction causes the IRP30 in the third cycle as described above.
Then, the processing other than the reading of the branch destination instruction is executed, and the operation is executed in the eighth cycle.

As described above, according to the embodiment of the present invention, when a BCT instruction that cannot be decoded is processed, the reading of the branch destination instruction of the BCT instruction is performed in parallel with the normal instruction preceding the branch instruction. You can do it. As a result, the embodiment of the present invention can accelerate the injection of the instructions 5 and 6 into the pipeline by one cycle as compared with the flow shown in FIG. 10 for explaining the operation in the case of the conventional technique under the same condition. The processing speed of the information processing device can be improved.

The operation example described above is an example of processing an instruction sequence including a branch instruction. Next, an example of performing processing by compounding an instruction sequence not including a branch instruction will be described. .

FIG. 5 is a diagram showing a pipeline flow in the case where the L instruction and the LTR instruction are consecutive in this order, and these instructions are replaced with the L-LTR compound instruction for processing.

The condition for compounding the L instruction and the LTR instruction is that the R1 field of the L instruction and the R1 of the LTR instruction of FIG.
This is the case where the field and the R2 field all have the same value. The L instruction and the LTR instruction are used under such a condition when the sign of the data fetched from the main memory device to the general-purpose register is inspected and the result is reflected in the condition code. That is, although the L instruction transfers data from the main storage device to the general-purpose register, since the transfer result is not reflected in the condition code, the LTR instruction is usually placed after the L instruction and reflected in the condition code. There is.

An embodiment of the present invention is such that
By combining the L instruction and the LTR instruction, it is possible to perform the same operation as if the L instruction reflecting the transfer result in the condition code is executed. That is, according to one embodiment of the present invention, the data in the main memory can be transferred to the general-purpose register, the code thereof can be checked, and the result can be reflected in the condition code.

In the operation of the L-LTR compound instruction, first, the operand data in the main memory required by the original L instruction is read, and this operand data is transferred to the general register 180 via the operation executing section 170. Perform processing,
At this time, the operation executing unit 170 checks the sign of the operand data, and executes the processing of reflecting the result in the condition code.

The pipeline flow of the L-LTR compound instruction will be described below with reference to FIG. In FIG. 5, instruction 0 is an instruction preceding the L instruction, instruction 3 is an instruction following the LTR instruction, and instruction 4 is an instruction following the instruction 3.

In the first cycle, the first instruction fetch shifter 20 fetches the instruction 0 from the IBR 10 and I
The second instruction fetch shifter 40 stores it in the RP 30, and at the same time, the second instruction fetch shifter 40 fetches an L instruction, which is a subsequent instruction of the instruction 0, and I
Store in RS50. The replacement instruction generation circuit 90 uses the IRP
The contents of 30 and IRS 50 are inspected, and it is detected that the combination of instruction 0 and L instruction is not the target of instruction compounding. Therefore, the selector 80 has the replacement instruction generation circuit 90.
Is controlled so as to select "0", and "0" is supplied to the adder 70. Therefore, the contents of the IBROP 60 are updated to the sum of the old value and the length of the instruction in the IRP 30, that is, the instruction 0, via the adder 70. The value from the adder 70 is also supplied to the first instruction fetch shifter 20.

As a result, in the second cycle, the first instruction fetch shifter 20 stores the L instruction in the IRP 30, and the second instruction fetch shifter 40 stores the L instruction in the IRS 50.
Store the TR command. At this time, the replacement instruction generation circuit 90
Examines the contents of IRP30 and IRS50, detects that the combination of the L instruction and the LTR instruction is the subject of the compounding instruction, and generates the L-LTR compound instruction. As a result, the second cycle becomes the D stage of the L-LTR compound instruction.

Further, in the second cycle, the replacement instruction generating circuit 90 supplies the pseudo operation code assigned to the L-LTR composite instruction to the instruction decoder 110 and selects the output of the second ILC decoder 52. The selector 80 is controlled. Since the adder 70 is supplied with the instruction length of the LTR instruction from the selector 80, the IB
The ROP 60 is updated by the adder 70 so as to indicate the sum of the old value thereof, the instruction length of the L instruction and the instruction length of the LTR instruction, that is, the instruction 3 which is a subsequent instruction of the LTR instruction. Further, the value of the adder 70 is the same as that of the first instruction fetch shifter 20.
Is also supplied to IRP3 in the third cycle.
Stored in 0. The instruction decoder 110 decodes the pseudo operation code supplied from the replacement instruction generating circuit 90 and generates the decoded information. Furthermore, the general-purpose register 180 is referred to by the X2 and B2 fields of the L instruction stored in the IRP 30, and the contents of the general-purpose register are
The contents of the D2 field of the L instruction are supplied together to the operand address adder 140.

In the third cycle, the A stage of the L-LTR compound instruction is executed. The operand address adder 140 calculates the logical address of the second operand of the original L instruction by adding the data supplied from the general-purpose register 180 and the IRP 30.

In the fourth cycle, the T stage of the L-LTR compound instruction is executed. TLB15 for operand
0 converts the logical address of the second operand of the original L instruction obtained by the operand address adder 140 into a physical address.

In the fifth cycle, the B stage of the L-LTR compound instruction is executed. The operand buffer storage device 160 is referred to by the physical address of the second operand of the original L instruction obtained by the operand TLB 150, and prepares the second operand data of the original L instruction used by the operation execution unit 180. In addition, the control memory 130
Is referred to by the instruction decoding information fetched from the instruction decoder 110 and prepares the control information necessary for executing the L-LTR compound instruction.

In the sixth cycle, the L stage of the L-LTR compound instruction is executed. The control information of the L-LTR compound instruction prepared in the control memory 130 is stored in the operation execution unit 17
0, and at the same time, the second operand data of the original L instruction prepared in the operand buffer storage device 160 is also transferred to the operation executing section 170.

In the seventh cycle, the E stage of the L-LTR compound instruction is executed and the operation of the L-LTR compound instruction is performed. The second operand data of the original L instruction is transferred to the first operand of the original L instruction, that is, the general register indicated by the first operand of the original LTR instruction, its sign is checked, and the result is a condition code. Reflected in.

On the other hand, as described above, the instruction 3 is input to the pipeline in the third cycle, and the next instruction 4 is input to the pipeline in the next fourth cycle.

As described above, according to the embodiment of the present invention, the L instruction and the LTR instruction can be combined and executed. As a result, the operation of the prior art under the same condition will be described with reference to FIG. Compared with the flow shown, the instruction 3 and the instruction 4 can be input into the pipeline one cycle earlier, and the processing speed of the information processing apparatus can be improved.

[0100]

As described above, according to the present invention, it is possible to combine two instructions having a predetermined combination and process them as one instruction, and at least a part of the read of the branch destination instruction is executed as the branch instruction. In parallel with the instruction preceding
The overhead of reading the branch destination instruction can be reduced, and thus the processing speed of the information processing device can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a pipeline flow in the case where a branch of a CLI-BC compounding instruction is not taken according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a pipeline flow in the case where a branch of a CLI-BC compounding instruction is taken according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a pipeline flow when a branch of a BCT instruction is taken according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a pipeline flow of an L-LTR compound instruction according to an embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration example of an information processing device according to a conventional technique.

FIG. 7 is a diagram illustrating an example of instructions used.

FIG. 8 is a diagram illustrating a pipeline flow in the case where a CLI instruction and a BC instruction are not branched in the related art.

FIG. 9 is a diagram for explaining a pipeline flow in the case where a CLI instruction and a BC instruction are taken in a branch according to a conventional technique.

FIG. 10 is a diagram illustrating a pipeline flow in the case where a branch of a BCT instruction is taken in the prior art.

FIG. 11 is a diagram illustrating a pipeline flow of an L instruction and an LTR instruction in a conventional technique.

[Explanation of symbols]

 10 instruction buffer register (IBR) 20 first instruction fetch shifter 30 first instruction register (IRP) 32 first ILC decoder 40 second instruction fetch shifter 50 second instruction register (IRS) 52 second ILC Decoder 60 Pointer (IBROP) 70 Adder 80 Selector 90 Replacement instruction generation circuit 100 First branch instruction detection circuit 105 Second branch instruction detection circuit 110 Instruction decoder 130 Control memory 140 Operand address adder 150 Operand TLB 160 operand Buffer storage device 170 operation execution unit 180 general-purpose register 200 instruction address adder 210 instruction TLB 220 instruction buffer storage device

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuro Ojima 1 Horiyamashita, Hadano-shi, Kanagawa Pref., General Computer Division, Hiritsu Manufacturing Co., Ltd.

Claims (4)

[Claims] 1. In a pipeline type information processing apparatus, an instruction buffer means for temporarily holding an instruction sequence sequentially read from a memory, and a first instruction for sequentially fetching instructions from the instruction buffer means to start pipeline processing. Instruction fetching means, second instruction fetching means that sequentially fetches an instruction next to the instruction fetched by the first instruction fetching means from the instruction buffer means, and the first instruction fetching means.
First instruction storing means for storing the instruction fetched by the instruction fetching means, second instruction storing means for storing the instruction fetched by the second instruction fetching means, and the first instruction storing means When the combination of the executed instruction and the instruction stored in the second instruction storage unit matches a predetermined combination of instructions, the replacement for replacing the combination of instructions with a compound instruction equivalent to those instructions An information processing apparatus comprising: an instruction generating means; and a branch instruction detecting means for detecting that the instruction stored in the second instruction storing means is a branch instruction. 2. When the replacement instruction generation means generates a replacement instruction, the first instruction fetch means immediately after the instruction stored in the first instruction storage means in the second instruction storage means. The information processing apparatus according to claim 1, wherein the information processing apparatus stores the instruction. 3. When the replacement instruction generation means generates a replacement instruction, the processing of the instruction stored in the second instruction storage means is pipeline processing of the instruction stored in the first instruction storage means. The information processing apparatus according to claim 1, wherein the information processing apparatus is executed in parallel with. 4. When the branch instruction detecting means detects a branch instruction, at least part of the processing of the branch instruction stored in the second instruction storing means is stored in the first instruction storing means. 4. The information processing apparatus according to claim 1, wherein the information processing apparatus is executed in parallel with pipeline processing of the executed instruction.