JPH07254612A - Heterojunction bipolar transistor - Google Patents

Abstract

PURPOSE:To provide a heterojunction bipolar transistor in which the thickness of a guard ring layer can be controlled accurately. CONSTITUTION:The heterojunction bipolar transistor comprises a collector layer, a base layer 4 and partial emitter layers 5, 7 laminated sequentially on a GaAs substrate 1 and a guard ring layer 9 wherein the emitter layer comprises an etching stop layer 6 inserted into a desired position and and two partial emitter layers 5, 7 sandwiching the etching stop layer 6. The guard ring layer 9 comprises the etching stop layer 6 and the partial emitter layer 5 located closer to the base layer 4 side than the etching stop layer 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction bipolar transistor, and more particularly to the structure of its guard ring.

[0002]

2. Description of the Related Art In recent years, GaAs-based heterojunction bipolar transistors (HBTs)
istor) is being actively researched and developed. This device is expected to have high emitter injection efficiency, high gain, and high speed. By the way, there is a base resistance as a parameter that contributes to speeding up, and in order to reduce it, the base layer is heavily doped. Recently, in a GaAs system, by using a base layer doped with carbon having a small diffusion coefficient, deterioration of characteristics due to diffusion of a base dopant into an emitter layer is eliminated, and H
Practical use is expected more and more as a high-performance electronic device next to EMT. On the other hand, as the HBT device is miniaturized to reduce the power consumption, another deterioration factor different from the deterioration of the characteristics due to the diffusion of the base dopant into the emitter layer has been clarified. This is because the influence of surface leakage current due to surface recombination becomes relatively large as the emitter size is reduced, and the base current increases.
In order to prevent this surface leakage current, the area of the constant film thickness portion of the emitter layer immediately above the emitter / base interface is widened within a range where it does not contact the base electrode, so that the emitter / base interface, that is, the p / n junction has a pn product. It is effective to coat with an emitter layer, which is a small wide gap material, to reduce the surface recombination current. This structure is known as a guard ring structure.

[0003]

By the way, since the effect of this guard ring structure strongly depends on the thickness of the guard ring layer, it is necessary to accurately control the thickness of the guard ring layer. However, the thickness of the guard ring layer is 0.0
Since it is about 5 μm, there is a problem that it is difficult to control the thickness accurately.

[0004]

SUMMARY OF THE INVENTION The present invention provides a heterojunction bipolar transistor which solves the above problems and comprises a GaAs substrate on which a collector layer, a base layer and an emitter layer are sequentially laminated, and a guard ring layer. In the heterojunction bipolar transistor having, the emitter layer is composed of an etching stopper layer inserted at a desired position and two partial emitter layers above and below the etching stopper layer, and the guard ring layer is a base layer from the etching stopper layer. The first invention is constituted by a partial emitter layer on the layer side or the etching stopper layer and a partial emitter layer on the base layer side of the etching stopper layer, and the emitter layer has a desired thickness on the base layer. Etching stop layer and an upper partial emitter layer formed through the etching stop layer Rannahli, the guard ring layer, that is formed by the etch stop layer is to the second invention.

[0005]

In the first invention described above, the etching stop layer is inserted into the emitter layer at a position where the thickness from the base layer corresponds to the thickness of the guard ring layer. Then, when the emitter layer is etched to form the emitter portion in a mesa shape, the etching is stopped by the etching stopper layer in the periphery of the emitter portion, and a partial emitter layer on the base layer side of the etching stopper layer remains. Therefore, if the guard ring layer is composed of this partial emitter layer, the thickness of the guard ring layer can be accurately controlled. The guard ring layer may be formed by adding an etching stop layer to this partial emitter layer. When the emitter layer is formed on the base layer via the etching stop layer having the thickness of the guard ring layer as in the second aspect of the invention, the etching stop layer is used as the guard ring layer, and the thickness is accurately controlled. In addition, the number of epitaxial layers to be laminated can be reduced and the lamination process can be simplified.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the drawings. 1A to 1D are views showing a manufacturing process of an embodiment of a heterojunction bipolar transistor according to the present invention. In the figure, 1 is a GaAs substrate, 2 is a GaAs contact layer having a thickness of 300 nm (n = 4 × 10
¹⁸ cm ⁻³ ), 3 is a 300 nm thick GaAs collector layer (n = 1 × 10 ¹⁸ cm ⁻³ ), 4 is 70 nm thick GaA
s base layer (p = 4 × 10 ¹⁹ cm ⁻³ ), 5 has a thickness of 20 n
m InGaP partial emitter layer (n = 5 × 10 ¹⁷ c
m ^-3 ), 6 is a 10 nm thick InGaAsP etching stop layer (n = 5 × 10 ¹⁷ cm ^-3 ), 7 is a 50 nm thick InGaP partial emitter layer (n = 5 × 10 ¹⁷ cm ^-3 ),
8 is a 50 nm thick InGaAs cap layer (n = 1 ×)
10 ¹⁹ cm ^-3 ). The thickness of the etching stopper layer 6 is preferably 1 nm or more, more preferably 3 nm or more. The reason is that if it becomes too thin, control by the etching time becomes difficult. In this embodiment, the guard ring 9 is designed to maximize the current gain when the thickness is 30 nm.
Therefore, even if the guard ring 9 is thicker than 30 nm or thinner than 30 nm, the current gain is lowered.

The manufacturing process of this embodiment is as follows.
1) First, as shown in FIG. 1A, a contact layer 2, a collector layer 3, a base layer 4, a partial emitter layer 5, an etching stop layer 6, a partial emitter layer 7 and a cap layer are formed on a GaAs substrate 1. 8 are sequentially laminated. 2) Next, a mask is formed on the cap layer 8 and the cap layer 8 and the partial emitter layer 7 are etched with an etchant made of tartaric acid (FIG. 1B). This etchant is compared with InGaAs forming the cap layer 8 and InGaP forming the partial emitter layer 7, and
Since the etching rate of aAsP is extremely low, InG
aAsP has a function as an etching stop layer. 3) Then, the base layer 4 is exposed by etching,
The guard ring 9 is formed (FIG. 1 (c)). 4) Next, the collector layer 3 is exposed by etching, and finally, the collector electrode 10, the base electrode 11, and the emitter electrode 12 are formed (FIG. 1D).

In the thus produced heterojunction bipolar transistor, the guard ring 9 is composed of the etching stop layer 6 and the partial emitter layer 5, and its thickness is accurately controlled to 30 nm. FIG. 2 is a diagram showing the relationship between the emitter size and the current gain when the thickness of the guard ring 9 is 30 nm. In addition, as a comparative example of this example, one in which the guard ring thickness was controlled by the etching time of the emitter layer was manufactured. When the manufacturing yields in which the current gain was 50 or more were compared between this example and the comparative example, the manufacturing yield of the present example was improved by 50% or more as compared with the comparative example.

In the above embodiment, the guard ring 9 may be composed of only the partial emitter layer 5. further,
Alternatively, except for the lower partial emitter layer 5, the etching stopper layer 6 may be directly laminated on the base layer 4, and the guard ring 9 may be composed of only the etching stopper layer 6. Further, the materials of the partial emitter layers 5 and 7 and the etching stop layer 6 are not limited to those in the above embodiment. For example, the partial emitter layers 5 and 7
Is InGaAsP, the etching stopper layer 6 is InGaAsP or InGaP having a composition different from that of the partial emitter layers 5 and 7, and tartaric acid is used as an etchant. Alternatively, the partial emitter layers 5 and 7 are made of AlGaAs, and the etching stop layer 6 is made of GaAs, InGaP, or I.
nGaAsP is used, and tartaric acid is used as an etchant. In this case, if the etching stopper layer 6 is InGaP, there is an advantage that a large etching selection ratio can be obtained, and since the partial emitter layers 5 and 7 and the etching stopper layer 6 are both ternary, they can be easily epitaxially grown. be able to. Furthermore, the partial emitter layers 5 and 7 are made of InA.
1GaP and the etching stop layer 6 is InGaP, In
GaAsP, AlGaAs or GaAs may be used, and tartaric acid may be used as an etchant.

FIG. 3 is a sectional view of another embodiment. In this embodiment, the etching stopper layer 13 made of InGaAsP is laminated on the base layer 4, and the emitter layer 15 made of InGaP is laminated thereon.
3 constitutes the guard ring 14. In this embodiment, the guard ring 14 is composed only of the etching stopper layer 13, and the number of layers stacked on the base layer 4 is further reduced as compared with the above-described embodiment, and the stacking process is simplified.

[0011]

As described above, according to the present invention, G
In a heterojunction bipolar transistor having a collector layer, a base layer and an emitter layer sequentially laminated on an aAs substrate and having a guard ring layer, the emitter layer is an etching stop layer inserted at a desired position and the upper and lower sides of the etching stop layer. The guard ring layer is composed of a partial emitter layer located on the base layer side of the etching stopper layer or a partial emitter layer located on the base layer side of the etching stopper layer and the etching stopper layer. Alternatively, the emitter layer is composed of an etching stopper layer having a desired thickness and an upper partial emitter layer formed through the etching stopper layer, and the guard ring layer is the etching stopper layer. It is possible to accurately control the thickness of the guard ring layer composed of There is an excellent effect that that.

[Brief description of drawings]

FIG. 1A to FIG. 1D are manufacturing process explanatory diagrams of an embodiment of a heterojunction bipolar transistor according to the present invention.

FIG. 2 is a diagram showing a relationship between a current gain and an emitter size when the guard ring thickness is 30 nm in the above embodiment.

FIG. 3 is a cross-sectional view of another embodiment according to the present invention.

[Explanation of symbols]

 1 substrate 2 contact layer 3 collector layer 4 base layer 5 and 7 partial emitter layer 6 and 13 etching stop layer 8 cap layer 9 and 14 guard ring 10 collector electrode 11 base electrode 12 emitter electrode 15 emitter layer

Claims (2)

[Claims] 1. A heterojunction bipolar transistor having a guard ring layer, which is formed by sequentially stacking a collector layer, a base layer, and an emitter layer on a GaAs substrate.
The emitter layer is composed of an etching stopper layer inserted at a desired position and two partial emitter layers above and below the etching stopper layer, and the guard ring layer is a partial emitter layer on the base layer side of the etching stopper layer or A heterojunction bipolar transistor comprising: the etching stop layer and a partial emitter layer on the base layer side of the etching stop layer. 2. A heterojunction bipolar transistor having a guard ring layer, which is formed by sequentially stacking a collector layer, a base layer and an emitter layer on a GaAs substrate.
The emitter layer is composed of an etching stopper layer having a desired thickness on the base layer and an upper partial emitter layer formed through the etching stopper layer, and the guard ring layer is composed of the etching stopper layer. And a heterojunction bipolar transistor.