JPH07253919A - Image memory device - Google Patents

Abstract

PURPOSE:To provide the image memory device which is high in memory use efficiency and reducible in hardware quantity. CONSTITUTION:When an address correcting circuit 1 makes corrections for the memory address generation of peripheral pixels from the input coordinates 41 of a center pixel and outputs the result to an address converter 11, the address converter 11 performs address conversion for reducing an unused area. Memories A21-A24 where plural pixels are allocated to the same addresses outputs data corresponding to the memory addresses to data buses 81-88 in read mode and inputs them from the data buses 81-88 in write mode. A selector 31 selects necessary peripheral pixel values from the read data and outputs them as data outputs 91-96.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory device used for video equipment, image processing devices and the like.

[0002]

2. Description of the Related Art A high-definition image circuit applied to a video equipment or an image processing apparatus is provided with an image memory having a size of one high-definition image frame.
Conventionally, as such an image memory, as shown in FIG.
It is realized that pixels are sequentially stored pixel by pixel, and six pixels around an address indicated by a horizontal coordinate X and a vertical coordinate Y are randomly read at the same time.

In the figure, the size required as a memory for one high-definition image frame is 1 in the horizontal direction.
920 pixels, 1035 lines in the vertical direction, and the number of bits per pixel is 10 bits. Also, the six surrounding pixels are
As shown in FIG. 9, it is defined as 6 pixels including the surrounding 5 white pixels 201 centered on the black pixel indicated by the integer value of the read address.

FIG. 10 shows a block configuration of a conventional image memory device. In the figure, 101 is an address correction circuit, which receives the address input 151 and outputs the memory addresses 161 to 168. 111-118
Is a memory B, which receives memory addresses 161 to 168 and control signals 171 to 178 as input, and data buses 181 to 181.
Input / output 188. A selector 121 receives the address input 151 and the data buses 181 to 188 and outputs the data outputs 191 to 196.

FIG. 11 shows a conventional memory map. It is assumed that the memory address is two-dimensionally assigned, and the horizontal coordinate X is assigned to the lower address and the vertical coordinate Y is assigned to the upper address.

Reference numeral 202 shown by a hatched portion is an effective image area used by the memory. 1035 vertically
Since there are lines, up to 2047 vertical addresses are required. Therefore, 203 shown in white in the drawing is an unused area of the memory.

FIG. 12 shows the conventional bank allocation. According to this, the image memory is divided into blocks 204 in units of 8 pixels each consisting of 4 horizontal pixels × 2 vertical lines, and 8 banks are allocated to 8 pixels of each block 204. The same memory address is assigned to 8 pixels in the same block. Therefore, the pixel data indicated by the (X, Y) coordinates is held at the address of the corresponding block in the memory of the corresponding bank number.

The memories B111 to B118 are assigned to the banks 1 to 8 of the memory, respectively.
Each of the memories B111 to B118 of these eight banks has 51
A memory of 2K words x 10 bits is required, and each memory B is composed of 6 SRAMs of 256K words x 4 bits.

According to the above-mentioned configuration of 12 bits per pixel, 2 bits become an unused area, as is apparent from FIG.

Next, the operation of the above conventional example will be described separately for writing and reading. First, the operation when writing the pixel data of the coordinates (X, Y) will be described. The address input 151 is expressed by X and Y, and is expressed by the numerical expressions 1 and 2 in binary expression.

[0011]

[Equation 1]

[0012]

[Equation 2]

The address correction 101 has an address input 15
The number 1 and the number 2 of 1 are received, and the X address is corrected to the number 4 by adding the values shown in FIG. 13 based on the value of the number 3 for each bank.

[0014]

[Equation 3]

[0015]

[Equation 4]

Further, also for the Y address, the values shown in FIG. 14 are added based on the value of the expression 5 to correct it to the expression 6, and the expression 7 is output as the memory addresses 161 to 168 for each bank. .

[0017]

[Equation 5]

[0018]

[Equation 6]

[0019]

[Equation 7]

In the memories B111 to 118, the numbers 5 and 3 are used.
Image data to be written is applied to the data bus (one of 181 to 188) of the bank (one of the eight memories B) determined by By setting the control signal (one of 171 to 178) of the corresponding bank to the write state, the image data is written to the addresses indicated by the memory addresses 161 to 168.

Next, the read operation for reading the six pixels around the coordinate (X, Y) will be described. Here, the address of each bank may differ depending on the values of X and Y. For example, when the central pixel is in bank 5, the addresses in the X direction of banks 4 and 8 are those obtained by subtracting 1. If the central pixel is in bank 8, the address of banks 1 and 5 in the X direction is 1.
It will be the sum. Alternatively, when the central pixel is in bank 2, the Y-direction address of banks 5, 6, and 7 is subtracted by one.

The address correction 101 operates in the same manner as at the time of writing. That is, the address correction 101 receives the equations 1 and 2 from the address input 151 and adds the values shown in FIG. 13 based on the value of the equation 3 for each bank to obtain the equation 4. Next, the value shown in FIG. 14 is added based on the value of the equation 5 to obtain the equation 6, and the equation 7 is changed to the memory address 16 for each bank.
1 to 168 are output.

The memories B111 to B118 use the control signal 1
71 to 178 read status and memory addresses 161-1
8 peripheral pixels are read by 68, and data bus 181
To 188. The selector 121 selects the peripheral 6-pixel element to be read from the 8 pixels by the equations 5 and 3 of the address input, and outputs it to the data outputs 191 to 198.

As described above, in the above-mentioned conventional image memory device, the image is divided into 8 banks, the address is corrected for each bank, and 6 pixels are selected from the read 8 pixels. At the same time, they will lead.
Here, the memory requires 48 SRAMs of 256 K words × 4 bits.

[0025]

However, the conventional image memory device described above has a problem that the address space cannot be effectively used as shown in FIG. In addition, the bit widths of commercially available memories are usually 4, 8, and 16 bits, which do not match the pixel bit width of 10 bits, so that the memory cannot be used efficiently and the amount of hardware increases. There was a point.

The present invention has been made to solve such a conventional problem, and an object of the present invention is to provide an image memory device having a high memory use efficiency.

[0027]

In order to achieve the above object, an image memory device of the present invention is an image memory for storing image information having two-dimensional coordinates of X and Y. It is characterized in that the result of address conversion of the Y coordinate by the address converter is used as a memory address.

Further, the image memory stores image information having two-dimensional coordinates of X and Y, and is characterized in that a plurality of pixels are assigned to one memory address of one bank.

[0029]

Therefore, according to the present invention, the address converter performs the address conversion of the image data to reduce the bit width of the address, and as a result, the memory use efficiency is improved.

Further, by allocating a plurality of pixels to one memory address of one bank, one bank becomes a memory having a bit width of a plurality of pixels. by this,
The efficiency of memory use in the bit direction is improved, and the amount of hardware is reduced.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of an image memory device according to the present invention will be described below with reference to the accompanying drawings. In the following description, it is assumed that the HDTV image frame conforms to the above-mentioned FIG. That is, one pixel is sequentially written in raster order, and six peripheral pixels of an address indicated by coordinates (X, Y) are simultaneously randomly read. The memory size for one frame is 1920 pixels in the horizontal direction and vertically in the vertical direction. 10
35 lines, the number of bits per pixel is 10 bits.

FIG. 1 shows the configuration of an embodiment of the present invention. In the figure, reference numeral 1 is an address correction circuit, which receives an address input 41 as an input and stores memory addresses 51 to 54.
Is output. An address converter 11 receives the memory addresses 51 to 54 as inputs and outputs the memory addresses 61 to 64 after the address conversion. 21 to 24 are memories A
And memory addresses 61 to 64 and control signals 71 to 7
4 is an input and the data buses 81 to 88 are input / output.
A selector 31 receives the address input 41 and the data buses 81 to 88, and outputs the data outputs 91 to 96.

FIG. 2 is a functional explanatory diagram of the address converter 11. Further, FIG. 3 shows a memory map after address conversion.

As shown in FIG. 3, in the address conversion of the present invention, the pixel values of the 1025th line and after in the vertical direction are assigned to the address unused area after 1921 pixels in the horizontal direction. That is, when the image data is composed of the effective image area 32 and the effective image area 33 before the address conversion, the effective image area 33 before the address conversion is address-converted so as to be allocated to the horizontal address unused area, and the address conversion is performed. A subsequent effective image area 34 is formed. This makes it possible to delete the addresses on and after the 1025th line in the vertical direction, resulting in the memory map shown in FIG. 4, and the memory unused area 35 is greatly reduced.

Next, FIG. 5 shows bank assignment in this embodiment. The image memory is divided into blocks 55 in units of 8 pixels each consisting of 4 horizontal pixels and 2 vertical lines. One memory address is assigned to one block 55. Then, 4 banks are assigned to 8 pixels in the block. That is, one block 55 has a 4-bank configuration. At this time, two pixels are assigned to one address in one bank. Here, in the banks 1, 2, 3, and 4, the memory A shown in FIG.
21, 22, 23 and 34 are assigned respectively.

When configured as described above, each of the four banks of memories A21 to 24 requires a capacity of 256 K words × 20 bits. This is for each memory A, for example, 256K
It is realized by configuring with 5 SRAMs each having 4 words. With the above configuration, as shown in FIG. 4, 20 bits per 2 pixels are secured in the bit direction, and there are no unused bits.

Next, the operation of the above embodiment will be described separately for writing and reading. First, as the operation at the time of writing, the case of writing the stroke number data of the coordinates (X, Y) in the memory will be described. The address correction circuit 1 receives the number 1 and the number 2 from the address input 41 and adds the correction values shown in FIG. 6 based on the value of the number 3 for each bank to obtain the corrected X address number 4. Then, the correction value shown in FIG. 7 is added based on the value of the equation 5 to obtain the correction Y address number 6, and the correction address number 7 is output as the memory addresses 51 to 54 for each bank.

The address converter 11 performs the following conversion on each of the input memory addresses 51 to 54, and outputs the memory addresses Ad after the address conversion as 61 to 6
Output as 4.

That is, when the expression 8 is satisfied, the memory address Ad after the address conversion is output as the expression 9, and on the contrary, when the expression 10 is satisfied, the memory address Ad after the address conversion is calculated. Output as 11.

[0040]

[Equation 8]

[0041]

[Equation 9]

[0042]

[Equation 10]

[0043]

[Equation 11]

In the memories A21 to 24, the data buses (81 to 82, 83 to 84, 85 to 86, 87 to 8) of the banks (one of the four memories A) determined by the equation 12 are used.
Image data to be written to any one of 8) and the control signal (any of 71 to 74) of the bank is set to the write state, so that the image data is written to the addresses indicated by the memory addresses 61 to 64.

[0045]

[Equation 12]

Next, as a read operation, coordinates (X, Y)
A case of reading out 6 pixels in the vicinity of will be described. Here, the address of each bank may differ depending on the values of X and Y.
For example, when the central pixel is at the left pixel of bank 3, the addresses in the X direction of banks 2 and 4 are those obtained by subtracting 1. When the central pixel is located at the right pixel of bank 4, the addresses in the X direction of banks 1 and 3 are incremented by one.
If the center pixel is on the right pixel of bank 1, then bank 3,
The address in the Y direction of 4 is the address subtracted by 1.

The address correction circuit 1 operates similarly to the write operation. That is, the address correction circuit 1 receives the numbers 1 and 2 from the address input 41, and the number 3 for each bank.
Equation 4 is obtained by adding the values shown in FIG. Further, the value shown in FIG. 7 is added based on the value of the equation 5 to obtain the equation 6, and the equation 7 is output as the memory addresses 51 to 54 for each bank.

In the address converter 11, the following conversion is performed for each of the memory addresses 51 to 54 in the same manner as at the time of writing, and the memory addresses Ad after address conversion are 61 to 61.
Output as 64.

That is, when the equation 13 is satisfied,
The memory address Ad after the address conversion is output as the equation 14, and on the contrary, when the expression 15 is satisfied, the memory address Ad after the address translation is output as the equation 16.

[0050]

[Equation 13]

[0051]

[Equation 14]

[0052]

[Equation 15]

[0053]

[Equation 16]

The memories A21 to 24 are connected to the control signals 71 to 7 respectively.
8 read state and memory address 61 after address conversion
~ 68 to read the peripheral 8 stroke elements, data bus 8
Output to 1 to 88. The selector 31 selects the peripheral 6 pixels to be read from the 8 pixels according to the number of address inputs 5 and 3, and outputs them to the data outputs 91 to 98.

As described above, in the image memory device of the above-described embodiment, by providing the address conversion 11, the memory addresses 51 to 54 are 19 bits, but the memory addresses 61 to 64 after the address conversion are 18 bits. Therefore, the address space can be reduced by 1 bit, and the use efficiency of the memory can be improved.

Further, in the image memory device of the above-mentioned embodiment, by assigning a plurality of pixels to one memory address of one bank in the memories A21 to 24, the
One bank can be a memory having a bit width corresponding to a plurality of pixels, the efficiency of use of the memory in the bit direction can be improved, and the efficiency of use of the memory can be improved.

As described above, the number of memories, which was 48 in the conventional example, can be reduced to 20 in the present embodiment, and the circuit can be reduced by substituting the selector for address conversion with hardware.

[0058]

As is apparent from the above-described embodiment, the present invention can reduce the memory address space by providing the address conversion, and can improve the memory use efficiency. Therefore, the amount of hardware can be reduced.

Further, according to the present invention, by allocating a plurality of pixels to one memory address of one bank, the efficiency of use of the memory in the bit direction is improved and the efficiency of use of the memory can be improved. Therefore, the amount of hardware can be reduced.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an image memory device according to the present invention.

FIG. 2 is a functional explanatory diagram of the address translator of FIG.

FIG. 3 is an explanatory diagram of an address conversion method of the present invention.

FIG. 4 is a memory map of the present invention.

FIG. 5 is an explanatory diagram of bank allocation according to the present invention.

FIG. 6 is a diagram showing an example of an X address addition value used in the address correction of the present invention.

FIG. 7 is a diagram showing an example of a Y address added value used in the address correction of the present invention.

FIG. 8 is an explanatory diagram of image data size of one high-definition image frame and peripheral pixels.

FIG. 9 is an explanatory diagram of peripheral pixels

FIG. 10 is a block configuration diagram of a conventional image memory device.

FIG. 11 is a memory map of a conventional image memory device.

FIG. 12 is an explanatory diagram of bank allocation of a conventional image memory device.

FIG. 13 is a diagram showing a correction addition value of an X address of a conventional image memory device.

FIG. 14 is a diagram showing a correction addition value of a Y address of a conventional image memory device.

[Explanation of symbols]

 1 address correction 11 address conversion 21-24 memory A 31 selector 41 address input 51-54 memory address 61-64 memory address after address conversion 71 control signal 1 72 control signal 2 73 control signal 3 74 control signal 4 81 data bus 1 82 data bus 2 83 data bus 3 84 data bus 4 85 data bus 5 86 data bus 6 87 data bus 7 88 data bus 8 91 data output 1 92 data output 2 93 data output 3 94 data output 4 95 data output 5 96 data Output 6

Claims (2)

[Claims] 1. An image memory for storing image information having two-dimensional coordinates of X and Y, wherein the result of address conversion of the X and Y coordinates of the image information by an address converter is used as a memory address. Image memory device. 2. An image memory device for storing image information having two-dimensional coordinates of X and Y, wherein a plurality of pixels are assigned to one memory address of one bank.