JPH0232478A - Image memory for parallel access - Google Patents

Abstract

PURPOSE: To speedily and parallelly access area structure by expressing data corresponding to one partial area by a scanning line number and a pixel position number so as to reduce picture memories. CONSTITUTION: The position of each pixel of a picture is expressed by the scanning line number Z and the pixel position number P. The picture memory is provided with one storing place with respect to each pixel and distributed to nine levels. One memory address is capable of address-specify a storing place in the nine different level pictures 0 to 8 by one address consisting of L with respect to the row of the memory and C with respect to the column of the memory. At the time of reading a matrix within a dashed line, the picture coordinate values Z=2 and P=4 of a central pixel become addresses and belonging pixel data is simultaneously read to specify storing places positioned at different level surfaces are specified by different addresses. These relations are shown at (b) and (c).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image memory for parallel access of area structures.

BACKGROUND OF THE INVENTION Processing of data relating to image display It is often necessary to store images or image data, in particular for pattern recognition. In this case, there is also a need to quickly access data of selectable partial areas that are part of the image.

In a known method for storing and recalling binary data for binary display of images (European Patent Application Publication No. 0157274), a number of image memories corresponding to the number of pixels of a partial area are provided, and various types of image memory are provided. Can be accessed simultaneously with changing addresses. For example, if a partial area consisting of 3.times.5 pixels is provided, it is necessary to arrange memories for nine pixels in the known method. Therefore, considerably more image memory is required than is originally required to store the image.

OBJECTS TO BE SOLVED BY THE INVENTION An object of the present invention is to provide an image memory that allows parallel access of area structures without providing storage locations several times larger than originally required.

Means for solving the problem and effects of the invention The above-mentioned problem is solved according to the invention by the features described in the characterizing part of claim 1. An image memory according to the invention having the configuration according to the characterizing part of claim 1 is characterized in that the image memory according to the invention is configured such that one sub-area can be fixed by supplying an address, for example a scanning line number and a pixel position number within one scanning line. It has the advantage that it is possible to read data corresponding to. A very fast readout is therefore possible, which is a great advantage in particular in the case of (on-line) image data processing synchronous with the generation of image data in a television system.

Advantageous embodiments are set out in the other claims.

In an advantageous embodiment, one bit may be stored in each storage location, or multiple bits, depending on whether a binary image, an image with multiple shades of gray, or a color image is stored.
t may be memorized.

In one embodiment of the invention, the number of level planes corresponds to the number of pixels of the subregion. Therefore, when reading out a 6×6 pixel matrix at the same time, nine level planes are provided.

In the case of 4×4 pixels, a level plane of 1 B is provided.

However, within the scope of the invention, as long as the requirements for readout speed permit, a smaller number of level planes than the number of pixels corresponding to one partial area is provided, and the unreadout data is readout by repeated accesses to the memory. It is also possible.

Description of examples Next, the present invention will be explained in detail using examples and drawings.

FIG. 1 shows the distribution of individual pixel data into various level planes of memory.

For the sake of simplicity, only a portion of the memory and thus of the image is shown in FIG. 1a). The position of each pixel in the image is represented by a scanning line number Z and a pixel position number P. The image memory has one storage location for each pixel. Memory locations are distributed into nine levels. A memory address consists of the bottom for a row of memory and the C for a column of memory. For example, L=Q and C=1 are one address. One such address can address memory locations in eight of nine mutually different levels. However, address generation is done so that different levels can be addressed with different addresses. In the table, the area surrounded by thick solid lines represents the memory, and the boundaries of the image areas are represented by broken lines.

For example, if a subarea in the form of a 5x6 matrix as shown in FIG. 1b) is to be read from memory,
The address of the pixel at the center of the matrix is read out as the address of this matrix. For example, the center pixel is Z=0,
When reading a matrix with P=6, L=
0, C=2 address specification. In this case level plane 4 is addressed. As can be seen from FIG. 1, other pixels are also distributed corresponding to the respective level planes. Therefore, the data of these pixels can be read out simultaneously.

For example, it is assumed that a square IJ box surrounded by a dashed line is to be read out. The image coordinate value of the center pixel of the matrix is z
−2, P = 4. M) Pixels belonging to IJ boxes are distributed and stored on all levels of the memory. Therefore, the data of these pixels can be read out simultaneously. However, this requires that storage locations located on different level planes be addressed by different addresses. The storage location located on level plane 7.8 can be addressed by L-0, C=1, level plane 6 can be addressed by L=o, C=1, and level plane 1. 2.4.5 is L=L C=1
Level plane 0.3 can be addressed by L=1, c=2.

The internal value of the pixel matrix is 1 on the memory level side.
Such a relationship between memory row L1 memory column C is shown in FIG. 1C).

Comparing the first example (z ``'' 0, p ``'' 6) and the second example (2=2, P=4), the arrangement between the pixel matrix position A or A and the memory level plane is I see that it's different. In the first example, the data for pixel A is stored on level plane 0, and in the second example, the data for pixel A is stored on level plane 7.
is stored in Therefore, it may be necessary to cyclically swap the positions of pixels in the IJ box horizontally and/or vertically before reading data.

In the embodiment of FIG. 2, the digital memory 21 is on the level plane =
[ ] or = 8t- equipped. Memory 21 is RAM
It is. For example, to store a binary image of 300×400 pixels, a total capacity of 120,000 blt is required.

Each level plane of memory 21 can be addressed by an address generator 22.23. To carry out this addressing, the outputs of the address generators 22, 23 are connected via address buses v3 to v8 to the address inputs of the storage level plane. A pixel position number P is supplied to the input 24 of the address generator 22, and the address generator 23
The scanning line number Z is supplied to the input 25 of the . Coordinate p,
Since z is also supplied to other parts of the circuit, the inputs 24, 25 are shown in several places in FIG.

A write signal is supplied to the input 26 for writing the image data. The write signal is supplied to address generators 22, 23, storage level surface selection circuit 29, and AND circuit 60 via line V1.

via the address generator 22.23.

The image signal to be stored is supplied to an input 28.

The storage level plane selection circuit 29 determines on which level plane the pixel data is to be written.

The address generators 22 and 23 send the write signal to the input side 26.
The same address is output from all output sides of each address generator 22, 25. Therefore, either output side of the address generator 22"
From 6t v7 + v8, memory column address C=INT((P+1)/l) for writing image data.
is output, and the output side v3. of the address generator 23 is output. v4゜From V5, the corresponding memory row address rNT(, (Z
+1)/3) is output.

For read operations, a read signal is applied to the address generator 22, 230 input 27.

When a read signal is applied to the address generators 22.25, the respective outputs of each address generator 22.23 output mutually different addresses.

The corresponding diagram is shown in detail in FIG.

In order to correctly arrange the data read from the memory 21 in positions A to A (Fig. 1b) in the matrix,
A circuit device consisting of two crossbars 1 and 32 is provided. The crossbar 31 is used to cyclically exchange pixels in the horizontal direction, and is controlled by a pixel position number P via a control circuit 33. The crossbar 52 is used for cyclical exchange in the vertical direction, and is connected to the control circuit 3 from the scanning line number ZK.
4. The output side of the crossbar 32 is connected to an output register 65 corresponding to the matrix.

The data read each time is written to the output register 35 and used for the next processing.

The algorithms used to derive the address, write control signals, and switching signals consisting of P and Z are stored in each circuit 22, 23, 29, 33.54 of FIG. The algorithm can be implemented using look-up tables or, if time permits, by a computer.

To write the image data, a write signal is applied to the input 26. The write level surface selection circuit 29 is activated by the write signal, the address generators 22 and 23 are switched to write address generation operation, and the AND circuit 30 operates based on the image signal B.
It is controlled to pass through. Image signal B AND circuit 30
is applied to all level surfaces through. Depending on the write control signal (write enable) generated by the write control circuit, i.e. the storage level surface selection circuit 29, the data corresponding to one pixel in each case is supplied to that level in synchronization with the image data stream. .

Thus, as shown in FIG. 1a), starting from P=Q, level plane 4 then level plane 5 then level plane 3 are addressed during scan line 2=0. This is repeated during the scan line Z=0. The corresponding addresses are L=Q, C=0, C-1 then C=2, and so on. During the write period of data for scan line z=1, starting from pixel position number P=[l, level plane 7, level plane 8, and then level plane 6 are addressed. This addressing corresponds to addressing during the scan line Z=[].

In this way, data from scan line z=2 is written on level plane 1.2.0. In the case of writing to scanning line Z=2, the address is composed of L=i and the continuous value of C.

All level planes of memory 21 are accessed in parallel to read out one matrix in each case (FIG. 1b)). As explained in connection with FIG. 1a), the addresses necessary for the access are generated by address generators 22, 23. The data corresponding to each matrix read out from the memory 21 is taken out from the output side of the storage level plane and sent to the crossbar 3 via the connection lines V10 to V18.
1. Depending on the pixel position number P supplied to the input 24, the control circuit 33 generates an intersection control signal for the crossbar 31.

By this intersection control, the output lines V30 to V38 of the crossbar 31 are connected to the line V30 so that the read data of one matrix coincides with the position in the matrix in the vertical direction.
10 to V18. To make this connection, the control circuit 53 switches the intersection located on one of the binary output lines V40 to V42 into conduction each time depending on the pixel position number P. A voltage level is applied. For example, line V40
When voltage level 1 is applied to , the intersection of Vlo and VS0, the intersection of vll and VS2, or the intersection of V187 and V38 becomes conductive. This suppresses horizontal circular exchanges which are undesirable for subsequent processing.

On the other hand, if voltage level 1 is applied to line V41, the intersections shown as black dots in FIG.
0 is connected, and the line V12 and line V51 are connected. Similarly, other lines are exchanged cyclically. In this way, for example, in the matrix surrounded by the dashed line in FIG. 1a), the intermediate rows successively take on the values 1.2.0.

In this case, the cyclic exchange in the vertical direction is carried out by the control circuit 34 via the control lines V51 P VS21 V2O
This is done by the crossbar 32, which is controlled depending on. The intersection points in the matrix surrounded by dashed lines that are switched into conduction for vertical cyclic exchange are represented in black, and the signal corresponding to this conduction state is output via line V52.

Output lines V20 to V28 of the crossbar 52 are connected to the input side of the output register 35.

The storage location of the output register 35 is indicated manually in accordance with FIG. 1b). The control input 36 of the output register 65 is supplied with a so-called enable pulse. The time position of the enable pulse is selected such that, even if a time lag occurs between the input signals, the input signals are written regardless of this lag. Depending on the requirements of the individual case, logic circuits not shown in FIG. 2 are connected to the output register 35. This logic circuit is used for subsequent processing of the data of the matrix read from the memory, for example pattern recognition processing.

[Brief explanation of the drawing]

1a), b) and c) show the distribution of individual pixels into different levels of the memory; FIG. 2 is a block circuit diagram of an embodiment of the memory according to the invention; FIG. 21...Digital memory, 22.23...Address generator, 29...Storage level surface selection circuit, 61°32
...Crossbar, 33.34...Control circuit, 35...
・Output register.

Claims (1)

[Claims] 1. In an image memory for parallel access of an area structure, one storage location is provided for data corresponding to one pixel in each case, and the storage locations are arranged in a plurality of levels. each one of the storage locations located on each of the level planes can be accessed simultaneously, and the data of the pixels corresponding to each sub-region of the input image are stored in mutually different level planes; An image memory for parallel access characterized by: 2. The image memory for parallel access according to claim 1, wherein each storage location has a capacity of at least 1 bit. 3. An address forming device is provided which is supplied with data representing the position of a partial area of the image and derives one address for each level from this data, and the output side of the memory location of each level plane is set to correspond to the partial area of the image. is connected to the output register via a switching device controllable by data representative of the position of the address forming device, which is switchable between various algorithms for performing a write or read operation, Image memory for parallel access according to claim 1, characterized in that it is possible to store and read out from said table by scan line number and pixel position number (Z, P).