JPH07253897A - I/o circuit - Google Patents

Abstract

PURPOSE:To improve the I/O circuit which is used in an uninterruptible system normally continuing the operation and to enable exchange of a board with the I/O circuit using a CMOS transistor without affecting the operation of the uninterruptible system when the board is exchanged. CONSTITUTION:In the I/O circuit using the CMOS transistor as an output buffer 21, the P-type MOS transistor 22 comprising the output buffer 21 has its back gate BG 1 pulled outside and given an electric potential different from its sources S1.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to I / O circuits.
In particular, it is used for non-stop systems that continue to operate all the time,
The present invention relates to an improvement that enables board replacement without affecting the operation of the non-stop system when replacing a board having I / O circuits using CMOS transistors.

[0002]

[Prior art]

Refer to FIG. 3. FIG. 3 is a configuration diagram of a system having an I / O circuit configured using conventional CMOS transistors. In FIG. 3, 1 is a main board on which a semiconductor device such as a CPU is mounted, and 15 is a first DC power supply for supplying power to the semiconductor device and the like mounted on the main board 1. Reference numeral 2 is a sub board mounted on the main board 1 and functioning as an I / O circuit. Reference numeral 21 is an output buffer of the I / O circuit mounted on the sub board 2.
Is a second DC power source for supplying power to the semiconductor device mounted on the sub board 2. The output buffer 21 is a P-type MO
A CMOS transistor including an S-transistor 22 and an N-type MOS transistor 23 is used to
The power is supplied from the DC power supply 25 and the output is sent to the external terminal 13. VDD and VSS are potentials applied to the output buffer 21 from the second DC power supply 25. BG1 and BG2 are back gates of the P-type MOS transistor 22 and the N-type MOS transistor 23, respectively, and are connected to the respective sources S1 and S2.

Reference numeral 3 denotes another sub board which is constructed similarly to the sub board 2 and functions as an I / O circuit mounted on the main board 1, and 31 is mounted on the other sub board 3. The reference numeral 35 designates another output buffer of the I / O circuit, and a reference numeral 35 designates a third DC power supply for supplying power to the semiconductor device mounted on the other sub board 3. The other output buffer 31 is supplied with power from the third DC power supply 35, and outputs to the same external terminal 13 that the output buffer 21 outputs.

The sub-board 2 and the other sub-board 3 are arranged in parallel, and even if one of the sub-board 2 and the other sub-board 3 deteriorates or stops functioning, the other one takes over the function and the operation is continued as a whole. Has become.

[0005]

By the way, when the second power supply 25 is cut off for repair or replacement of the sub board 2, the potential VDD applied to the output buffer 21 becomes 0V which is the same as the potential VSS. At this time, when a signal is output from the other sub-board 3 to the external terminal 13, the P-type MOS transistor 22 has a parasitic diode 221 between the drain D1 and the back gate BG1.
Output signal of the other power supply 35 passes through the other output buffer 31 to the output terminal X of the output buffer 21, flows in the forward direction of the parasitic diode 221, and the back gate B
The potential V1 (0V) is reached from G1 via the source S1 of the P-type MOS transistor 22. If this current is greater than or equal to the allowable current of the parasitic diode 221, the parasitic diode 221 may be destroyed. That is, the CMOS transistor of the output buffer 21 is exposed to destruction.

An object of the present invention is to solve this problem, and for a multi-power supply system which prevents the CMOS transistors constituting the output buffer 21 from being destroyed even when the second power supply 25 of the sub board 2 is cut off. It is to provide an I / O circuit.

[0007]

SUMMARY OF THE INVENTION The above object is to realize a CMOS.
I using transistor as output buffer (21)
In the / O circuit, the P-type MOS transistor (22) forming the output buffer (21) is the P-type MO transistor.
The back gate (BG1) of the S transistor (22) is pulled out to the outside, and the P-type MOS transistor (2)
This is achieved by an I / O circuit formed so that it can have a potential different from that of the source (S1) of 2).

The back gate (BG1) is connected to the first power source (15), and the source (S1) is connected.
Is connected to a second power supply (25) and the potential of the first power supply (15) is equal to or higher than the potential of the second power supply (25), the P-type MOS transistor ( The reverse voltage is only applied to the parasitic diode (221) of 22), and since the forward current does not flow, the output buffer (21) is not damaged.

[0009]

Operation: Normally, the back gate B of the CMOS transistor
G1 is set to the same potential as the source S1, but the I / O circuit according to the present invention is a CMOS that constitutes the output buffer 21.
The back gate BG1 of the P-type transistor 22 of the transistors is drawn to the outside. For this reason, the back gate BG1 is not the same potential as the source S1 of the P-type transistor 22 and can be given another potential. Even if the power source of the output buffer 21 is turned off for maintenance and the source S1 of the P-type transistor 22 becomes 0V, the potential applied from the outside to the output terminal X if the back gate BG1 is held at another potential. If the potential applied to the back gate BG1 is the same or higher, no forward current flows through the parasitic diode 221 of the P-type transistor 22. Therefore, even if the power is turned off during maintenance and inspection, the CMOS transistor is not accidentally destroyed.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An I / O circuit according to an embodiment of the present invention will be described in more detail below with reference to the drawings.

FIG. 1 is a block diagram of a system having an I / O circuit according to an embodiment of the present invention. In FIG. 1, 1 is a main board on which a semiconductor device such as a CPU is mounted, and 15 is a first DC power supply for supplying power to the semiconductor device and the like mounted on the main board 1. 2 is a sub board that functions as an I / O circuit mounted on the main board 1.
Reference numeral 1 is an output buffer of the I / O circuit mounted on the sub board 2, and 25 is a second DC power supply for supplying power to the semiconductor device mounted on the sub board 2. The output buffer 21 is configured by using a CMOS transistor composed of a P-type MOS transistor 22 and an N-type MOS transistor 23, is supplied with power from the second DC power supply 25, and outputs an output from the output point X to the external terminal 13. . VDD and VSS
Is a potential applied from the second DC power supply 25 to the output buffer 21.

Similar to the sub board 2, 3 is another sub board which functions as an I / O circuit mounted on the main board 1, and 31 is an I / O mounted on the other sub board 3. Reference numeral 35 is another output buffer of the circuit, and reference numeral 35 is a third DC power supply for supplying power to the semiconductor device mounted on another sub board 3. The other output buffer 31 is supplied with power from the third DC power supply 35, and outputs to the same external terminal 13 that the output buffer 21 outputs.

BG1 and BG2 are the back gate of the P-type MOS transistor 22 and the back gate of the N-type MOS transistor 23, respectively. The back gate BG2 of the N-type MOS transistor 23 is the N-type MOS transistor 2 respectively.
3 is connected to the source S2, but the back gate BG1 of the P-type MOS transistor 22 is not connected to the source S1 of the P-type MOS transistor 22 and is pulled out to the outside, so that the sub-board 2 is repaired or replaced. Therefore, even if the power supply 25 is cut off, BG1 does not become 0V because it is supplied from the first power supply 15 of the main board 1, so that no current flows through the parasitic diode.

The other back gate BG3 of the other P-type MOS transistor 32 of the other output buffer 31 is also a P-type MOS.
Since it is pulled out to the outside without being connected to the source of the transistor 32, BG3 is supplied from the first power source 15 of the main board 1 even if the power source 35 is cut off for repair or replacement of the sub board 3. Is not 0V,
Therefore, no current flows through the parasitic diode.

The sub-board 2 and the other sub-board 3 are arranged in parallel, and even if one of the sub-board 2 and the other sub-function is deteriorated or stopped, the other one takes over the function and the operation is continued as a whole. Has become.

See FIG. 2. FIG. 2 shows a CMOS used in the I / O circuit according to this embodiment.
It is a schematic diagram of a cross section of a transistor. In FIG. 2, P-
A P-type transistor is formed in an N-well formed on the substrate, and S1, D1, G1 and BG1 are the source, drain, gate and back gate of the P-type transistor, respectively. An N-type transistor is formed in the P-well, and S2, D2, G2 and BG2 are the source, drain, gate and back gate of the N-type transistor, respectively. When this CMOS transistor is used as an output buffer, point A where G1 and G2 are commonly connected becomes an input terminal, and point X where D1 and D2 are commonly connected becomes an output terminal. The potential VDD is applied to S1, and the potential VSS (ground, 0V) is applied to the location where S2 and the P- substrate are commonly connected.

221 and 231 are the CMOSs, respectively.
It is a parasitic diode of a P-type MOS transistor and an N-type MOS transistor which are necessarily formed in the layer structure of the transistor. The parasitic diode 221 of the P-type MOS transistor has a diode function between the drain D1 of the P-type transistor and the back gate BG1. The back gate BG1 is drawn to the outside, so that it can be applied with a potential different from that of S1.

With this configuration, if a potential VDD is 0V and a potential is externally applied to the output terminal X point, is this potential equal to the potential applied to the back gate BG1? Alternatively, when it is lowered, the parasitic diode 221 does not conduct, and the CMOS transistor is not destroyed. And maintenance can be performed without stopping the non-stop system.

Furthermore, the present invention can be used to directly connect the outputs of LSIs operating with different power supply voltages such as 3.3V and 5.0V to form a bus.

FIG. 5 shows an example of the prior art in which the outputs of LSIs operating at different power supply voltages are directly connected to each other. In this case, when the driver 31 of the LSI operating at a high power supply voltage drives the driver 21 of the LSI operating at a low power supply voltage (when the driver 31 is in the drive state and the driver 21 is in the non-drive state), the low power supply voltage is low. A current flows through the parasitic diode of the driver 21 of the LSI that operates in. V _X is V
This is because it is equal to or higher than _BG1 . As a result, power consumption may increase or the driver 21 may be destroyed.

FIG. 4 FIG. 4 shows an example in which the present invention is used to solve the above-mentioned drawbacks. In this way, the LS operating at a low power supply voltage
The BG1 potential of the I driver 21 is set to the high voltage power supply 3
When the voltage is equal to the voltage of 5, when the driver 31 is in the drive state and the driver 21 is in the non-drive state, the driver 21
No current flows through the parasitic diode of. V _X
Is equal to or lower than V _BG1 . Therefore, there is no possibility that the power consumption will increase or the driver 21 will be destroyed.

[0022]

As described above, the I / O according to the present invention
According to the O circuit, the back gate of the P-type MOS transistor of the CMOS transistors forming the output buffer of the I / O circuit is drawn to the outside,
It is formed so as to have a potential different from that of the source of the transistor. The back gate of this P-type MOS transistor is not the power source of this I / O circuit, but the I / O
By connecting to a power source whose potential is established even during maintenance of the circuit, it is possible to prevent the parasitic diode, which is necessarily formed in the P-type MOS transistor, from conducting in the forward direction. Therefore, the CMOS transistor is not destroyed, and maintenance can be performed without stopping the non-stop system.

Further, as shown in FIG. 4, a bus can be constructed by directly connecting the outputs of LSIs operating with different power supply voltages.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a system having an I / O circuit according to an embodiment of the present invention.

FIG. 2 is a CMO used in the I / O circuit according to the present embodiment.
It is a schematic diagram of a cross section of an S transistor.

FIG. 3 is a configuration diagram of a system having an I / O circuit according to a conventional technique.

FIG. 4 is a configuration diagram of a bus according to another embodiment of the present invention.

FIG. 5 is a configuration diagram of a bus according to a conventional technique.

[Explanation of symbols]

1 Main Board 2 Sub Board 3 Other Sub Board 13 External Terminal 15 First DC Power Supply 21 Output Buffer 22 P-type MOS Transistor 23 N-type MOS Transistor 25 Second DC Power Supply 31 Other Output Buffer 32 Other P-type MOS Transistor 35 Third DC power supply VDD / VSS Potential applied to output buffer S1, D1, G1, BG1 Source, drain, gate, back gate S2, D2, G2, BG2 N-type MOS transistor source of P-type MOS transistor , Drain, gate, back gate BG3 Back gate of other P-type MOS transistor A Input terminal X Output terminal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/088 H03K 19/0175

Claims (2)

[Claims] 1. An I / O circuit using a CMOS transistor as an output buffer (21), wherein a P-type MOS transistor (22) constituting the output buffer (21) is a P-type MOS transistor (22).
Back gate (BG1) of the
I / O circuit characterized in that it is formed so as to have a potential different from that of the source (S1) of the MOS transistor (22). 2. The back gate (BG1) is connected to a first power supply (15), the source (S1) is connected to a second power supply (25), and the first power supply (15) is connected to the first power supply (15). The electric potential is equal to or equal to the electric potential of the second power supply (25).
2. The I / O circuit according to claim 1, wherein the potential is higher than the potential of the power supply (25).