JPH0725060A - Optical printing head and manufacture thereof - Google Patents

Optical printing head and manufacture thereof

Info

Publication number
JPH0725060A
JPH0725060A JP15474193A JP15474193A JPH0725060A JP H0725060 A JPH0725060 A JP H0725060A JP 15474193 A JP15474193 A JP 15474193A JP 15474193 A JP15474193 A JP 15474193A JP H0725060 A JPH0725060 A JP H0725060A
Authority
JP
Japan
Prior art keywords
light emitting
emitting diode
metal
plating layer
array chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15474193A
Other languages
Japanese (ja)
Inventor
Katsunori Moritoki
克典 守時
Masaki Muto
正樹 武藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15474193A priority Critical patent/JPH0725060A/en
Publication of JPH0725060A publication Critical patent/JPH0725060A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To enhance the productivity and reliability of an optical printing head by a method wherein wire bonding is eliminated in a process for arranging and packaging a light-emitting diode array chip on a light transmittable board. CONSTITUTION:A plurality of electroconductor film 22 for circuit are arranged on the surface of a light transmittable board 21. On the light emitting surface side of a light emitting diode array chip 23, which is formed by integrating a plurality of light emitting diodes 24 in tandem, the metallic bumps 26 for the electrode terminals of the light-emitting diode are arranged. The light emitting diode array chip 23 is die-bonded onto the board 21 by turning facedown or under the condition that its light-emitting surface faces to the surface of the board and the metallic bumps 26 come into contact with the metal plating layer 27 of conductor film 22. The metallic bump 26 has the Young's modulus, which is higher than that of the metal plating layer 27. In addition, the film thickness of the metal plating layer 27 is larger than the fluctuating dimension of the height of the metallic bump 26.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子写真方式のプリン
タやディジタル複写機などに組み込まれて、一次元イメ
ージ情報の電気信号を一次元の光学画像に変換する光プ
リントヘッドおよびその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical print head which is incorporated in an electrophotographic printer, a digital copying machine or the like to convert an electric signal of one-dimensional image information into a one-dimensional optical image and a manufacturing method thereof. It is a thing.

【0002】[0002]

【従来の技術】ノンインパクトプリンタの書き込み手段
として好適な光プリントヘッドは、電子写真方式のプリ
ンタやディジタル複写機などに適用されている。電子写
真方式のプリンタには、1本の変調レーザ光を回転多面
鏡に当てて偏向させ、得られた偏向光を電子写真感光体
に照射させる方式のものや、発光ダイオードアレイから
輻射させた複数本の光をセルフォックレンズアレイで集
束し、電子写真感光体に照射させる方式のものなどがあ
る。後者は十分な光量を得ることができるのみならず並
列書き込みができ、かつ、光学系を小型に設計できるこ
とから、高速プリンタやパーソナルファクシミリなどに
適用されている。
2. Description of the Related Art An optical print head suitable as a writing means of a non-impact printer is applied to electrophotographic printers, digital copying machines and the like. In the electrophotographic printer, one modulated laser beam is applied to a rotary polygon mirror to be deflected, and the obtained deflected light is applied to an electrophotographic photosensitive member, or a plurality of light emitting diode arrays are radiated. For example, there is a system in which light from a book is focused by a SELFOC lens array and is applied to an electrophotographic photosensitive member. The latter has been applied to high-speed printers, personal facsimiles, etc. because it can write in parallel, can write in parallel, and can design the optical system in a small size.

【0003】発光ダイオードアレイを用いた光プリント
ヘッドに付属させる光学系には、等倍光学レンズたる集
束性ロッドレンズアレイや、光ファイバアレイ基板(特
開昭55−98879号公報)などがあり、後者はプリ
ンタを小型に構成できて比較的安価でもある。
As an optical system attached to an optical print head using a light emitting diode array, there are a converging rod lens array which is an equal-magnification optical lens, an optical fiber array substrate (JP-A-55-98879), and the like. The latter is also relatively inexpensive because the printer can be made compact.

【0004】従来の代表的な光プリントヘッドを図9お
よび図10を参照して説明すると、絶縁基板1上に回路
導体膜2およびダイボンド用導電性樹脂層3を介してダ
イボンドされている複数個の発光ダイオードアレイチッ
プ4は、直線状に並んでいる。各発光ダイオードアレイ
チップ4は、単結晶半導体基板にモノリシックにつくり
込まれた複数の発光ダイオード5と、その電極端子6と
を有している。絶縁基板1上には駆動用IC7が、発光
ダイオードアレイチップ4と同様にダイボンドされてお
り、それぞれの電極端子6、8が金属ワイヤ9によって
相互にワイヤボンドされている。発光ダイオード5の出
力光は、集束性ロッドレンズアレイ10を通じてとり出
され、焦点11で結像する。12はシャーシを示す。
A typical conventional optical print head will be described with reference to FIGS. 9 and 10. A plurality of die-bonded substrates are formed on an insulating substrate 1 through a circuit conductor film 2 and a die-bonding conductive resin layer 3. The light emitting diode array chips 4 are arranged in a straight line. Each light emitting diode array chip 4 has a plurality of light emitting diodes 5 monolithically formed on a single crystal semiconductor substrate and its electrode terminals 6. A driving IC 7 is die-bonded on the insulating substrate 1 similarly to the light emitting diode array chip 4, and the respective electrode terminals 6 and 8 are wire-bonded to each other by a metal wire 9. The output light of the light emitting diode 5 is taken out through the converging rod lens array 10 and forms an image at a focal point 11. Reference numeral 12 indicates a chassis.

【0005】外部端子13を通じて入力された情報信号
は、回路用導体膜2および金属ワイヤ9を通じて駆動用
IC7に伝達され、駆動用IC7はこの情報信号をシリ
アル・パラレル変換し、発光強度補正を行うなどして当
該発光ダイオードアレイチップ4の発光ダイオード5
に、再び金属ワイヤ9を通じて信号伝達する。発光ダイ
オードアレイチップ4は、伝達された信号電流に比例し
た輻射強度で当該発光ダイオード5を発光させる。
The information signal input through the external terminal 13 is transmitted to the driving IC 7 through the circuit conductor film 2 and the metal wire 9, and the driving IC 7 performs serial / parallel conversion of this information signal to correct the emission intensity. The light emitting diode 5 of the light emitting diode array chip 4
Then, the signal is transmitted again through the metal wire 9. The light emitting diode array chip 4 causes the light emitting diode 5 to emit light with a radiation intensity proportional to the transmitted signal current.

【0006】このような光プリントヘッドを用いた光プ
リンタの構成を図11に示す。感光体ドラム14は、ア
ルミニウム等からなる円筒状導体上に有機光導電体(O
PC)やアモルファスシリコン感光体等の光伝導性材料
層を有し、矢印の方向に回転する。帯電器15は感光体
ドラム14の表面に数百Vの均一帯電を施す。光プリン
トヘッド16は図9および図10に示したもので、その
焦点が感光体ドラム14の表面上に位置するように配置
されている。発光ダイオード5からロッドレンズアレイ
10を通じて輻射された光信号は、感光体ドラム14の
表面上に結像して一次元静電潜像を描く。この静電潜像
は現像器17でトナー現像され、得られたトナー像は転
写器18で転写紙19に転写される。20はクリーナを
示す。
FIG. 11 shows the configuration of an optical printer using such an optical print head. The photoconductor drum 14 includes an organic photoconductor (O) on a cylindrical conductor made of aluminum or the like.
It has a photoconductive material layer such as PC) or an amorphous silicon photoconductor and rotates in the direction of the arrow. The charger 15 uniformly charges the surface of the photoconductor drum 14 at several hundreds of volts. The optical print head 16 shown in FIGS. 9 and 10 is arranged so that its focal point is located on the surface of the photosensitive drum 14. The optical signal radiated from the light emitting diode 5 through the rod lens array 10 forms an image on the surface of the photoconductor drum 14 to form a one-dimensional electrostatic latent image. The electrostatic latent image is toner-developed by the developing device 17, and the obtained toner image is transferred to the transfer paper 19 by the transfer device 18. 20 indicates a cleaner.

【0007】ここで、従来の光プリントヘッド16の製
造方法を説明しておくと、まず、単結晶III−V族半
導体基板(ウエハ)に、モノリシックに発光ダイオード
5およびその電極端子6をつくり込み、このウエハを発
光ダイオードアレイチップ4の単位に切断分離する。一
方、絶縁基板1の表面上の所定の回路用導体膜2上に導
電性樹脂層3を塗布形成し、その上に複数個の発光ダイ
オードアレイチップ4を直線状に並べる。これと同様
に、駆動用IC7も当該回路用導体膜2上に導電性樹脂
層3を介して載置する。その後、約150℃の温度下で
両樹脂層3、3を硬化させてダイボンドする。つぎに、
両電極端子6、8間に金線またはアルミニウム線を用い
たワイヤボンドを施し、完成した光プリントヘッド16
を集束性ロッドレンズアレイ10とともにシャーシ12
に組み込む。
Here, the conventional method for manufacturing the optical print head 16 will be described. First, the light emitting diode 5 and its electrode terminal 6 are monolithically formed in a single crystal III-V group semiconductor substrate (wafer). The wafer is cut and separated into units of the light emitting diode array chip 4. On the other hand, a conductive resin layer 3 is applied and formed on a predetermined circuit conductor film 2 on the surface of the insulating substrate 1, and a plurality of light emitting diode array chips 4 are linearly arranged on the conductive resin layer 3. Similarly, the driving IC 7 is also mounted on the circuit conductor film 2 via the conductive resin layer 3. After that, both resin layers 3 and 3 are cured at a temperature of about 150 ° C. and die-bonded. Next,
An optical print head 16 completed by wire bonding using a gold wire or an aluminum wire between both electrode terminals 6 and 8.
The focusing rod lens array 10 together with the chassis 12
Built in.

【0008】[0008]

【発明が解決しようとする課題】しかし、このような構
成であると、個々の発光ダイオード5の電極端子6に対
して逐一ワイヤボンドを施す必要がある。一例として、
発光ダイオード解像度が400dpiの光プリントヘッ
ド(A4サイズ)においては、発光ダイオードアレイチ
ップ4側だけで3,456本、駆動用IC7側を含める
と約4,000本の各ワイヤボンドが必要となる。この
ため、高速のワイヤボンダーを用いても30分〜1時間
の時間をワイヤボンドに費やすことになり、これが生産
性および歩留まりの向上を阻む大きな要因になってい
た。
However, with such a structure, it is necessary to wire bond the electrode terminals 6 of the individual light emitting diodes 5 one by one. As an example,
In an optical print head (A4 size) having a light emitting diode resolution of 400 dpi, 3,456 wire bonds are required on the light emitting diode array chip 4 side alone, and about 4,000 wire bonds are required when the driving IC 7 side is included. Therefore, even if a high-speed wire bonder is used, a time of 30 minutes to 1 hour is spent for wire bonding, which is a major factor that hinders improvement in productivity and yield.

【0009】また、絶縁基板1上に搭載された発光ダイ
オードアレイチップ4の高さが、ダイボンド用導電性樹
脂層3の層厚や位置によってばらつきやすく、これが、
集束性ロッドレンズアレイ10の焦点位置を狂わせて、
発光出力や解像度に低下をきたすという課題もあった。
Further, the height of the light emitting diode array chip 4 mounted on the insulating substrate 1 tends to vary depending on the layer thickness and position of the conductive resin layer 3 for die bonding, which is
By shifting the focus position of the converging rod lens array 10,
There is also a problem that the light emission output and the resolution are lowered.

【0010】[0010]

【課題を解決するための手段】本発明は上述した課題を
解決するために、複数の回路用導体膜を表面上に配列し
ている透光性基板と、直線状に並んだ複数の発光ダイオ
ードを集積して、各発光ダイオードの電極端子としての
金属バンプを発光面側の面上に配列している発光ダイオ
ードアレイチップとからなり、発光ダイオードアレイチ
ップはその発光面を透光性基板の表面に向けてダイボン
ドされ、前記金属バンプは前記回路用導体膜の金属めっ
き層に接し、前記金属バンプが前記金属めっき層に比べ
て高いヤング率を有していることを特徴とする光プリン
トヘッドが提供される。
In order to solve the above-mentioned problems, the present invention provides a transparent substrate having a plurality of circuit conductive films arranged on the surface thereof, and a plurality of light emitting diodes arranged in a straight line. And a light emitting diode array chip in which metal bumps as electrode terminals of each light emitting diode are arranged on the light emitting surface side, and the light emitting diode array chip has its light emitting surface on the surface of the transparent substrate. An optical print head characterized in that the metal bump is in contact with a metal plating layer of the circuit conductor film, and the metal bump has a higher Young's modulus than the metal plating layer. Provided.

【0011】また、複数の回路用導体膜を表面上に配列
している透光性基板と、直線状に並んだ複数の発光ダイ
オードを集積して、各発光ダイオードの電極端子として
の金属バンプを発光面側の面上に配列している発光ダイ
オードアレイチップとからなり、発光ダイオードアレイ
チップはその発光面を透光性基板の表面に向けてダイボ
ンドされ、前記金属バンプは前記回路用導体膜上の少な
くとも前記金属バンプに対向する位置に形成された金属
めっき層に接し、前記金属めっき層が前記金属バンプの
高さのばらつき寸度よりも大きく前記金属バンプの高さ
よりは小さい層厚を有していることを特徴とする光プリ
ントヘッドが提供される。
Further, a light-transmissive substrate having a plurality of circuit conductor films arranged on its surface and a plurality of linearly arranged light emitting diodes are integrated to form metal bumps as electrode terminals of each light emitting diode. A light emitting diode array chip arranged on a surface on the light emitting surface side, the light emitting diode array chip is die-bonded with its light emitting surface facing the surface of the transparent substrate, and the metal bumps are on the circuit conductor film. In contact with at least the metal plating layer formed at a position facing the metal bump, and the metal plating layer has a layer thickness larger than the height variation of the metal bump and smaller than the height of the metal bump. An optical print head is provided.

【0012】さらに、発光ダイオードアレイチップの発
光面側の面上に配列された電極端子たる金属バンプを、
透光性基板の表面上に配列された回路用導体膜の金属め
っき層の所定位置に重ね合わせる工程と、発光ダイオー
ドアレイチップを透光性基板側へ加圧して仮固定をする
工程と、前記加圧を解く工程と、前記金属バンプと前記
回路用導体膜上の前記金属めっき層とを、前者の融点と
後者の融点との間の温度に加熱して本固定をする工程
と、発光ダイオードアレイチップと透光性基板との間隙
に透光性絶縁樹脂を注入する工程と、透光性絶縁樹脂を
硬化させる工程とを備えたことを特徴とする光プリント
ヘッドの製造方法が提供される。
Further, metal bumps, which are electrode terminals, are arranged on the light emitting surface side of the light emitting diode array chip.
Stacking the metal plating layer of the conductor film for a circuit arranged on the surface of the transparent substrate at a predetermined position, pressing the light emitting diode array chip to the transparent substrate side for temporary fixing, A step of releasing pressure, a step of heating the metal bump and the metal plating layer on the conductor film for a circuit to a temperature between the melting point of the former and the melting point of the latter to perform final fixing, and a light emitting diode A method for manufacturing an optical print head, comprising: a step of injecting a translucent insulating resin into a gap between an array chip and a translucent substrate; and a step of curing the translucent insulating resin. .

【0013】[0013]

【作用】本発明によると、発光ダイオードアレイチップ
が、その発光面を透光性基板の表面に向けたフェイスダ
ウン姿勢でダイボンドされ、発光ダイオードの電極端子
が透光性基板の表面上の回路用導体膜に直接に接して結
合される。このため、従来のワイヤボンドは不要とな
り、ワイヤボンドに相当する前記結合が、ダイボンドと
同時に達成され、しかも、複数箇所における前記結合が
一挙に達成される。
According to the present invention, the light emitting diode array chip is die-bonded in a face-down posture with its light emitting surface facing the surface of the transparent substrate, and the electrode terminals of the light emitting diode are for circuits on the surface of the transparent substrate. Bonded directly to the conductor film. Therefore, the conventional wire bond is not necessary, and the bonding corresponding to the wire bond is achieved at the same time as the die bonding, and the bonding at a plurality of points is achieved all at once.

【0014】また、前記結合は金属バンプを金属めっき
層に強く押し当てるかたちで達成されるので、ダイボン
ド用導電性樹脂層の層厚にばらつきがあっても、これを
ダイボンド時に均等化させることができる。
Further, since the bonding is achieved by pressing the metal bump strongly against the metal plating layer, even if there is a variation in the layer thickness of the conductive resin layer for die bonding, it can be made uniform during die bonding. it can.

【0015】さらに、金属バンプのヤング率を金属めっ
き層のヤング率よりも高く設定したり、金属めっき層の
層厚を金属バンプの高さばらつき寸度よりも大きく設定
したりすることによって、本固定の工程に先立って施さ
れる重要な仮固定を確実なものにすることができる。
Further, by setting the Young's modulus of the metal bump higher than the Young's modulus of the metal plating layer, or by setting the layer thickness of the metal plating layer larger than the height variation of the metal bump, It is possible to ensure the important temporary fixing performed prior to the fixing process.

【0016】[0016]

【実施例】つぎに本発明の一実施例を図面の参照により
説明する。
An embodiment of the present invention will be described below with reference to the drawings.

【0017】図1に示すように、透光性基板21はその
表面上に複数の回路用導体膜22を配列している。発光
ダイオードアレイチップ23は、直線状に並んだ複数の
発光ダイオード24をモノリシックに集積しており、各
発光ダイオード24の電極リード部25上に電極端子と
して設けられた金属バンプ26が、発光面側の面上に配
列されている。発光ダイオードアレイチップ23は、そ
の発光面が透光性基板21の表面に向き合うフェイスダ
ウン姿勢でダイボンドされている。そして、金属バンプ
26が回路用導体膜22の金属めっき層27に接してい
る。回路用導体膜22はその全長のうち、金属バンプ2
6が当接する表面部分にのみ金属めっき層27を有して
いる。また、透光性基板21は、少なくとも光路となる
領域が透明であればよい。28は透光性絶縁樹脂層、2
9は導電性樹脂層、30はチップ裏面電極、31は駆動
用ICを示す。
As shown in FIG. 1, the transparent substrate 21 has a plurality of circuit conductive films 22 arranged on the surface thereof. The light emitting diode array chip 23 monolithically integrates a plurality of linearly arranged light emitting diodes 24. The metal bumps 26 provided as electrode terminals on the electrode lead portions 25 of each light emitting diode 24 have a light emitting surface side. Are arranged on the surface of. The light emitting diode array chip 23 is die-bonded such that its light emitting surface faces the surface of the transparent substrate 21 in a face-down posture. The metal bumps 26 are in contact with the metal plating layer 27 of the circuit conductor film 22. The conductor film 22 for a circuit has a metal bump 2 in its entire length.
The metal plating layer 27 is provided only on the surface portion with which 6 abuts. In addition, the light-transmissive substrate 21 may be transparent at least in a region serving as an optical path. 28 is a translucent insulating resin layer, 2
Reference numeral 9 is a conductive resin layer, 30 is a chip back surface electrode, and 31 is a driving IC.

【0018】このように構成された光プリントヘッドは
図2に示すように、集束性ロッドレンズアレイ32とと
もにシャーシ33に組み込まれる。34は外部端子、3
5は感光体ドラムを示す。
The optical print head thus constructed is incorporated in the chassis 33 together with the converging rod lens array 32, as shown in FIG. 34 is an external terminal, 3
Reference numeral 5 denotes a photosensitive drum.

【0019】外部端子34に入力された情報信号電圧
は、回路用導体膜22、金属めっき層27および金属バ
ンプ26を通じて駆動用IC31に入力される。ここ
で、シフトレジスタによるパラレルシリアル変換や電圧
・電流変換など、発光ダイオードアレイチップ23への
出力補正が行われる。そして、各発光ダイオード24に
対する信号電流が、再び回路用導体膜22を通じて発光
ダイオードアレイチップ23の当該電極リード部25に
入力され、それぞれの発光ダイオード24は入力された
信号電流に応じた発光強度で光輻射する。
The information signal voltage input to the external terminal 34 is input to the driving IC 31 through the circuit conductor film 22, the metal plating layer 27 and the metal bumps 26. Here, output correction to the light emitting diode array chip 23 is performed by parallel / serial conversion by a shift register, voltage / current conversion, and the like. Then, the signal current to each light emitting diode 24 is input again to the electrode lead portion 25 of the light emitting diode array chip 23 through the circuit conductor film 22, and each light emitting diode 24 has the light emission intensity corresponding to the input signal current. Emits light.

【0020】このように構成された光プリントヘッドの
製造方法は以下のとおりである。まず、単結晶III−
V属半導体基板(ウエハ)に、複数の発光ダイオード2
4とその電極リード部25をつくり込む。本例では発光
波長660nmおよび740nmの発光ダイオードを1
6dot/mmでつくり込んだ。つぎに、電極リード部
25上に金属バンプ26を形成する。金属バンプ26は
金、インジュウムまたは半田等をめっき法で形成した
り、金線等の金属細線を熱エネルギーと超音波エネルギ
ーとで球状に融着させたものであってもよい。本例では
線径約25μmの金線を球状に融着した数μm〜50μ
mの突起を金属バンプ用に形成した。こののち、ウエハ
を高精度ダイシング技術によって発光ダイオードアレイ
チップ23の単位に切断分離する。
The method of manufacturing the optical print head having the above structure is as follows. First, single crystal III-
A plurality of light emitting diodes 2 are provided on a group V semiconductor substrate (wafer).
4 and its electrode lead portion 25 are built in. In this example, one light-emitting diode with emission wavelengths of 660 nm and 740 nm is used.
It was built in at 6 dots / mm. Next, the metal bumps 26 are formed on the electrode lead portions 25. The metal bump 26 may be formed by plating gold, indium, solder, or the like, or may be formed by fusing a metal thin wire such as a gold wire into a spherical shape by heat energy and ultrasonic energy. In this example, a gold wire having a wire diameter of about 25 μm is fused into a spherical shape of several μm to 50 μm.
m projections were formed for the metal bumps. After that, the wafer is cut and separated into units of the light emitting diode array chip 23 by a high precision dicing technique.

【0021】一方、透光性基板21の表面上に複数の回
路用導体膜22を形成する。回路用導体膜22は、金の
厚膜ペーストを印刷し硬化させたのち、フォトリソグラ
フ法によってパターニングし、エッチング加工を施して
所定のパターン膜に形成する。回路用導体膜22のう
ち、発光ダイオードアレイチップ23の電極リード部2
5に対向する部分に金属めっき層27を形成する。本例
では、電解めっき法を適用して層厚約1μmのニッケル
めっき層を形成したのち、層厚約10μmの半田めっき
層を形成した。
On the other hand, a plurality of circuit conductor films 22 are formed on the surface of the transparent substrate 21. The circuit conductor film 22 is formed into a predetermined pattern film by printing a gold thick film paste and curing it, followed by patterning by photolithography and etching. Of the circuit conductive film 22, the electrode lead portion 2 of the light emitting diode array chip 23.
The metal plating layer 27 is formed in the portion facing 5 In this example, an electrolytic plating method was applied to form a nickel plating layer having a layer thickness of about 1 μm, and then a solder plating layer having a layer thickness of about 10 μm was formed.

【0022】つぎに、この発光ダイオードアレイチップ
23を図3の(a)に示すように、透光性基板21の所
定位置に配列する。なお、図3には1個の発光ダイオー
ドアレイチップ26につき3個の金属バンプ26が示さ
れているにすぎないが、実際には各発光ダイオードアレ
イチップ23につき64個の発光ダイオードが集積され
ているので、64個の金属バンプ26が存在する。
Next, as shown in FIG. 3A, the light emitting diode array chip 23 is arranged at a predetermined position on the transparent substrate 21. Although only three metal bumps 26 are shown for each light emitting diode array chip 26 in FIG. 3, 64 light emitting diodes are actually integrated for each light emitting diode array chip 23. Therefore, there are 64 metal bumps 26.

【0023】つぎに図3の(b)に示すように、加圧ツ
ール37を用い、透光性基板21の表面上に位置合わせ
されている発光ダイオードアレイチップ23の裏面側か
ら鉛直方向に加圧する。この加圧によって金属バンプ2
6および金属めっき層27が弾性変形を起こす。その後
にこの加圧を緩めるが、この工程によって発光ダイオー
ドアレイチップ23が透光性基板21の表面上に仮固定
される。
Next, as shown in FIG. 3B, a pressing tool 37 is used to apply a pressure in the vertical direction from the back surface side of the light emitting diode array chip 23 aligned on the front surface of the transparent substrate 21. Press. By this pressure, the metal bump 2
6 and the metal plating layer 27 elastically deform. Thereafter, the pressure is released, but the light emitting diode array chip 23 is temporarily fixed on the surface of the transparent substrate 21 by this step.

【0024】金属バンプ26のヤング率は、金属めっき
層27のヤング率よりも大きく設定する。このような関
係に材料を選ぶことによって、金属めっき層27が金属
バンプ26よりも先に大きな弾性変形を起こし、金属バ
ンプ26が金属めっき層27内に埋め込まれる。これに
続いて金属バンプ26が弾性変形を起こし、レベリング
されるので高さばらつきが是正される。このようなメカ
ニズムによって金属バンプ26が金属めっき層27に仮
固定される。
The Young's modulus of the metal bump 26 is set to be larger than that of the metal plating layer 27. By selecting the material in such a relationship, the metal plating layer 27 undergoes large elastic deformation before the metal bumps 26, and the metal bumps 26 are embedded in the metal plating layer 27. Following this, the metal bumps 26 are elastically deformed and leveled, so that height variations are corrected. The metal bump 26 is temporarily fixed to the metal plating layer 27 by such a mechanism.

【0025】金属めっき層27の層厚を金属バンプ26
の弾性変形後の高さばらつき寸度よりも大きく設定する
ことによって、すべての金属バンプ26をすべての金属
めっき層27に確実に埋入でき、十分な仮固定の効果を
得ることができる。
The thickness of the metal plating layer 27 is set to the metal bump 26.
By setting it to be larger than the height variation dimension after the elastic deformation, all the metal bumps 26 can be reliably embedded in all the metal plating layers 27, and a sufficient temporary fixing effect can be obtained.

【0026】金属めっき層27の層厚は、金属バンプ2
6の弾性変形後の高さよりも小さく設定しておく。もし
も、金属めっき層27の層厚が金属バンプ26の高さと
同等以上であると、金属バンプ26が金属めっき層27
内に完全に埋まってしまい、発光ダイオードアレイチッ
プ23に形成されている電極リード部25に半田等のめ
っき層材料が接触する危険がある。電極リード部25は
通常、アルミニウムを主成分とする金属からなるので、
半田に対して腐食しやすく信頼性を低下させる。そこ
で、半田等の金属めっき層27の層厚を金属バンプ26
の弾性変形後の高さよりも小さくすることによって、電
極リード部25と金属めっき層27との接触を避ける。
The metal plating layer 27 has a layer thickness of the metal bump 2
The height is set to be smaller than the height of 6 after the elastic deformation. If the layer thickness of the metal plating layer 27 is equal to or greater than the height of the metal bump 26, the metal bump 26 will be
There is a risk that the plating layer material such as solder will come into contact with the electrode lead portion 25 formed on the light emitting diode array chip 23, because it will be completely buried inside. Since the electrode lead portion 25 is usually made of a metal whose main component is aluminum,
It easily corrodes against solder and reduces reliability. Therefore, the layer thickness of the metal plating layer 27 such as solder is set to the metal bump 26.
By making the height smaller than that after elastic deformation, contact between the electrode lead portion 25 and the metal plating layer 27 is avoided.

【0027】本例では金からなる金属バンプ26の加圧
後の高さばらつきを3μm未満に抑えることができたの
で、半田からなる金属めっき層27の層厚は3μm〜3
0μmが適当な値であった。とくに層厚を10μm〜2
0μmの範囲に選ぶと、仮固定での安定性および本固定
での信頼性の両面で好ましい結果が得られた。
In this example, since the height variation of the metal bumps 26 made of gold after being pressed could be suppressed to less than 3 μm, the thickness of the metal plating layer 27 made of solder was 3 μm to 3 μm.
An appropriate value was 0 μm. Especially, the layer thickness is 10 μm to 2
When selected in the range of 0 μm, favorable results were obtained in terms of both stability in temporary fixing and reliability in main fixing.

【0028】同様にして、第2および第3の発光ダイオ
ードアレイチップを順次に配列し、順次に加圧して光プ
リントヘッドの光記録幅に相当する個数の発光ダイオー
ドアレイチップ23を配列する(図3のc)。本実施例
においては54個のチップを直線上に配置してA4サイ
ズ16dot/mmの密着型光プリントヘッドを作製し
た。
Similarly, the second and third light emitting diode array chips are sequentially arranged, and the light emitting diode array chips 23 are arranged in a number corresponding to the optical recording width of the optical print head by sequentially applying pressure (FIG. 3c). In this example, 54 chips were arranged on a straight line to manufacture a contact type optical print head of A4 size 16 dot / mm.

【0029】図3には発光ダイオードアレイチップ23
のみを示したが、駆動用IC31に対しても上述と同様
の金属バンプを形成する。そして、切断分割後の半導体
チップを所定位置に配列し、加圧によって仮固定する。
FIG. 3 shows a light emitting diode array chip 23.
Although only shown, the same metal bump as described above is formed on the driving IC 31. Then, the semiconductor chips after cutting and dividing are arranged in a predetermined position and temporarily fixed by pressurization.

【0030】つぎに、発光ダイオードアレイチップ23
および駆動用IC31が仮固定された透光性基板21を
高温雰囲気中に置く。このとき、金属バンプ26の融点
と金属めっき層27の融点との間の温度に設定する。本
例では185℃〜220℃の温度に設定した。これによ
って、融点の低い半田めっき層のみが融解し、その表面
張力によって金バンプの表面上に吹上がり、理想的な半
田接続効果を得ることができた(図3のd)。
Next, the light emitting diode array chip 23
The transparent substrate 21 on which the driving IC 31 is temporarily fixed is placed in a high temperature atmosphere. At this time, the temperature is set between the melting point of the metal bump 26 and the melting point of the metal plating layer 27. In this example, the temperature is set to 185 ° C to 220 ° C. As a result, only the solder plating layer having a low melting point was melted, and the surface tension of the solder plating layer blew up onto the surface of the gold bump, and an ideal solder connection effect could be obtained (d in FIG. 3).

【0031】つぎに、発光ダイオードアレイチップ23
および駆動用IC31と、透光性基板21との各間隙に
透光性絶縁樹脂層28を充填によって形成する。この材
料としては紫外線硬化型の透光性絶縁樹脂を用いる。そ
して、充填後に紫外線を透光性基板21のチップ非装着
面から照射して硬化させる(図3のe)。
Next, the light emitting diode array chip 23
A transparent insulating resin layer 28 is formed by filling each gap between the driving IC 31 and the transparent substrate 21. As this material, a UV-curable translucent insulating resin is used. After the filling, ultraviolet rays are irradiated from the chip non-mounting surface of the transparent substrate 21 to cure (e in FIG. 3).

【0032】本例では紫外線硬化樹脂を用いたが、熱硬
化型のものであってもよい。また、熱・紫外線併用型の
樹脂であってもよい。発光ダイオードアレイチップ23
に対しては透光性絶縁樹脂を充填するが、駆動用IC3
1に対しては透光性のものである必要はない。
Although an ultraviolet curable resin is used in this example, a thermosetting type resin may be used. Also, a heat / ultraviolet combined type resin may be used. Light emitting diode array chip 23
Is filled with a translucent insulating resin, but the driving IC3
1 does not have to be translucent.

【0033】こののち、発光ダイオードアレイチップ2
3の裏面電極30と所定の回路用導体膜22とを電気的
に接続するためのエポキシ系導電性樹脂層29を形成す
る。
After this, the light emitting diode array chip 2
An epoxy-based conductive resin layer 29 for electrically connecting the back electrode 30 of No. 3 and the predetermined circuit conductor film 22 is formed.

【0034】エポキシ系導電性樹脂を塗布して130℃
〜150℃の温度下で約1時間硬化させる(図3の
f)。
Epoxy conductive resin is applied and the temperature is 130 ° C.
Cure at a temperature of ~ 150 ° C for about 1 hour (f in Figure 3).

【0035】以上のような構成および製造方法であるの
で、ダイボンド工程とワイヤボンド工程との2工程を設
定する必要がなくなり、電気的接続と機械的接続とが同
時に得られる。また、発光ダイオードアレイチップと駆
動用ICとの間における多数箇所での電気的接続を一挙
に達成できるので、量産性に富んだ信頼性の高い光プリ
ントヘッドを得ることができる。 発光ダイオードアレ
イチップを駆動させる集積回路を発光ダイオードアレイ
チップと同時に仮固定、本硬化、透光性絶縁樹脂充填、
透光性絶縁樹脂硬化、導電性樹脂塗布、導電性樹脂硬化
させることが可能であり、これによって更に生産性を向
上させることができる。
Since the structure and manufacturing method are as described above, it is not necessary to set the two steps of the die bonding step and the wire bonding step, and electrical connection and mechanical connection can be obtained at the same time. In addition, since electrical connection can be achieved at a large number of points between the light emitting diode array chip and the driving IC, it is possible to obtain a highly reliable optical print head that is highly productive. The integrated circuit that drives the light emitting diode array chip is temporarily fixed at the same time as the light emitting diode array chip, fully cured, and filled with translucent insulating resin.
It is possible to cure the translucent insulating resin, apply the conductive resin, and cure the conductive resin, thereby further improving the productivity.

【0036】図4に示す実施例の光プリントヘッドで
は、光ファイバアレイ基板38を用いている。39は光
ファイバ束を示す。光ファイバアレイ基板38は図5な
いし図7に示すような構造になっている。40はベース
ガラスを示す。光ファイバ束39を構成する光ファイバ
は、開口数(NA)に相当する入射角より大きな角度の
光を除去するために、図7に示すようにコア41の周囲
に屈折率の小さなクラッド42を有し、その周囲に光吸
収体層43を有している。コア径が12、開口数が0.
9の光ファイバを用いた。各コア41には約2μmの厚
さのクラッド42と、約2μmの厚さの光吸収体層43
が被覆されている。この様な光ファイバを複数本まとめ
て光ファイバ束39を形成し、光ファイバとほぼ同等の
熱膨脹係数を有する2枚のベースガラス40、40間に
光ファイバ束39を挟んで配列し、加熱・加圧して溶融
し一体化する。このため、当初は円形であった光ファイ
バ束は変形し、五角形あるいは六角形のような断面形状
になる。これを適度な厚さに切り出し、光ファイバの露
出端面を光学的に鏡面に研磨して光ファイバアレイ基板
38を得る。この光ファイバアレイ基板上に前記実施例
におけると同様に回路用導体膜22を形成する。このと
き、発光ダイオードアレイチップ23の発光ダイオード
24が光ファイバ束39の端面に対向し得るように形成
する。金属めっき層および金属バンプの形成は前述した
実施例と同様に行う。
The optical print head of the embodiment shown in FIG. 4 uses the optical fiber array substrate 38. Reference numeral 39 denotes an optical fiber bundle. The optical fiber array substrate 38 has a structure as shown in FIGS. 40 indicates a base glass. The optical fibers forming the optical fiber bundle 39 have a clad 42 having a small refractive index around the core 41 as shown in FIG. 7 in order to remove light having an angle larger than the incident angle corresponding to the numerical aperture (NA). The light absorber layer 43 is provided around it. Core diameter is 12 and numerical aperture is 0.
9 optical fibers were used. Each core 41 has a clad 42 having a thickness of about 2 μm and a light absorber layer 43 having a thickness of about 2 μm.
Are covered. A plurality of such optical fibers are combined to form an optical fiber bundle 39, and the optical fiber bundle 39 is arranged between two base glasses 40 and 40 having a thermal expansion coefficient substantially equal to that of the optical fibers, and heating / heating is performed. Apply pressure to melt and integrate. For this reason, the optical fiber bundle, which was initially circular, is deformed into a pentagonal or hexagonal cross-sectional shape. This is cut out to an appropriate thickness, and the exposed end surface of the optical fiber is optically polished to a mirror surface to obtain an optical fiber array substrate 38. The circuit conductor film 22 is formed on the optical fiber array substrate in the same manner as in the above embodiment. At this time, the light emitting diode 24 of the light emitting diode array chip 23 is formed so as to face the end face of the optical fiber bundle 39. The metal plating layer and the metal bump are formed in the same manner as in the above-mentioned embodiment.

【0037】このように構成された光プリントヘッドの
動作は前述した実施例のものと基本的に同様である。発
光ダイオードから輻射された光は、光ファイバの端面か
ら入射する。ファイバの開口数に対応した角度より小さ
い角度で入射した光だけがファイバのコア内部で完全反
射を繰り返して、ファイバの他端から出射される。
The operation of the optical print head thus constructed is basically the same as that of the above-described embodiment. The light emitted from the light emitting diode enters from the end face of the optical fiber. Only light that is incident at an angle smaller than the angle corresponding to the numerical aperture of the fiber is repeatedly completely reflected inside the core of the fiber and is emitted from the other end of the fiber.

【0038】図8に示すように、光ファイバアレイ基板
38の光ファイバの他端は感光体ドラム35に近接して
配置されており、感光体ドラム35の所定位置に光を照
射する。なお、開口数に対応した角度より大きい角度で
入射した光は、各光ファイバの光吸収体層43で吸収さ
れる。
As shown in FIG. 8, the other end of the optical fiber of the optical fiber array substrate 38 is arranged in proximity to the photoconductor drum 35, and the predetermined position of the photoconductor drum 35 is irradiated with light. Light incident at an angle larger than the angle corresponding to the numerical aperture is absorbed by the light absorber layer 43 of each optical fiber.

【0039】ここで感光体ドラム35を、透光性ベルト
に透明電極を形成したのち、感光体を塗布した感光体ベ
ルトを用いることができる。この場合、光ファイバアレ
イ基板35を感光体ベルトの感光体が塗布されていない
面に密着させることができ、このように構成すると、解
像度等の面で有利である。
Here, as the photosensitive drum 35, a photosensitive belt formed by forming a transparent electrode on a translucent belt and then applying a photosensitive member thereto can be used. In this case, the optical fiber array substrate 35 can be brought into close contact with the surface of the photosensitive belt on which the photosensitive member is not applied, and such a configuration is advantageous in terms of resolution and the like.

【0040】このようにして得られた光プリントヘッド
では、従来のセルフォックレンズアレイを用いた光プリ
ントヘッドと同一の発光ダイオードを用いて記録体を照
明したとき、約4〜8倍の光信号を得ることができた。
In the optical print head thus obtained, when the recording medium is illuminated by using the same light emitting diode as in the conventional optical print head using the SELFOC lens array, an optical signal of about 4 to 8 times is obtained. I was able to get

【0041】[0041]

【発明の効果】以上のように本発明によると、発光ダイ
オードアレイチップの電極端子から駆動用ICに通じる
電気的接続にワイヤボンドを要しないので、光プリント
ヘッドの生産性、信頼性および歩留まりをともに大幅に
向上させることができる。
As described above, according to the present invention, the wire connection is not required for the electrical connection from the electrode terminals of the light emitting diode array chip to the driving IC, so that the productivity, reliability and yield of the optical print head can be improved. Both can be greatly improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における光プリントヘッドの
断面図。
FIG. 1 is a sectional view of an optical print head according to an embodiment of the present invention.

【図2】本発明の一実施例における光プリントヘッドを
適用したプリンタの要部の断面図。
FIG. 2 is a sectional view of a main part of a printer to which the optical print head according to the embodiment of the invention is applied.

【図3】本発明の一実施例における光プリントヘッドの
製造工程図。
FIG. 3 is a manufacturing process diagram of an optical print head according to an embodiment of the present invention.

【図4】本発明の他の実施例における光プリントヘッド
の側面図。
FIG. 4 is a side view of an optical print head according to another embodiment of the present invention.

【図5】光ファイバアレイ基板の説明図。FIG. 5 is an explanatory diagram of an optical fiber array substrate.

【図6】光ファイバアレイ基板の説明図。FIG. 6 is an explanatory diagram of an optical fiber array substrate.

【図7】光ファイバアレイ基板の説明図。FIG. 7 is an explanatory diagram of an optical fiber array substrate.

【図8】本発明の他の実施例における光プリントヘッド
を適用したブリンタの要部の断面図。
FIG. 8 is a cross-sectional view of a main part of a printer to which an optical print head according to another embodiment of the present invention is applied.

【図9】従来の光プリントヘッドの横断面図。FIG. 9 is a cross-sectional view of a conventional optical printhead.

【図10】従来の光プリントヘッドの縦断面図。FIG. 10 is a vertical cross-sectional view of a conventional optical print head.

【図11】光プリンタの構成図。FIG. 11 is a configuration diagram of an optical printer.

【符号の説明】[Explanation of symbols]

21 透光性基板 22 回路用導体膜 23 発光ダイオードアレイチップ 24 発光ダイオード 25 電極リード部 26 金属バンプ 27 金属めっき層 21 Translucent Substrate 22 Circuit Conductor Film 23 Light Emitting Diode Array Chip 24 Light Emitting Diode 25 Electrode Lead 26 Metal Bump 27 Metal Plating Layer

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 複数の回路用導体膜を表面上に配列して
いる透光性基板と、 直線状に並んだ複数の発光ダイオードを集積して、各発
光ダイオードの電極端子としての金属バンプを発光面側
の面上に配列している発光ダイオードアレイチップとか
らなり、 発光ダイオードアレイチップはその発光面を透光性基板
の表面に向けてダイボンドされ、前記金属バンプは前記
回路用導体膜上の少なくとも前記金属バンプに対向する
位置に形成された金属めっき層に接し、前記金属バンプ
が前記金属めっき層に比べて高いヤング率を有している
ことを特徴とする光プリントヘッド。
1. A light transmissive substrate having a plurality of circuit conductive films arranged on the surface thereof and a plurality of light emitting diodes arranged in a straight line are integrated to form a metal bump as an electrode terminal of each light emitting diode. The light emitting diode array chip is arranged on the surface of the light emitting surface, and the light emitting diode array chip is die-bonded with its light emitting surface facing the surface of the transparent substrate, and the metal bumps are on the circuit conductor film. Of at least the metal plating layer formed at a position facing the metal bump, and the metal bump has a Young's modulus higher than that of the metal plating layer.
【請求項2】 複数の回路用導体膜を表面上に配列して
いる透光性基板と、 直線状に並んだ複数の発光ダイオードを集積して、各発
光ダイオードの電極端子としての金属バンプを発光面側
の面上に配列している発光ダイオードアレイチップとか
らなり、 発光ダイオードアレイチップはその発光面を透光性基板
の表面に向けてダイボンドされ、前記金属バンプは前記
回路用導体膜上の少なくとも前記金属バンプに対向する
位置に形成された金属めっき層に接し、前記金属めっき
層が前記金属バンプの高さばらつき寸度よりも大きく前
記金属バンプの高さよりは小さい層厚を有していること
を特徴とする光プリントヘッド。
2. A light-transmitting substrate having a plurality of circuit conductor films arranged on the surface thereof, and a plurality of light emitting diodes arranged in a straight line, and metal bumps serving as electrode terminals of each light emitting diode. The light emitting diode array chip is arranged on the surface of the light emitting surface, and the light emitting diode array chip is die-bonded with its light emitting surface facing the surface of the transparent substrate, and the metal bumps are on the circuit conductor film. At least in contact with a metal plating layer formed at a position facing the metal bump, and the metal plating layer has a layer thickness larger than the height variation dimension of the metal bump and smaller than the height of the metal bump. Optical print head characterized by
【請求項3】 金属バンプが金からなり、金属めっき層
が半田からなることを特徴とする請求項1または請求項
2記載の光プリントヘッド。
3. The optical print head according to claim 1, wherein the metal bump is made of gold and the metal plating layer is made of solder.
【請求項4】 金属バンプが非共晶半田からなり、金属
めっき層が共晶半田からなることを特徴とする請求項1
または請求項2記載の光プリントヘッド。
4. The metal bump is made of non-eutectic solder, and the metal plating layer is made of eutectic solder.
Alternatively, the optical print head according to claim 2.
【請求項5】 発光ダイオードアレイチップの発光面側
の面上に配列された電極端子たる金属バンプを、透光性
基板の表面上に配列された回路用導体膜の金属めっき層
の所定位置に重ね合わせる工程と、 発光ダイオードアレイチップを透光性基板側へ加圧して
仮固定をする工程と、 前記加圧を解く工程と、 前記金属バンプと前記回路用導体膜上の前記金属めっき
層とを、前者の融点と後者の融点との間の温度に加熱し
て本固定をする工程と、 発光ダイオードアレイチップと透光性基板との間隙に透
光性絶縁樹脂を注入する工程と、 透光性絶縁樹脂を硬化させる工程とを備えたことを特徴
とする光プリントヘッドの製造方法。
5. A metal bump, which is an electrode terminal arranged on the light emitting surface side of the light emitting diode array chip, is provided at a predetermined position of the metal plating layer of the circuit conductive film arranged on the surface of the transparent substrate. A step of stacking, a step of temporarily pressing the light emitting diode array chip toward the transparent substrate side, a step of releasing the pressure, the metal bump and the metal plating layer on the circuit conductive film. Is heated to a temperature between the melting point of the former and the melting point of the latter to perform permanent fixing, and a step of injecting a translucent insulating resin into the gap between the light emitting diode array chip and the translucent substrate, And a step of curing the light-insulating resin.
JP15474193A 1993-06-25 1993-06-25 Optical printing head and manufacture thereof Pending JPH0725060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15474193A JPH0725060A (en) 1993-06-25 1993-06-25 Optical printing head and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15474193A JPH0725060A (en) 1993-06-25 1993-06-25 Optical printing head and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0725060A true JPH0725060A (en) 1995-01-27

Family

ID=15590911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15474193A Pending JPH0725060A (en) 1993-06-25 1993-06-25 Optical printing head and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0725060A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1207563A2 (en) * 2000-11-08 2002-05-22 LumiLeds Lighting U.S., LLC Direct bonding of flip-chip light-emitting diode and flip-chip ESD protection chip to electrodes in a package
JP2003008083A (en) * 2001-05-15 2003-01-10 Lumileds Lighting Us Llc Multiple chip semiconductor led assembly
KR100494021B1 (en) * 2001-11-30 2005-06-10 다이닛뽕스크린 세이조오 가부시키가이샤 Light source device and image recording apparatus
CN102339935A (en) * 2010-07-15 2012-02-01 展晶科技(深圳)有限公司 Flip-chip-type LED (light-emitting diode) package structure
JP2014090164A (en) * 2012-10-29 2014-05-15 Lg Innotek Co Ltd Light-emitting element and light-emitting element package
CN104347787A (en) * 2014-09-30 2015-02-11 佛山市国星光电股份有限公司 Preparation method of LED (light emitting diode) luminous unit

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1207563A2 (en) * 2000-11-08 2002-05-22 LumiLeds Lighting U.S., LLC Direct bonding of flip-chip light-emitting diode and flip-chip ESD protection chip to electrodes in a package
EP1207563A3 (en) * 2000-11-08 2007-03-21 LumiLeds Lighting U.S., LLC Direct bonding of flip-chip light-emitting diode and flip-chip ESD protection chip to electrodes in a package
JP2003008083A (en) * 2001-05-15 2003-01-10 Lumileds Lighting Us Llc Multiple chip semiconductor led assembly
KR100494021B1 (en) * 2001-11-30 2005-06-10 다이닛뽕스크린 세이조오 가부시키가이샤 Light source device and image recording apparatus
CN102339935A (en) * 2010-07-15 2012-02-01 展晶科技(深圳)有限公司 Flip-chip-type LED (light-emitting diode) package structure
JP2014090164A (en) * 2012-10-29 2014-05-15 Lg Innotek Co Ltd Light-emitting element and light-emitting element package
CN104347787A (en) * 2014-09-30 2015-02-11 佛山市国星光电股份有限公司 Preparation method of LED (light emitting diode) luminous unit
CN104347787B (en) * 2014-09-30 2017-05-31 佛山市国星光电股份有限公司 A kind of preparation method of LED luminescence units

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