JPH07250035A - Optical receiver - Google Patents

Abstract

PURPOSE:To provide the optical receiver for providing a signal logically synthesizing an optical signal to be made incident on a photodetecting element array without increasing the number of wires such as pull-out wires from the photodetecting element array. CONSTITUTION:Concerning this optical receiver for which a photodiode array 14-ij is formed on a substrate 10, each terminal is connected by an induced common connecting wire 17, terminal resistors 21 and 22 are connected to each of respective terminals of photodetecting elements at both the terminal parts of the photodiode array and further, the signal logically synthesizing plural amplitude modulated optical signals 27 made incident from one terminal of the common connecting wire 17 on the photodiode array is detected through a waveform shaping circuit 25, an LC circuit network provided with a fixed characteristic impedance is composed of the photodiode array and the common connecting wire and further, the value of the terminal resistors 21 and 22 is made equal with the characteristic impedance of the LC circuit network.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical receiver, and more particularly to an optical receiver for obtaining a signal obtained by logically combining a plurality of optical signals incident on a photodetector array.

[0002]

2. Description of the Related Art In recent years, with the progress of semiconductor technology and computer architecture, a massively parallel computer has been put into practical use in which a large number of processors perform processing in parallel to dramatically improve the total processing capacity. In a massively parallel computer, as the number of installed processors increases, a bus for exchanging data between the processors is required to have higher speed and larger capacity.

In the conventional method of realizing a bus between processors by electric wiring, it is difficult to satisfy the demands for high speed and large capacity required in a massively parallel computer, and the number of wirings is enormous. Therefore, there are problems that connection becomes difficult, and that a relay buffer for compensating for signal loss in long electric wiring must be installed.

In order to solve these various difficulties when a bus between processors is realized by electric wiring, wiring between boards mounting a large number of processor elements can be simplified instead of electric wiring, and high-speed communication can be achieved. An optical bus using optical interconnection, which has the advantage that it is possible, is promising. FIG. 13 is a conceptual diagram showing an example of such an optical bus system.
A planar light emitting / receiving device 110-11n in which a plurality of light emitting / receiving elements are arranged in a matrix is provided on 10n, and an optical signal propagating in a free space between the boards 100-10n is formed into a ring shape by the reflecting mirrors 121-124. It is circulated to connect the buses to all the boards 100 to 10n. Each light emitting / light receiving element is, for example, a light emitting / transmissive element having a light emitting / transmissive function arranged in the center of the substrate, and an annular light receiving element arranged around it. The transmissive element here is a transmissive optical element such as an amplifier, a switch, or a lens.

In FIG. 13, an optical signal emitted from the lower surface of the uppermost board 100 is partially received by the upper surface of the board 101, and the remaining transmitted signal is an optical signal passing through another path generated in the board 101. The light is emitted from the lower surface of the board 101 toward the lower board in parallel with. Similarly, the optical signals emitted from the lower surface of the board 10n at the lowermost stage are sequentially reflected by the reflecting mirrors 121 to 124 and enter the upper surface of the board 100. The optical bus system in which the light circulates in this manner has attracted a great deal of attention because it can be applied not only to a massively parallel computer but also to a system that handles large-capacity high-speed data such as a large-capacity exchange.

In JP-A-5-152608, "Optical Element and Optical Bus, and Optical Interprocessor Coupling Network Using These", in the ring-shaped optical bus configuration shown in FIG. As shown in FIG. 14 showing an example in which four elements are mounted, planar light emitting / light receiving devices 110 to 1 are provided on each processor board.
An example is shown in which 13 and the processor element PEij are connected.

In FIG. 14, an optical signal vertically emitted from the light emitting elements of the light emitting / receiving devices 110 to 113 on each board shown in FIG. 14 is incident on the light receiving elements of the light emitting / receiving devices on the subsequent boards. . The optical elements arranged in a matrix on the device are vertically coupled by paths that are optically independent of each other. The outputs of the light receiving elements in the same row of the light emitting / receiving devices 110 to 113 on each board are input to the same processor element (PE), and which processor on the other board has the same column number.
The optical signal generated from the element can be always received. That is, for example, the outputs of the light receiving elements at the positions 00, 10, 20, 30 of the light emitting / receiving device 110 are logically synthesized and input to the processor element PE00. Therefore, the signal transmitted from the processor element PEi0 can always be received by the processor element PE00. On the other hand, this processor
The light emitting element located at the position of hatched 00 is driven by the transmission signal output of the element PE00, and is transmitted toward PEi0.

Thus, it can be seen that PEi0s can send and receive signals to and from each other for arbitrary i. Similarly, for any i, the processor elements PEi1 are
PEi2 and PEi3 can send and receive signals to and from each other. In this way, a large number, but not all, of the optical bus couplings have coupled the processor elements together.

On the other hand, the processor elements mounted on the same processor board are electrically connected to each other, and PE0j, ..., P3 for any j.
The j's can send and receive signals to and from each other.

As can be easily understood from the above, communication between arbitrary processor elements on different processor boards is performed once by optical communication of the optical bus or by addition of electrical communication on the board. If you go around, you can achieve it.

In the above description, an example in which four processor elements are mounted on each processor board has been shown. However, in general, even if the number of m mounted elements is expanded, most of them are used for electrical or optical communication. It is clear that any number of times, at most once each, for a total of two communications, can communicate between any of the processor elements.

As described above, if there is an optical receiver capable of detecting a logical composite signal of a plurality of amplitude-modulated optical signals, it has a part of the function of a crossbar coupling network capable of arbitrarily coupling all the processor elements. An optical bus can be realized and can be used in a massively parallel computer.
No. 2608.

By the way, as shown in the above example, light emission /
In order to allow the light-receiving device to play a part of the function of the crossbar coupling network, it is necessary that a plurality of independent amplitude-modulated optical signals can be received by a plurality of light-receiving elements, that is, photodetector array, and output from the same output terminal. It is indispensable to be able to output a signal obtained by logically synthesizing the optical input signal (logic synthesized signal). In this case, instead of directly taking out a signal obtained by logically combining the outputs of a plurality of light receiving elements, each output of the light detecting element array, which is the light receiving element of the light emitting / light receiving device, is individually taken out and led to a processor element or the like to obtain a logic gate. In the method of performing logic synthesis using elements, wiring such as lead lines becomes enormous.

[0014]

As described above, each output of the photodetector array is individually taken out and input to the logic gate element, and a plurality of amplitude-modulated optical signals incident on the photodetector array are logically combined. The conventional method of obtaining the logic synthesis signal has a problem that wiring such as lead lines becomes enormous.

The present invention provides an optical receiver capable of obtaining a signal obtained by logically combining optical signals incident on a photodetecting element array without increasing wirings such as lead lines from the photodetecting element array. With the goal.

[0016]

In order to solve the above-mentioned problems, an optical receiver according to the present invention comprises a substrate and a plurality of photo-detecting elements arranged on the substrate in at least one direction at predetermined intervals. Photodetection element array, inductive common connection wiring for commonly connecting one end of each of the plurality of photodetection elements of the photodetection element array, and one end of each of the photodetection elements at both ends of the photodetection element array. The connected first and second terminating resistors, and means for converting an electrical signal obtained by detecting a plurality of optical signals incident on the photodetector array from at least one end of the common connection wiring into a logically synthesized signal. Be equipped with
An LC circuit network having a constant characteristic impedance is constituted by the photodetector array and the common connection wiring, and the resistance values of the first and second terminating resistors are made equal to the characteristic impedance of the LC circuit network. .

[0017]

The light detecting element such as a photodiode is equivalently represented by a parallel circuit of a high impedance constant current source that outputs a current proportional to the intensity of incident light and a capacitance. Therefore, in a so-called wired-OR circuit configuration in which each output terminal of the photodetector is simply connected to extract a logical composite signal from the voltage generated by the same load, the number of leads from the photodetector array is Although the output of the detection element is significantly reduced as compared with the case where the output is individually taken out, on the other hand, there is a problem that there are many reflection points where impedance matching cannot be achieved. When the optical signal is a low speed signal with a transmission rate of several tens of Mb / s or less,
Although there is no particular problem in such a wired-OR circuit configuration, when the optical signal is a high-speed signal having a transmission rate of 100 Mb / s or more, the reflected waves at the reflection points interfere with each other and the waveform of the logically synthesized signal is generated. The distortion increases.

On the other hand, in the optical receiver of the present invention, each output of the photodetector array is not simply connected to the load, but
An LC circuit network is configured by the capacitance generated when the photodetection element is formed on the substrate and the inductance of the inductive common connection wiring connecting each end of the photodetection element,
The characteristic impedance is made equal at any node (common connection point of photodetection elements) on the network. Further, terminating resistors are respectively connected to one ends of the photodetecting elements at both ends of the photodetecting element array, and the resistance value of these terminating resistors is made equal to the characteristic impedance of the LC network. Here, the capacitance of the photodetection element includes not only the intrinsic capacitance (junction capacitance, etc.) of the photodetection element itself, but also the stray capacitance by electrodes, wiring, etc. that are effectively added to this.

With such a configuration, the photocurrent output from each photodetecting element of the photodetecting element array is equally distributed at the element output terminals and output to the left and right of the LC network,
It is propagated to and absorbed by the terminating resistor without causing reflection at a node or the like. Therefore, if a signal obtained by logically combining a plurality of optical signals incident on the photodetector array is taken out from at least one end of the common connection wiring, a good logically combined signal without waveform distortion due to reflection can be obtained. Will be obtained.

Since the optical receiver according to the present invention is a wired-OR circuit in terms of logic circuit, the output logical combination signal is a logical sum (OR) signal or optical signal when the optical signal to be handled is positive logic. In the case of negative logic, it becomes a logical product (NAND) signal.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view and a sectional view of an optical receiver according to an embodiment of the present invention. In FIG. 1, a semiconductor substrate 10 is, for example, a semi-insulating InP substrate, on which a n-type conductive layer 11, an i-layer 12 made of InGaAs, and a p-type conductive layer 13 are stacked to form a pin photodiode 14-. i
j (i = 1, 2, ..., N, j = 1, 2, ..., M) are formed in a matrix array. The photodiodes 14-ij are insulated from each other by an insulating layer 15 formed on the substrate 11. Then, the anode electrode 16 is formed on the p-type conductive layer 13, and the inductive common connection wiring 17 for commonly connecting the anode electrodes 16 arranged in the row direction (the left-right direction in the drawing) is formed on the insulating layer 15. Has been formed. The n-type conductive layer 11 is a common cathode electrode 18 for bias application, which is formed on the substrate 10 along the row direction.
Respectively connected to.

The photodiodes 14-11, 14-1n, 14-21, at both ends in the row direction of the photodiode array.
One end (anode side) of each of 14-2n, ... 14-m1, 14-mn is connected to one end of the first and second terminating resistors 21, 22 via inductive external connection wirings 19, 20, respectively. ing. Here, the external connection wirings 19 and 20 have, for example, a line width equal to that of the common connection wiring 17 and a length that is half that of the common connection wiring 17, so that the value of its inductance is half that of the common connection wiring 17. Termination resistor 2
The other ends of 1 and 22 are connected to the ground ends 23 and 24, respectively. A reverse bias voltage Vb for the photodiode 14-ij is applied between the common cathode electrode 18 and the ground terminal 23.

On the other hand, the other end of the external connection wiring 20 and the ground end 2
4 is connected to the input end of the waveform shaping circuit 25. The waveform shaping circuit 25 is composed of, for example, an amplifier and a discriminator, and a signal obtained by logically combining the n pieces of amplitude-modulated optical signals 26-ij incident on the photodiode array arranged in the row direction is converted into a rectangular wave having a predetermined logical amplitude. This is for shaping, and is for binarizing the logic synthesis signal. In addition,
The waveform shaping circuit 25 may simply be a limiter amplifier or may be a circuit that amplifies the logic synthesis signal.

Next, the operation of the optical receiver of this embodiment will be described. 2 is a diagram showing the electrical connection relationship of the photodiode arrays arranged in the row direction of FIG. 1, and FIG. 3 is an equivalent circuit diagram thereof. As shown in FIGS. 2 and 3, the capacitances C of the photodiodes 14-1 to 14-1n
(Hereinafter, referred to as photodiode capacitance), the inductance L of the common connection wiring 17, and the external connection wirings 19 and 20.
And the common connection wiring 17 is divided into halves, a repetitive LC circuit network based on a circuit in which L / 2 is connected to the left and right of C is formed. I understand. R is a terminating resistor 21,
22 represents the resistance value of 22. As described above, the photodiode is equivalently represented by a parallel circuit of a constant current source and a capacitance, but is equivalent to a capacitive element in terms of high frequency, and its capacitance (hereinafter referred to as the photodiode capacitance) C Is given by the sum of the junction capacitance Cj and the stray capacitance Cp formed by an electrode or the like as in the following equation.

C = Cj + Cp (1) Here, for the junction capacitance Cj, the applied voltage (bias voltage) is V
When the pn junction capacitance is Cs and the potential difference between the pn junctions is φ when b and Vb = 0, it is expressed by the following equation.

Cj = Cs / (1-Vb / φ) ^1/2 (2) When C = Cj + Cp is satisfied in FIG. 3, the circuit of FIG. 2 applying the reverse bias voltage Vb to the photodiode and the LC circuit of FIG. The nets are electrically equivalent. In the repetitive LC network shown in FIG. 3, the cutoff frequency fc of the propagation signal
Is given by

Fc = 1 / π (LC) ^1/2 (3) In the frequency region lower than this cutoff frequency fc, the characteristic impedance Z of the LC network can be approximated by the following equation.

Z = (L / C) ^1/2 (4) Therefore, the characteristic impedance Z of the LC network shown in FIG.
Has a predetermined constant impedance (for example, 50Ω) in any connection line, and the terminating resistors 2 at both ends
If the value R of 1 and 22 is made equal to the characteristic impedance Z of the LC network, the photocurrent output from each photodiode 14-ij of the photodiode array is distributed in half from each node to both sides of the LC network. , Is propagated and absorbed to the terminating resistors 21 and 22 without causing reflection.
As a result, a signal obtained by logically combining a plurality of amplitude-modulated optical signals 26 entering the photodiode array does not cause waveform distortion due to reflection, and has a correct combined waveform of the original signal,
It is input to the waveform shaping circuit 25. Therefore, it is possible to reduce the identification error of the logic synthesis signal output in the waveform shaping circuit 25.

Here, the case where the input impedance of the waveform shaping circuit 25 is sufficiently larger than Z has been described, but when it is small, the terminating resistor 22 is set so that the combined impedance of the input impedance and the terminating resistor 22 becomes equal to Z. It goes without saying that you need to choose a value for.

Next, a specific design example is shown below. now,
When L = 0.1 nH and C = 0.4 pF in FIG. 3, the cutoff frequency fc is about 50 GHz, and the characteristic impedance Z has a value of 50 Ω which is constant with sufficient accuracy at 10 Gb / s or less. Also, the substrate 1 in FIG.
Assuming that the relative permittivity of 0 is 9, the substrate 10 for signals of 5 GHz
Since the wavelength inside is 20 mm, capacitance elements such as photodiodes are arranged at intervals of several mm or less.
For the analysis of the electrical characteristics of the C network, the lumped constant handling can be applied with sufficient accuracy. Therefore, Cp in equation (1)
Can include the stray capacitance of the connection wiring. Impedance matching can be achieved by terminating both ends of the LC network with terminating resistors 21 and 22 having a value of R = Z.
This is equivalent to connecting loads of the same impedance to the left and right of the node.

In FIG. 1, the spacing between the photodiodes 14-ij in the row direction (unit length of the common connection wiring 17) and the common connection wiring 17 and the external connection wirings 19 and 20 are set so that the inductance L has a desired value. The line width of is set to a value determined in advance by simulation or experimentally. Of these, the photodiode 14-ij
The spacing in the row direction of is set between 50 μm and 3 mm. The line width of the common connection layer 17 and the external connection wirings 19 and 20 is set to a width of 1 μm or more that can be formed by a normal photolithography process.

On the other hand, the photodiodes 1 at both ends in the row direction
4-11, 14-1n, 14-21, 14-2n, ... 1
When the signal transmission speed is about 10 Gp / s or less, the distance between the 4-m1, 14-mn and the terminating resistors 21 and 22, that is, the length of the external connection wirings 19 and 20 is accurate. It is not always necessary to be 1/2 of the row-direction spacing of the photodiodes, and there is no problem even if it is selected between 1 and 0 times the spacing of the photodiodes 14-ij in the row direction. In other words, the inductance of the external connection wirings 19 and 20 is preferably L / 2, but may be between 0 and L.

Generally, the photodiode has the formula (1)
As shown in (2), the junction capacitance is reduced by applying the reverse bias voltage Vb. On the other hand, in the optical receiver of the present embodiment, the characteristic impedance Z is calculated and designed in the vicinity of the center of the adjustment range of the photodiode capacitance, and there are processing errors in the LC network and variations in the photodiode characteristics between elements. At this time, the reverse bias voltage Vb is adjusted to adjust the value of the photodiode capacitance C so that the impedance matching is best achieved, that is, the characteristic impedance Z has a desired value in FIG.

Although the waveform shaping circuit 25 is connected to only one end of the LC network in the above embodiment, it may be connected to both ends. In that case, each output may be used independently, but when the waveform shaping circuit is an amplifier type, by adding the logical synthesis signals output from the waveform shaping circuits on both sides to the output of the optical receiver, The amplitude of the output logic synthesis signal can be made larger. Although the terminating resistors 21 and 22 are directly formed on the substrate 10 as film resistors in FIG. 1, they may be provided as external resistors by being drawn out of the substrate 10 via the waveguide of the impedance Z, or waveform shaping. It may be formed on the same integrated circuit as an external circuit such as a circuit.

In the optical receiver of the present invention, it is easy to set the cut-off frequency fc shown in equation (3) to a value sufficiently higher than the used frequency, but how is the characteristic impedance Z shown in equation (4)? It is important to set a desired value (for example, 50Ω). For this purpose, it is necessary to appropriately set the values of the photodiode capacitance C and the inductance L in FIG. Therefore, various embodiments for setting L and C to appropriate values will be described next. Figure 4
FIG. 2 is an enlarged plan view showing the photodiode 14-ij, the common connection wiring 17, the external connection wiring 19 (20) and the common cathode electrode 18 of FIG.

On the other hand, in the embodiment of FIG. 5, by increasing the width of the anode electrode 16 of the photodiode 14-ij, the connection between the n-type conductive layer 11 and the anode electrode 16 and between the anode electrode 16 and the common connection wiring 17 is increased. This is an example in which the capacitance between the wiring and the external connection wiring 19 (20) is increased. In addition, the embodiment of FIG.
A portion of the anode electrode 16 facing the photodiode 14-ij is projected toward the photodiode 14-ij.
In this example, the capacitance between the common cathode electrode 18 and the common cathode electrode 18 is increased.

By configuring as in the embodiments of FIGS. 5 and 6, the junction capacitance Cj of the photodiode 14-ij is obtained.
Even if is not sufficiently large, the photodiode capacitance C in FIG. 3 can be set to a desired value by increasing the stray capacitance Cp.

In the embodiment shown in FIG. 7, in addition to increasing the stray capacitance Cp of the photodiode 14-ij by the same method as that shown in FIG. 5, a diode 30 is provided in parallel with the photodiode 14-ij so that Cj is increased. This is an example in which the adjustment range of the photodiode capacitance C is widened by adjusting the bias voltage Vb ′ applied to the diode 31 via the adjacent common cathode electrode 18 at the same time as making it apparently large. The diode 30 is
It is assumed that light is shielded by a light shielding film (not shown) so that the capacitance does not change in response to light.

The method of the embodiment shown in FIG. 7 has the effect of not only widening the capacity adjustment range but also increasing the allowable range of manufacturing variations, and this can be expected to have advantages such as an improvement in manufacturing yield.

In the embodiment shown in FIG. 8, the photodiode 14-
This is an example in which the area of the n-type conductive layer 11 in ij is increased so that capacitance is also provided between the n-type conductive layer 11 and the wirings 17, 19 (20). Even in this case, the stray capacitance Cp can be increased and the photodiode capacitance C can be increased. Note that the embodiment of FIG. 8 is further expanded to increase the stray capacitance Cp by continuously forming the n-type conductive layer 11 on the substrate 10 without individually drawing out the n-type conductive layer 11 to the common cathode electrode 18. You may let me. In this case, the equivalent circuit is different from that in FIG. 3 in a strict sense, but it can be regarded as equivalent to that in FIG. 3 in the lumped constant approximation model.

In the embodiment shown in FIG. 9, the photodiode 14-
An insulating film 31 such as a SiO ₂ film or a SiN film is formed on the anode electrode 16 of ij, and a ground layer 32 is further formed on the insulating film 31, and the anode electrode 16, the insulating film 31 and the ground layer 32 form the MIM capacitor. It is an example of forming. Even in this case, the stray capacitance Cp can be increased and the photodiode capacitance C can be increased.

Needless to say, the method of increasing the stray capacitance Cp described in the embodiments of FIGS. 5 to 9 can be implemented by appropriately combining two to five in any combination.

When the above-mentioned method of increasing the stray capacitance Cp is used, the characteristic impedance Z of the LC network is lowered from the equation (4). On the other hand, in order to increase the characteristic impedance Z, the inductance L of the inductive common connection wiring 17 and the inductance L / 2 of the external connection wirings 19 and 20 may be increased. An example thereof is shown in FIGS.

The embodiment of FIG. 10 is an example in which the line widths of the common connection wiring 17 and the external connection wirings 19 and 20 are partially thinned to increase the inductances L and L / 2. If there is a concern that the direct current resistance of the wiring may increase by reducing the line width, the wiring thickness may be increased within a range that does not increase the stray capacitance Cp.

The embodiment of FIG. 11 is an example in which the common connection wiring 17 and the external connection wirings 19 and 20 are meandered to increase the inductances L and L / 2. Further, the embodiment of FIG. 12 is an example in which the common connection wiring 17 and the external connection wirings 19 and 20 are formed in a spiral shape to form a so-called spiral inductor, thereby increasing the inductances L and L / 2.

The present invention is not limited to the above-described embodiments, but can be implemented with various modifications as follows. For example, in the above embodiment, the photodiode 14-
Although a back surface input type photodiode in which light is incident from the substrate 10 side is shown as ij, a front surface input type photodiode in which light is incident from the side opposite to the substrate may be used.
Further, the pn junction of the photodiode may have a relationship opposite to that shown in the drawing.

The material of the substrate 10 is not limited to InP, and GaA may be changed depending on the wavelength of the optical signal.
s, GaP, Ga, Si, etc. can be appropriately used,
Accordingly, the material forming the pn junction of the photodiode may be different from InGaP.

Further, although the matrix array, that is, a two-dimensional array is shown as the photodiode array in FIG. 1, it is needless to say that the present invention can be applied even when the photodiode array is a one-dimensional array in which a plurality of photodiodes are arranged in a row. Absent. Further, the present invention can be applied not only to an array of photodiodes alone, but also to a composite element array arranged in a ring shape around other elements having other functions, for example.

A phototransistor may be used as the photodetector, and in general, any current output photodetector such as a photodiode or phototransistor can be used in principle.

[0050]

As described above, according to the optical receiver of the present invention, it is possible to obtain a good logic synthesized signal without waveform distortion for a plurality of high-speed optical signal inputs without increasing the number of wirings such as external leads. Can be obtained.

Therefore, the optical receiver according to the present invention can realize a high-performance optical bus having a function close to that of a crossbar network in a bus connection of, for example, a massively parallel computer, and can greatly improve the system performance. Can be planned.
Further, since the optical receiver of the present invention has a small number of wires and is relatively simple and compact, the optical bus can have excellent characteristics such as spatial multiplicity of optical interconnection. It also contributes to the cost reduction of optical buses.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view showing a configuration of an optical receiver according to an embodiment of the present invention.

FIG. 2 is a diagram showing an electric circuit configuration of the embodiment.

FIG. 3 is a diagram showing an LC circuit network which is an equivalent circuit of FIG.

FIG. 4 is an enlarged plan view of an essential part of FIG.

FIG. 5 is an enlarged plan view of an essential part in another embodiment of the present invention.

FIG. 6 is an enlarged plan view of an essential part in another embodiment of the present invention.

FIG. 7 is an enlarged plan view of an essential part in another embodiment of the present invention.

FIG. 8 is a cross-sectional view of essential parts in another embodiment of the present invention.

FIG. 9 is a cross-sectional view of essential parts in another embodiment of the present invention.

FIG. 10 is an enlarged plan view of an essential part in another embodiment of the present invention.

FIG. 11 is an enlarged plan view of an essential part in another embodiment of the present invention.

FIG. 12 is an enlarged plan view of an essential part in another embodiment of the present invention.

FIG. 13 is a configuration diagram of a ring-shaped optical bus.

14 is a diagram showing an arrangement of light emitting elements and light receiving elements in the light emitting / receiving device on each processor board in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Substrate 11 ... N-type conductive layer 12 ... i-layer 13 ... P-type conductive layer 14-ij ... Photodiode 15 ... Insulating layer 16 ... Anode electrode 17 ... Common connection wiring 18 ... Common cathode electrode 19, 20 ... External connection wiring 21, 22 ... Termination resistors 23, 24 ... Grounding end 25 ... Waveform shaping circuit 26-ij ... Amplitude modulated optical signal 30 ... Diode 31 ... Insulating film 32 ... Grounding layer 100-10n ... Processor board 110-11n ... Light emitting / receiving device 121-124 ... Reflector

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04B 10/04 10/06 10/00 // H01L 31/10 H01L 31/10 G

Claims (1)

[Claims] 1. A substrate, a photodetector array provided on the substrate and having a plurality of photodetectors arranged in a predetermined interval in at least one direction, and a plurality of photodetector elements of the photodetector array. At least one of inductive common connection wiring for commonly connecting each one end, first and second terminating resistors respectively connected to each one end of the photodetection elements at both ends of the photodetection element array, and at least the common connection wiring A plurality of optical signals that are incident on the photodetector array from one end are converted into a logically combined signal, and the photodetector array and the common connection wiring predetermine the signal. An optical receiver having an LC circuit network having a constant characteristic impedance and the resistance values of the first and second terminating resistors being equal to the characteristic impedance of the LC circuit network.