JPH07120761B2 - Semiconductor integrated circuit with built-in light receiving element - Google Patents

Description

The present invention relates to a semiconductor integrated circuit with a built-in light receiving element, and more particularly to a light receiving element for converting an optical signal into an electric signal and impedance conversion of an electric signal generated in the light receiving element, Both of the electronic circuits for signal amplification are integrated on the same chip,
The present invention relates to a semiconductor integrated circuit with a built-in light receiving element used in a photocoupler realized by optically combining with a light emitting element.

[Conventional technology]

Conventionally, a semiconductor integrated circuit with a built-in light receiving element having a sectional structure shown in FIG. 3 has been used on the light receiving side of this type of photocoupler. That is, in order to realize a photo coupler having a high common-mode noise signal rejection ratio (CMRR), an indium oxide film 46 having a light-transmitting property and a conductivity is formed on the surface of the light receiving element composed of the P-type semiconductor layer 35 and the N-type epitaxial layer 32-1. By covering with a substance like this and grounding this substance, a shield is provided between the input and output of the photocoupler. (Such a conventional example is described, for example, in Japanese Patent Laid-Open No. 50-92691 as an optical coupling isolator (applicant Yokogawa Hewlett-Packard Co.).) [Problems to be Solved by the Invention] The conventional semiconductor integrated circuit with a built-in light receiving element for a high CMRR photocoupler has the following drawbacks. High CMRR
Indium oxide is a typical substance that shields the input and output of the photocoupler. In FIG. 3, the indium oxide film 46 is deposited on the insulating film 45 and then etched into a desired pattern. Then, the indium oxide film 46 is connected to the reference potential source terminal 41 to shield the input-output capacitance C _IO with respect to the light emitting element portion on the input side.

However, the material of indium oxide is expensive. Moreover, there is a special aspect such as using hydrochloric acid during etching,
The manufacturing process for forming this portion cannot be shared with the manufacturing process for a general bipolar integrated circuit. Therefore, in the conventional example, the unit price of the pellet is increased for the above two reasons, and the market price of the final product, the high CMRR photocoupler, is about one digit higher than that of the non-shielded type.

[Means for solving problems]

In the semiconductor integrated circuit with a built-in light receiving element according to the present invention, an N-type semiconductor region provided around a semiconductor substrate except a surface thereof is surrounded by a P-type semiconductor region, and a P-type semiconductor layer provided in the N-type semiconductor region. And a PN junction photodiode having the P-type semiconductor layer and an electrode wiring connecting the P-type semiconductor region, means for applying a reference potential to the P-type semiconductor region and the P-type semiconductor layer, and the PN And an electronic circuit including a bipolar transistor for amplifying an output signal of the junction photodiode.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a main part of the first embodiment of the present invention.

In this embodiment, a P-type semiconductor region (P-type insulating isolation region) is formed around the periphery except the surface of a semiconductor substrate in which N-type upper epitaxial layers 2-1, 2-2, ... Are deposited on a P-type semiconductor base plate 1 made of silicon. 3-1 and 3-2 and the N-type semiconductor region (N-type epitaxial layer 2-1) surrounded by the P-type semiconductor base plate 1) and N
A PN junction photodiode including a P-type semiconductor layer 5 provided in the type epitaxial layer 2-1 and an electrode wiring 9 connecting the P-type semiconductor layer 5 and the P-type semiconductor region described above,
A bipolar transistor (N ⁺ type emitter layer 6, P type base layer 6) for amplifying the output signal of the PN junction photodiode.
And an N type epitaxial layer 2-2. ) And an electronic circuit including.

The P-type semiconductor layer 5 can be formed in the same process as the P-type base layer 4. The PN junction photodiode has an N-type epitaxial layer 2-1 as a cathode region, a P-type semiconductor layer 5, a P-type insulating isolation region 3-2 and a P-type semiconductor base plate 1 as an anode, and this anode is used as a ground terminal or the like. Shielded by connecting to the reference potential source terminal of. That is, P
The type semiconductor layer 5 is located at the most sensitive portion to electromagnetic wave induction in the input side and output side circuits of the photocoupler, and effectively shields the input and output. In this example, PN
Although all the junctions can function as photodiodes, a portion not used as a light receiving element may be covered with a light shielding film (not shown) such as aluminum. In other words, a transparent insulating film, for example, a SiO ₂ film may be attached to the one shown in the drawing by the CVD method, and aluminum may be selectively deposited thereon to a thickness of 50 to 100 nm. Then, this light-shielding film may be connected to the reference potential source terminal, and the shield effect will be perfect.

Such a PN junction photodiode has an advantage that the photoelectric conversion efficiency is very good because the anode region is provided in the periphery. Note that the increase in capacitance due to the increase in the area of the PN junction can be dealt with by reducing the size of the light receiving element. The thickness of the N-type epitaxial layer 2, the specific resistance and the depth of the P-type base layer 4 are determined by weighing both the center wavelength of incident light and the response characteristics of the NPN transistor.

In this embodiment, the P-type semiconductor layer 5 and the P-type insulating isolation region 3-2 are used.
May be directly connected.

FIG. 2 is a vertical sectional view of a semiconductor chip showing a second embodiment of the present invention and a main part. The N ⁺ type buried layer 11-2 lowers the collector series resistance of the NPN transistor, and the N ⁺ type buried layer 11-1
The PN junction photodiode and the P-type semiconductor base plate 1 are electrically separated. The P ⁺ type buried layer 12-2 forms a PN junction photodiode by a PN junction formed between the P ⁺ type buried layer 12-2 and the N type epitaxial layer 2-1. The anode region of the P ⁺ type buried layer 12-2 is a P type insulating isolation region 3'-4, The series resistance can be remarkably reduced by diffusing and forming 3'-5 so as to hit the P ⁺ type buried layer 12-2. The elements described above are the PN junction photodiode and
This is to improve the frequency characteristics and noise characteristics of the NPN transistor, and this embodiment has the advantages of low noise and high-speed operation.

〔The invention's effect〕

As described above, according to the present invention, a P-type semiconductor layer is provided in an N-type semiconductor region surrounded by a P-type semiconductor region, and the P-type semiconductor region is connected to the P-type semiconductor region to provide a reference potential. Since the element can be shielded, it can be realized by using an ordinary manufacturing process of a bipolar integrated circuit. Therefore, there is an effect that the semiconductor integrated circuit with a built-in light receiving element can be improved in quality and reduced in price.

[Brief description of drawings]

FIG. 1, FIG. 2 and FIG. 3 are cross-sectional views of a semiconductor chip showing the main parts of a first embodiment, a second embodiment and a conventional example of the present invention. 1,31 ... P-type semiconductor base plate, 2-1,2-2,32-1,32-2
... N-type epitaxial layers, 3-1 to 3-3, 3'-1
~ 3'-3, 33-1 to 33-2 ... P-type insulation isolation region, 4,
34 …… N ⁺ type emitter layer, 5,35 …… P type semiconductor layer, 6,36…
… P-type base layer, 7,37 …… N ⁺ -type collector contact layer,
8,38 …… N ⁺ type cathode contact layer, 9 …… electrode wiring,
10,39 …… Cathode electrode, 11-1, 11-2 …… N ⁺ type buried layer, 12-1 to 12-4 …… P ⁺ type buried layer, 40 …… Anode electrode, 41 …… Reference Potential source terminal, 42 ... Collector electrode, 43 ...
… Base electrode, 44 …… Emitter electrode, 45 …… Insulating film, 46
…… Indium oxide film.

Claims (1)

[Claims] 1. An N-type semiconductor region provided around a semiconductor substrate except a surface thereof with a P-type semiconductor region, a P-type semiconductor layer provided in the N-type semiconductor region, and the P-type semiconductor layer. A PN junction photodiode having an electrode wiring connecting the P-type semiconductor region; a means for applying a reference potential to the P-type semiconductor region and the P-type semiconductor layer;
A semiconductor integrated circuit with a built-in light receiving element, comprising: an electronic circuit including a bipolar transistor for amplifying an output signal of a PN junction photodiode.